From 7609017dc3112337c3098e7d04dcd437549f8b14 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Tue, 20 Apr 2010 22:34:09 +0000 Subject: Because of the EMMS problem, right now we have to support user-defined operations that use MMX register types, but the compiler shouldn't generate them on its own. This adds a Synthesizable abstraction to represent this, and changes the vector widening computation so it won't produce MMX types. (The motivation is to remove noise from the ABI compatibility part of the gcc test suite, which has some breakage right now.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp') diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 11dca398b7..5c3992ea06 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -720,7 +720,7 @@ void TargetLowering::computeRegisterProperties() { unsigned NElts = VT.getVectorNumElements(); for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { EVT SVT = (MVT::SimpleValueType)nVT; - if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && + if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && SVT.getVectorNumElements() > NElts && NElts != 1) { TransformToType[i] = SVT; ValueTypeActions.setTypeAction(VT, Promote); -- cgit v1.2.3