From d64ba3ee62cc854218d9b76b9420493d82313d06 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 9 Jun 2010 19:00:55 +0000 Subject: It's an error to translate this: %reg1025 = %reg1024 ... %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 into this: %reg1025 = %reg1024 ... %reg1027 = EXTRACT_SUBREG %reg1025, 4 %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 The problem here is that SUBREG_TO_REG is there to assert that an implicit zext occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG here, it will give us the value after the , not the original value of %reg1024 before . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105741 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/OptimizeExts.cpp | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'lib/CodeGen/OptimizeExts.cpp') diff --git a/lib/CodeGen/OptimizeExts.cpp b/lib/CodeGen/OptimizeExts.cpp index 41fc204074..38f3cf7e41 100644 --- a/lib/CodeGen/OptimizeExts.cpp +++ b/lib/CodeGen/OptimizeExts.cpp @@ -118,6 +118,26 @@ bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB, continue; } + // It's an error to translate this: + // + // %reg1025 = %reg1024 + // ... + // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 + // + // into this: + // + // %reg1025 = %reg1024 + // ... + // %reg1027 = EXTRACT_SUBREG %reg1025, 4 + // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 + // + // The problem here is that SUBREG_TO_REG is there to assert that an + // implicit zext occurs. It doesn't insert a zext instruction. If we allow + // the EXTRACT_SUBREG here, it will give us the value after the , + // not the original value of %reg1024 before . + if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) + continue; + MachineBasicBlock *UseMBB = UseMI->getParent(); if (UseMBB == MBB) { // Local uses that come after the extension. -- cgit v1.2.3