From 5711564b091c39188775aee2768ad36a9b9a99b2 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 22 Dec 2009 21:48:20 +0000 Subject: Allow explicit %reg0 operands beyond what the .td file describes. ARM uses these to indicate predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91922 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineVerifier.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/CodeGen/MachineVerifier.cpp') diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 917d0535b2..959269f85f 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -553,7 +553,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { report("Explicit operand marked as implicit", MO, MONum); } } else { - if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) + // ARM adds %reg0 operands to indicate predicates. We'll allow that. + if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) report("Extra explicit operand on non-variadic instruction", MO, MONum); } -- cgit v1.2.3