From 977679d6034791fd48a344e5b990503ba50fc242 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 7 Jan 2012 03:02:36 +0000 Subject: Added a late machine instruction copy propagation pass. This catches opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LLVMTargetMachine.cpp | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) (limited to 'lib/CodeGen/LLVMTargetMachine.cpp') diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 62227fd4d6..7fd089a5db 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -452,23 +452,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, if (addPostRegAlloc(PM)) printAndVerify(PM, "After PostRegAlloc passes"); - PM.add(createExpandPostRAPseudosPass()); - printAndVerify(PM, "After ExpandPostRAPseudos"); - // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); printAndVerify(PM, "After PrologEpilogCodeInserter"); - // Run pre-sched2 passes. - if (addPreSched2(PM)) - printAndVerify(PM, "After PreSched2 passes"); - - // Second pass scheduler. - if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) { - PM.add(createPostRAScheduler(getOptLevel())); - printAndVerify(PM, "After PostRAScheduler"); - } - // Branch folding must be run after regalloc and prolog/epilog insertion. if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) { PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); @@ -481,6 +468,26 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, printNoVerify(PM, "After TailDuplicate"); } + // Copy propagation. + if (getOptLevel() != CodeGenOpt::None) { + PM.add(createMachineCopyPropagationPass()); + printNoVerify(PM, "After copy propagation pass"); + } + + // Expand pseudo instructions before second scheduling pass. + PM.add(createExpandPostRAPseudosPass()); + printNoVerify(PM, "After ExpandPostRAPseudos"); + + // Run pre-sched2 passes. + if (addPreSched2(PM)) + printNoVerify(PM, "After PreSched2 passes"); + + // Second pass scheduler. + if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) { + PM.add(createPostRAScheduler(getOptLevel())); + printNoVerify(PM, "After PostRAScheduler"); + } + PM.add(createGCMachineCodeAnalysisPass()); if (PrintGCInfo) -- cgit v1.2.3