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* Tidy up a bit. No functional change.Jim Grosbach2013-04-059-259/+261
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178915 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the optimization about promoting vector-element-access with symbolic ↵Shuxin Yang2013-04-051-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | index. This optimization is unstable at this moment; it 1) block us on a very important application 2) PR15200 3) test6 and test7 in test/Transforms/ScalarRepl/dynamic-vector-gep.ll (the CHECK command compare the output against wrong result) I personally believe this optimization should not have any impact on the autovectorized code, as auto-vectorizer is supposed to put gather/scatter in a "right" way. Although in theory downstream optimizaters might reveal some gather/scatter optimization opportunities, the chance is quite slim. For the hand-crafted vectorizing code, in term of redundancy elimination, load-CSE, copy-propagation and DSE can collectively achieve the same result, but in much simpler way. On the other hand, these optimizers are able to improve the code in a incremental way; in contrast, SROA is sort of all-or-none approach. However, SROA might slighly win in stack size, as it tries to figure out a stretch of memory tightenly cover the area accessed by the dynamic index. rdar://13174884 PR15200 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178912 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/13551789> Fix a race in the LockFileManager.Douglas Gregor2013-04-051-5/+32
| | | | | | | | | It's possible for the lock file to disappear and the owning process to return before we're able to see the generated file. Spin for a little while to see if it shows up before failing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178909 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/13551789> Fix yet another race in unique_file.Douglas Gregor2013-04-051-3/+1
| | | | | | | | | | | If the directory that will contain the unique file doesn't exist when we tried to create the file, but another process creates it before we get a chance to try creating it, we would bail out rather than try to create the unique file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178908 91177308-0d34-0410-b5e6-96231b3b80d8
* [Support][FileSystem] Fix identify_magic for big endian ELF.Michael J. Spencer2013-04-051-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178905 91177308-0d34-0410-b5e6-96231b3b80d8
* Define versions of Section that are explicitly marked as little endian.Rafael Espindola2013-04-051-34/+34
| | | | | | These should really be templated like ELF, but this is a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178896 91177308-0d34-0410-b5e6-96231b3b80d8
* Added two debug logging messages to VisitInstructionsTopDown to match ↵Michael Gottesman2013-04-051-0/+4
| | | | | | VisitInstructionsBottomUp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178895 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct in getSection and getSection64.Rafael Espindola2013-04-051-86/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178894 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleaned up whitespace and made debug logging less verbose.Michael Gottesman2013-04-051-114/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178893 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 178851 as it broke buildbotsRenato Golin2013-04-051-161/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178883 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for numeric displacement expressions in bracketedChad Rosier2013-04-051-64/+246
| | | | | | | | | | | | | | | | | | | | | | | memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
* [Support] Disable assertion dialogs from the MSVC debug CRTReid Kleckner2013-04-051-0/+22
| | | | | | | | | | | | | | | | Summary: Sets a report hook that emulates pressing "retry" in the "abort, retry, ignore" dialog box that _CrtDbgReport normally raises. There are many other ways to disable assertion reports, but this was the only way I could find that still calls our exception handler. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178880 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't fetch pointers from a InMemoryStruct.Rafael Espindola2013-04-051-9/+18
| | | | | | | | InMemoryStruct is extremely dangerous as it returns data from an internal buffer when the endiannes doesn't match. This should fix the tests on big endian hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178875 91177308-0d34-0410-b5e6-96231b3b80d8
* Respect Addend when processing MCJIT relocations to local/global symbols.Ulrich Weigand2013-04-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the RuntimeDyldELF::processRelocationRef routine finds the target symbol of a relocation in the local or global symbol table, it performs a section-relative relocation: Value.SectionID = lsi->second.first; Value.Addend = lsi->second.second; At this point, however, any Addend that might have been specified in the original relocation record is lost. This is somewhat difficult to trigger for relocations within the code section since they usually do not contain non-zero Addends (when built with the default JIT code model, in any case). However, the problem can be reliably triggered by a relocation within the data section caused by code like: int test[2] = { -1, 0 }; int *p = &test[1]; The initializer of "p" will need a relocation to "test + 4". On platforms using RelA relocations this means an Addend of 4 is required. Current code ignores this addend when processing the relocation, resulting in incorrect execution. Fixed by taking the Addend into account when processing relocations to symbols found in the local or global symbol table. Tested on x86_64-linux and powerpc64-linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178869 91177308-0d34-0410-b5e6-96231b3b80d8
* Buildbot fix for r178851: mistake was in wrong ↵Stepan Dyatkovskiy2013-04-051-1/+1
| | | | | | TargetRegisterInfo::getRegClass usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178854 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated ↵Stepan Dyatkovskiy2013-04-051-10/+161
| | | | | | | | | | | | | | | | | | | instruction vldmia at incorrect position". Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass. It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4 But it also tracks conflicts between different register classes (e.g. D2 and S5). For more details see: Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824 LLVM Commits discussion: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SchedMachineModel for the PPC G5Hal Finkel2013-04-052-10/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SchedMachineModel for the PPC A2Hal Finkel2013-04-052-2/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-052-24/+67
| | | | | | | | | | | | | | | | | | | | This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer2013-04-054-32/+67
| | | | | | descriptions for compares git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-054-5/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable DFSResult for ConvergingScheduler.Andrew Trick2013-04-051-2/+0
| | | | | | | | For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178822 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler: format DEBUG output.Andrew Trick2013-04-051-22/+17
| | | | | | | I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178821 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Pass OperandValueKind information to the cost modelArnold Schwaighofer2013-04-041-2/+13
| | | | | | | | | | | | Pass down the fact that an operand is going to be a vector of constants. This should bring the performance of MultiSource/Benchmarks/PAQ8p/paq8p on x86 back. It had degraded to scalar performance due to my pervious shift cost change that made all shifts expensive on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178809 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer2013-04-041-0/+29
| | | | | | | | | | | | SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer2013-04-045-12/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: revert 178722 for now.Manman Ren2013-04-043-15/+4
| | | | | | | | | | | | | | There is a difference for FORM_ref_addr between DWARF 2 and DWARF 3+. Since Eric is against guarding DWARF 2 ref_addr with DarwinGDBCompat, we are still in discussion on how to handle this. The correct solution is to update our header to say version 4 instead of version 2 and update tool chains as well. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178806 91177308-0d34-0410-b5e6-96231b3b80d8
* typoAdrian Prantl2013-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178804 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the current PPC BCL definition to BCLalwaysHal Finkel2013-04-043-5/+5
| | | | | | | | | | | | BCL is normally a conditional branch-and-link instruction, but has an unconditional form (which is used in the SjLj code, for example). To make clear that this BCL instruction definition is specifically the special unconditional form (which does not meaningfully take a condition-register input), rename it to BCLalways. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel2013-04-041-0/+27
| | | | | | | | The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-041-0/+2
| | | | | | | | | | | | | | | It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
* Reassociate: Avoid iterator invalidation.Benjamin Kramer2013-04-041-7/+12
| | | | | | | | OpndPtrs stored pointers into the Opnd vector that became invalid when the vector grows. Store indices instead. Sadly I only have a large testcase that only triggers under valgrind, so I didn't include it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178793 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add bru instruction.Richard Osborne2013-04-041-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-044-34/+46
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen2013-04-041-46/+103
| | | | | | | | | | | | | | | | | The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
* FormattingEli Bendersky2013-04-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178771 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-041-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178763 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix wrong address when substituting ENDIFVincent Lejeune2013-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-044-5/+35
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178737 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: according to DWARF 2, FORM_ref_addr the same size as an address onManman Ren2013-04-043-4/+15
| | | | | | | | | | | | the target system. It was hard-coded to 4 bytes before. I can't get llvm to generate a ref_addr on a reasonably sized testing case. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178722 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored out the helper method FindPredecessorAutoreleaseWithSafePath from ↵Michael Gottesman2013-04-031-25/+45
| | | | | | | | ObjCARCOpt::OptimizeReturns. Now ObjCARCOpt::OptimizeReturns is easy to read and reason about. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178715 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored out the helper function FindPredecessorRetainWithSafePath from ↵Michael Gottesman2013-04-031-18/+32
| | | | | | ObjCARCOpt::OptimizeReturns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178714 91177308-0d34-0410-b5e6-96231b3b80d8
* Small cleanups.Michael Gottesman2013-04-031-14/+14
| | | | | | | | Cleaned up trailing whitespace and added extra slashes in front of a function level comment so that it follow the convention of having 3 slashes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178712 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactored out a part of ObjCARCOpt::OptimizeReturns into its own method ↵Michael Gottesman2013-04-031-22/+33
| | | | | | HasSafePathToPredecessorCall. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178710 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed an old comment.Michael Gottesman2013-04-031-7/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178709 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up arc annotations by moving the top/bottom BB annotations into ↵Michael Gottesman2013-04-031-58/+46
| | | | | | | | conditional macros that no-op in Release mode instead of #ifdef sections of the code. This is to follow the example of the DEBUG macro. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178705 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Vector shifts are expensive in most casesArnold Schwaighofer2013-04-031-0/+42
| | | | | | | | | | | | | | The default logic does not correctly identify costs of casts because they are marked as custom on x86. For some cases, where the shift amount is a scalar we would be able to generate better code. Unfortunately, when this is the case the value (the splat) will get hoisted out of the loop, thereby making it invisible to ISel. radar://13130673 radar://13537826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178703 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178675 91177308-0d34-0410-b5e6-96231b3b80d8
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