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* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
* some comment fix for X86 and ARMJia Liu2012-02-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.Evan Cheng2012-02-071-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin fleshing out more convenience predicates in llvm::Triple andChandler Carruth2012-02-051-17/+7
| | | | | | | | | | convert at least one client over to use them. Subsequent patches both to LLVM and Clang will try to convert more people over to a common set of predicates. This round of predicates is focused on OS-categorization predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149815 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-0/+24
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is ↵Craig Topper2012-01-101-4/+2
| | | | | | the final piece to remove the AVX hack that disabled SSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147843 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. ↵Craig Topper2012-01-101-4/+0
| | | | | | AVX is now an SSE level and no longer disables SSE checks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147842 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-101-6/+6
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. ↵Craig Topper2012-01-091-21/+15
| | | | | | Predicate functions have been altered to maintain previous names and behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147770 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hasSSE1orAVX(). It's the same as hasXMM().Evan Cheng2011-12-091-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146246 91177308-0d34-0410-b5e6-96231b3b80d8
* Many of the SSE patterns should not be selected when AVX is available. This ↵Evan Cheng2011-12-081-0/+1
| | | | | | | | | | | | | | | | | | | led to the following code in X86Subtarget.cpp if (HasAVX) X86SSELevel = NoMMXSSE; This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected. However, this breaks instructions which do not have AVX variants. The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX(). Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change. However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case, the prefetch instructions. rdar://10538297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XOP feature flag.Jan Sjödin2011-12-021-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
* Add methods for querying minimum SSE version along with AVX. Simplifies all ↵Craig Topper2011-11-221-0/+4
| | | | | | the places that had to check a version of SSE and AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145053 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics and feature flag for read/write FS/GS base instructions. Also ↵Craig Topper2011-10-301-0/+8
| | | | | | add AVX2 feature flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NaClModeDavid Meyer2011-10-181-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-141-0/+4
| | | | | | processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r141854 because it was causing failures:Bill Wendling2011-10-131-4/+0
| | | | | | | | | | | | | | | | | http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-131-0/+4
| | | | | | processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-111-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-091-2/+6
| | | | | | disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-031-0/+8
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-0/+8
| | | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman2011-08-261-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi2011-07-201-1/+2
| | | | | | to appease test/CodeGen/X86 on cygwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore old behavior. Always auto-detect features unless cpu or features are ↵Evan Cheng2011-07-081-1/+1
| | | | | | specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134757 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Mode64Bit feature and sink it down to MC layer.Evan Cheng2011-07-071-7/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-1/+4
| | | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-3/+3
| | | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-231-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-191-3/+7
| | | | | | predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar2011-04-191-7/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Add getTargetTriple() accessor.Daniel Dunbar2011-04-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129812 91177308-0d34-0410-b5e6-96231b3b80d8
* Stack alignment is 16 bytes on FreeBSD/i386 too.Roman Divacky2011-02-221-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126226 91177308-0d34-0410-b5e6-96231b3b80d8
* The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.Duncan Sands2011-02-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126130 91177308-0d34-0410-b5e6-96231b3b80d8
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-171-3/+1
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace.NAKAMURA Takumi2011-02-171-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125746 91177308-0d34-0410-b5e6-96231b3b80d8
* Patches to build EFI with Clang/LLVM. By Carl Norum.Evan Cheng2011-02-011-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124639 91177308-0d34-0410-b5e6-96231b3b80d8
* Formalize the notion that AVX and SSE are non-overlapping extensions from ↵Nate Begeman2010-12-101-0/+2
| | | | | | the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for the x86 popcnt instruction.Benjamin Kramer2010-12-041-0/+4
| | | | | | | | - Also adds a new POPCNT subtarget feature that is currently enabled if the target supports SSE4.2 (nehalem) or SSE4A (barcelona). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
* Jim Asked us to move DataLayout on ARM back to the most specialized classes. DoRafael Espindola2010-10-031-14/+0
| | | | | | | | so and also change X86 for consistency. Investigating if this can be improved a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Fix Cygwin's TD.NAKAMURA Takumi2010-09-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly emit __chkstk call instead of __alloca on non-mingw windows targets.Anton Korobeynikov2010-09-021-0/+4
| | | | | | Patch by Cameron Esfahani! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
* Add x86 CLMUL (Carry-less multiplication) cpu featureBruno Cardoso Lopes2010-07-231-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the X86 backend use Triple instead of a string and some enums.Eric Christopher2010-07-051-18/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel doesn't yet handle callee-pop functions.Dan Gohman2010-05-271-0/+4
| | | | | | | To support this, move IsCalleePop from X86ISelLowering to X86Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
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