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path: root/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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* Add more const qualifiers for LLVM IR pointers in CodeGen.Dan Gohman2010-04-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
* vldm/vstm can only do up to 16 double-word registers at a time.Jim Grosbach2010-03-261-1/+5
| | | | | | Radar 7797856 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
* pr6652: Use LDM to restore PC to the return address on ARMv4.Bob Wilson2010-03-201-6/+11
| | | | | | | Patch by John Tytgat! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant writeback flag in ARM addressing mode 5.Bob Wilson2010-03-161-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the writeback flag from ARM's address mode 4. Now that we have separateBob Wilson2010-03-161-2/+1
| | | | | | | instructions for ld/st with writeback, the flag is completely redundant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
* Wrap a long line and add some parens to be consistent.Bob Wilson2010-03-161-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98596 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-84/+99
| | | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine the code to build VLDM and VSTM instructions, since they areBob Wilson2010-03-131-16/+14
| | | | | | | mostly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98402 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. No functional changes.Bob Wilson2010-03-121-15/+16
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* pr6480: Don't try producing ld/st-multiple instructions when the address isBob Wilson2010-03-041-0/+5
| | | | | | | | | an undef value. This is only going to come up for bugpoint-reduced tests -- correct programs will not access memory at undefined addresses -- so it's not worth the effort of doing anything more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
* Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understandJakob Stoklund Olesen2010-02-241-1/+9
| | | | | | | <undef> operands, and can cause scavenger failures when it translates <kill,undef> to <kill>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97046 91177308-0d34-0410-b5e6-96231b3b80d8
* Load / store multiple instructions cannot load / store sp. Sorry, can't come ↵Evan Cheng2010-02-121-1/+2
| | | | | | up with a reasonable test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't fold insufficiently aligned ldr/str into ldm/stm instructions.Jakob Stoklund Olesen2010-01-141-0/+12
| | | | | | | | | | | | | An unaligned ldr causes a trap, and is then emulated by the kernel with awesome performance. The darwin kernel does not emulate unaligned ldm/stm Thumb2 instructions, so don't generate them. This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2. Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably also a bad idea, but that is beyond the scope of this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93393 91177308-0d34-0410-b5e6-96231b3b80d8
* Move kill flags when the same register occurs more than once in a sequence.Jakob Stoklund Olesen2009-12-231-1/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92058 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle undef operands properly.Jakob Stoklund Olesen2009-12-231-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92054 91177308-0d34-0410-b5e6-96231b3b80d8
* Make insert position available to MergeOpsUpdate.Jakob Stoklund Olesen2009-12-231-24/+25
| | | | | | | Rearrange arguments. No functional changes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92053 91177308-0d34-0410-b5e6-96231b3b80d8
* Perform kill flag calculations in new method. No functional changes.Jakob Stoklund Olesen2009-12-231-12/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92052 91177308-0d34-0410-b5e6-96231b3b80d8
* Move repeated code to a new method. No functional change.Jakob Stoklund Olesen2009-12-231-17/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92051 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bunch of little errors that Clang complains about when its being pedanticDouglas Gregor2009-12-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91764 91177308-0d34-0410-b5e6-96231b3b80d8
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-3/+3
| | | | | | | Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
* When expanding t2STRDi8 r, r to two stores, add kill markers correctly.Evan Cheng2009-11-141-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-46/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | | VISIBILITY_HIDDEN removal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-2/+2
| | | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
* Load / store multiple was missing opportunites when the load / store bundles ↵Evan Cheng2009-10-221-0/+3
| | | | | | are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ld/st multiples to explicitly model the writeback to base register. ↵Evan Cheng2009-10-011-3/+20
| | | | | | This fixes most of the -ldstopti-before-sched2 regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.Evan Cheng2009-09-291-0/+4
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* Enable pre-regalloc load / store multiple pass for Thumb2.Evan Cheng2009-09-271-55/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comment.Evan Cheng2009-09-261-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82836 91177308-0d34-0410-b5e6-96231b3b80d8
* Code clean up and prepare for Thumb2 support. No functionality changes.Evan Cheng2009-09-251-21/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
* Update register class references to use the global constant ↵Jim Grosbach2009-09-111-1/+1
| | | | | | ARM::*RegisterClass names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-6/+2
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+4
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* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
* Code refactoring. No functionality change.Evan Cheng2009-08-081-22/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-4/+16
| | | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-041-6/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 does not have ib (increment before) and da (decrement after) forms of ↵Evan Cheng2009-08-041-4/+10
| | | | | | ldm / stm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78057 91177308-0d34-0410-b5e6-96231b3b80d8
* Load / store multiple pass fixes for Thumb2. Not enabled yet.Evan Cheng2009-08-041-76/+85
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78031 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-3/+3
| | | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-111-1/+1
| | | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a bogus assertion.Evan Cheng2009-07-101-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75206 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for load / store multiple opt pass Thumb2 support ↵Evan Cheng2009-07-091-55/+158
| | | | | | (post-allocation only). It's kind of there, but not quite. I'll return to this later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75190 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how so_imm and t2_so_imm are handled. At instruction selection time, ↵Evan Cheng2009-07-081-3/+2
| | | | | | the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-3/+3
| | | | | | | Finish converting lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
* Start converting to new error handling API.Torok Edwin2009-07-081-3/+4
| | | | | | | | cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable arm pre-allocation load / store multiple optimization pass.Evan Cheng2009-06-191-16/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
* Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.Evan Cheng2009-06-191-15/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73749 91177308-0d34-0410-b5e6-96231b3b80d8
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-181-18/+48
| | | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
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