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* Add a testcase for checking the integer-promotion of many different vectorNadav Rotem2011-06-142-2/+171
| | | | | | | | | | | | | | | types (with power of two types such as 8,16,32 .. 512). Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding only if the target of the conversion is an integer (when the type action is scalarize). Add handling to the legalization of vector load/store in cases where the saved vector is integer-promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132985 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable trunc-store simplification on vectors.Nadav Rotem2011-06-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132984 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement Jakob's suggestion on how to detect fall thought without callingRafael Espindola2011-06-141-12/+19
| | | | | | AnalyzeBranch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132981 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-2/+3
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the threshold used by branch folding softer. Before we would get aRafael Espindola2011-06-142-5/+23
| | | | | | | sharp all or nothing transition when one extra predecessor was added. Now we still test first ones for merging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132974 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in FindMemType. When widening vector loads, use a wider memory typeNadav Rotem2011-06-131-0/+2
| | | | | | | | | only if the number of packed elements is a power of two. Bug found in Duncan's testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132923 91177308-0d34-0410-b5e6-96231b3b80d8
* Be less aggressive about hinting in RAFast.Jakob Stoklund Olesen2011-06-131-7/+5
| | | | | | | | | | In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132900 91177308-0d34-0410-b5e6-96231b3b80d8
* Include callee-saved registers in debug output.Jakob Stoklund Olesen2011-06-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132899 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix invalid uses of Twine. Hopefully this fixes the problem that Takumi isRafael Espindola2011-06-131-7/+7
| | | | | | having. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132898 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the calculation of the vectorTypeBreakdown into registers. OddNadav Rotem2011-06-121-5/+17
| | | | | | | | types such as i33 were rounded to i32. Originated from Duncan's testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132893 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the generated code by getCopyFromPartsVector for promoted integer types.Nadav Rotem2011-06-121-21/+20
| | | | | | | | | | | Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132892 91177308-0d34-0410-b5e6-96231b3b80d8
* Really fix the fall-through logic.Rafael Espindola2011-06-121-0/+3
| | | | | | Add a triple to the tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132885 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix silly bug I introduce in the previous commit. Fixes debug builds.Rafael Espindola2011-06-121-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132883 91177308-0d34-0410-b5e6-96231b3b80d8
* AnalyzeBranch doesn't change which successors a bb has, just the orderRafael Espindola2011-06-121-4/+11
| | | | | | | | | | | | | | | | | | we try to branch to them. Before we were creating successor lists with duplicated entries. Fixing that found a bug in isBlockOnlyReachableByFallthrough that would causes it to return the wrong answer for ----------- ... jne foo jmp bar foo: ---------- git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132882 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r132871.Chad Rosier2011-06-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132872 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Chad Rosier2011-06-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132871 91177308-0d34-0410-b5e6-96231b3b80d8
* 80-col cleanups.Eric Christopher2011-06-101-6/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132863 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed tabs. Also fixed my editor...Rafael Espindola2011-06-101-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132857 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the ParmContext enum values to make a bit more sense and add a smallCameron Zwarich2011-06-101-1/+1
| | | | | | comment on their meaning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132854 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tabs.Cameron Zwarich2011-06-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132853 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a pointless const_cast.Cameron Zwarich2011-06-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132852 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicated test.Rafael Espindola2011-06-101-4/+3
| | | | | | Thanks Bob Wilson for noticing it! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132851 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure that EmitGlobalVariable is correctly differentiating between declarationsChad Rosier2011-06-101-1/+1
| | | | | | | | | and definitions when emitting global variables. This was causing global declarations to be emitted as if they were definitions. Fixes <rdar://problem/9429892>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132825 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the optional verification step more strict.Rafael Espindola2011-06-091-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132822 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid a gcc warning about multiline comments.Rafael Espindola2011-06-091-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132821 91177308-0d34-0410-b5e6-96231b3b80d8
* On last fix to the early tail duplication.Rafael Espindola2011-06-091-4/+60
| | | | | | | | With this I am able to bootstrap clang with early tail duplication enabled for any small bb and setting tail-dup-size to a relatively large value(8) to stress this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132816 91177308-0d34-0410-b5e6-96231b3b80d8
* Also consider phi nodes when deciding if a register is live out.Rafael Espindola2011-06-091-10/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132814 91177308-0d34-0410-b5e6-96231b3b80d8
* Change this DAGCombine to build AND of SHR instead of SHR of AND; this ↵Eli Friedman2011-06-091-15/+16
| | | | | | | | | | matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132809 91177308-0d34-0410-b5e6-96231b3b80d8
* AnalyzeBranch modifies the bb, but we don't want to modify a bb withRafael Espindola2011-06-091-7/+6
| | | | | | eh edges. Swap the order of the checks to avoid it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132806 91177308-0d34-0410-b5e6-96231b3b80d8
* A PHI in this basic block is a use in another basic block.Rafael Espindola2011-06-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132805 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor some checks into shouldTailDuplicate. Update comments.Rafael Espindola2011-06-091-18/+29
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132798 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r132764 since it didn't cause the windows buildbot failures.Eric Christopher2011-06-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132776 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert 132764 to see if it fixes the Windows buildbot.Eric Christopher2011-06-091-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132771 91177308-0d34-0410-b5e6-96231b3b80d8
* If the alignment of the byval argument is greater than the alignmentEric Christopher2011-06-091-0/+2
| | | | | | | | | | of the frame then increase the maximum alignment of the frame to match. Fixes PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132764 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-083-14/+19
| | | | | | | | | No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132751 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix count.Rafael Espindola2011-06-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132749 91177308-0d34-0410-b5e6-96231b3b80d8
* Count how many phis we are creating.Rafael Espindola2011-06-081-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132748 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-9/+16
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132738 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a silly error I introduce in r131951.Rafael Espindola2011-06-071-4/+1
| | | | | | Fixes PR10095. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132735 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
| | | | | | | | I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132701 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen2011-06-061-87/+57
| | | | | | | | | | | | | | | When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132697 91177308-0d34-0410-b5e6-96231b3b80d8
* Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen2011-06-062-23/+52
| | | | | | | | | | | | Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132690 91177308-0d34-0410-b5e6-96231b3b80d8
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-063-0/+192
| | | | | | | | legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132689 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132681 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen2011-06-061-11/+6
| | | | | | | | | | | | | | | The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132680 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-061-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132676 91177308-0d34-0410-b5e6-96231b3b80d8
* Use path API for path concatenation.Benjamin Kramer2011-06-051-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132668 91177308-0d34-0410-b5e6-96231b3b80d8
* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132648 91177308-0d34-0410-b5e6-96231b3b80d8
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