aboutsummaryrefslogtreecommitdiffstats
path: root/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Fix PR8811 by teaching MachineVerifier about optional defs.Cameron Zwarich2010-12-191-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122199 91177308-0d34-0410-b5e6-96231b3b80d8
* StrongPHIElimination will never run before TwoAddressInstructionPass.Cameron Zwarich2010-12-191-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122197 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing standard headers. Patch by Joerg Sonnenberger!Nick Lewycky2010-12-192-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122193 91177308-0d34-0410-b5e6-96231b3b80d8
* teach MaskedValueIsZero how to analyze ADDE. This isChris Lattner2010-12-191-2/+13
| | | | | | | | enough to teach it that ADDE(0,0) is known 0 except the low bit, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122191 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some checks for StrongPHIElim. These checks make it impossible to use anCameron Zwarich2010-12-193-12/+6
| | | | | | | | | | | | alternative register allocator that does not require LiveIntervals by specifying it on the command-line for a target that has StrongPHIElimination enabled by default. These checks are pretty meaningless anyways, since StrongPHIElimination and PHIElimination are never used at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122176 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR8642: if a critical edge has a PHI value that can trap,Chris Lattner2010-12-191-0/+41
| | | | | | | | isel is *required* to split the edge. PHI values get evaluated on the edge, not in their predecessor block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122170 91177308-0d34-0410-b5e6-96231b3b80d8
* Apparently, operandices is not a word.Jakob Stoklund Olesen2010-12-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122135 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the inline spiller to attempt folding a load instruction into its singleJakob Stoklund Olesen2010-12-182-5/+27
| | | | | | | | | | | | | | | | | | use before rematerializing the load. This allows us to produce: addps LCPI0_1(%rip), %xmm2 Instead of: movaps LCPI0_1(%rip), %xmm3 addps %xmm3, %xmm2 Saving a register and an instruction. The standard spiller already knows how to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122133 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak debug spew.Jakob Stoklund Olesen2010-12-181-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122132 91177308-0d34-0410-b5e6-96231b3b80d8
* Check that the register is live-in to the loop header before inserting copies inJakob Stoklund Olesen2010-12-181-5/+7
| | | | | | | | | the loop predecessors. The register can be live-out from a predecessor without being live-in to the loop header if there is a critical edge from the predecessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122123 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix GCC warning:Nick Lewycky2010-12-181-0/+1
| | | | | | | lib/CodeGen/RegAllocGreedy.cpp:311: error: unused variable 'PhysReg' [-Wunused-variable] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122122 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass a Banner argument to the machine code verifier both fromJakob Stoklund Olesen2010-12-185-15/+22
| | | | | | | | createMachineVerifierPass and MachineFunction::verify. The banner is printed before the machine code dump, just like the printer pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122113 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid dereferencing end() in collectInterferingVRegs() when there is noJakob Stoklund Olesen2010-12-171-1/+1
| | | | | | interference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122108 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the -verify-regalloc command line option available to base classes asJakob Stoklund Olesen2010-12-173-4/+15
| | | | | | | | RegAllocBase::VerifyEnabled. Run the machine code verifier in a few interesting places during RegAllocGreedy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122107 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable loop splitting in RegAllocGreedy.Jakob Stoklund Olesen2010-12-171-23/+64
| | | | | | | The heuristics split around the largest loop where the current register may be allocated without interference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122106 91177308-0d34-0410-b5e6-96231b3b80d8
* During local stack slot allocation, the materializeFrameBaseRegister functionBill Wendling2010-12-171-6/+11
| | | | | | | | | | | | | | | | may be called. If the entry block is empty, the insertion point iterator will be the "end()" value. Calling ->getParent() on it (among others) causes problems. Modify materializeFrameBaseRegister to take the machine basic block and insert the frame base register at the beginning of that block. (It's very similar to what the code does all ready. The only difference is that it will always insert at the beginning of the entry block instead of after a previous materialization of the frame base register. I doubt that that matters here.) <rdar://problem/8782198> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson2010-12-171-16/+9
| | | | | | | BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122102 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a transform to DAG Combiner. This improves theDale Johannesen2010-12-171-0/+20
| | | | | | | | | code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122090 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow missing kill flags on an untied operand of a two-address instruction whenJakob Stoklund Olesen2010-12-171-1/+6
| | | | | | | | | | | | | | the operand uses the same register as a tied operand: %r1 = add %r1, %r1 If add were a three-address instruction, kill flags would be required on at least one of the uses. Since it is a two-address instruction, the tied use operand must not have a kill flag. This change makes the kill flag on the untied use operand optional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122082 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineLoopRange comparators for sorting loop lists by number and by area.Jakob Stoklund Olesen2010-12-171-2/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122073 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide LiveIntervalUnion::Query::checkLoopInterference.Jakob Stoklund Olesen2010-12-173-2/+39
| | | | | | | | This is a three-way interval list intersection between a virtual register, a live interval union, and a loop. It will be used to identify interference-free loops for live range splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122034 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-172-5/+6
| | | | | | Radar 8776599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122018 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment typo.Bob Wilson2010-12-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122016 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Make TargetAsmBackend available to the AsmStreamer.Daniel Dunbar2010-12-161-2/+5
| | | | | | - Treaty talks on the non-proliferation of MC objects broke down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121949 91177308-0d34-0410-b5e6-96231b3b80d8
* Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation ofJakob Stoklund Olesen2010-12-152-11/+39
| | | | | | | | live range splitting around loops guided by register pressure. So far, trySplit() simply prints a lot of debug output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121918 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineLoopRanges analysis.Jakob Stoklund Olesen2010-12-152-0/+86
| | | | | | | | A MachineLoopRange contains the intervals of slot indexes covered by the blocks in a loop. This representation of the loop blocks is more efficient to compare against interfering registers during register coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121917 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach machine cse to commute instructions.Evan Cheng2010-12-151-2/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121903 91177308-0d34-0410-b5e6-96231b3b80d8
* Move Value::getUnderlyingObject to be a standaloneDan Gohman2010-12-151-2/+3
| | | | | | | | function so that it can live in Analysis instead of VMCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121885 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build.Jakob Stoklund Olesen2010-12-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121872 91177308-0d34-0410-b5e6-96231b3b80d8
* Detect and enumerate bypass loops.Jakob Stoklund Olesen2010-12-152-0/+39
| | | | | | | | Bypass loops have the current live range live through, but contain no uses or defs. Splitting around a bypass loop can free registers for other uses inside the loop by spilling the split range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121871 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate SplitAnalysis::getSplitLoops().Jakob Stoklund Olesen2010-12-152-7/+14
| | | | | | | This method returns the set of loops with uses that are candidates for splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121870 91177308-0d34-0410-b5e6-96231b3b80d8
* take care of some todos, transforming [us]mul_lohi into Chris Lattner2010-12-151-2/+46
| | | | | | | a wider mul if the wider mul is legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121848 91177308-0d34-0410-b5e6-96231b3b80d8
* when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner2010-12-151-1/+1
| | | | | | | result, the top bits are truncated off anyway, just use SRL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify RegAllocGreedy's use of register aliases.Jakob Stoklund Olesen2010-12-141-17/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121807 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify CCState's use of register aliases.Jakob Stoklund Olesen2010-12-141-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121806 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify AggressiveAntiDepBreaker's use of register aliases.Jakob Stoklund Olesen2010-12-141-31/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121805 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.Jakob Stoklund Olesen2010-12-141-14/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121801 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng2010-12-141-1/+2
| | | | | | | | | | | | | | | | | | | | regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8
* Move debugging code entirely within DEBUG(). Silences an unused variableMatt Beaumont-Gay2010-12-141-8/+8
| | | | | | | warning in the opt build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121791 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.Jakob Stoklund Olesen2010-12-143-5/+52
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121783 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TRI::printReg instead of AbstractRegisterDescription when printingJakob Stoklund Olesen2010-12-143-34/+13
| | | | | | LiveIntervalUnions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
* Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().Jakob Stoklund Olesen2010-12-141-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121774 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused vector.Jakob Stoklund Olesen2010-12-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121741 91177308-0d34-0410-b5e6-96231b3b80d8
* Try reassigning all virtual register interferences, not just those with lowerJakob Stoklund Olesen2010-12-141-49/+71
| | | | | | | | spill weight. Filter out fixed registers instead. Add support for reassigning an interference that was assigned to an alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121737 91177308-0d34-0410-b5e6-96231b3b80d8
* Add stub for RAGreedy::trySplit.Jakob Stoklund Olesen2010-12-141-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121736 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a couple dag combines to transform mulhi/mullo into a wider multiplyChris Lattner2010-12-131-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121696 91177308-0d34-0410-b5e6-96231b3b80d8
* remove the verbose-asm "constant pool double" comments that we were printingChris Lattner2010-12-131-8/+0
| | | | | | | | | | | | for each constant pool entry. Using WriteTypeSymbolic here takes time proportional to the size of the module, for each constant pool entry. This speeds up -verbose-asm llc on 252.eon (a random testcase at my disposal) from 4.4s to 2.137s. llc takes 2.11s with asm-verbose off, so this is now a pretty reasonable cost for verbose comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121691 91177308-0d34-0410-b5e6-96231b3b80d8
* reduce indentation by using continue, no functionality change.Chris Lattner2010-12-131-38/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121662 91177308-0d34-0410-b5e6-96231b3b80d8
* Catch attempts to remove a deleted node from the CSE maps. Better toDuncan Sands2010-12-121-3/+2
| | | | | | | | catch this here rather than later after accessing uninitialized memory etc. Fires when compiling the testcase in PR8237. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121635 91177308-0d34-0410-b5e6-96231b3b80d8
* Add named timer groups for the different stages of register allocation.Jakob Stoklund Olesen2010-12-113-9/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121604 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-22 16:06:13 +0000