diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 65 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 16 | ||||
| -rw-r--r-- | lib/Target/ARM/NEONPreAllocPass.cpp | 16 |
3 files changed, 85 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 0739d4731d..39c253ba43 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1510,18 +1510,67 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue MemAddr, MemUpdate, MemOpc; if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc)) return NULL; + if (VT.is64BitVector()) { + switch (VT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("unhandled vld2lane type"); + case MVT::v8i8: Opc = ARM::VLD2LNd8; break; + case MVT::v4i16: Opc = ARM::VLD2LNd16; break; + case MVT::v2f32: + case MVT::v2i32: Opc = ARM::VLD2LNd32; break; + } + SDValue Chain = N->getOperand(0); + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, + N->getOperand(3), N->getOperand(4), + N->getOperand(5), Chain }; + return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7); + } + // Quad registers are handled by extracting subregs, doing the load, + // and then inserting the results as subregs. + EVT RegVT; + unsigned Opc2 = 0; switch (VT.getSimpleVT().SimpleTy) { default: llvm_unreachable("unhandled vld2lane type"); - case MVT::v8i8: Opc = ARM::VLD2LNd8; break; - case MVT::v4i16: Opc = ARM::VLD2LNd16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VLD2LNd32; break; + case MVT::v8i16: + Opc = ARM::VLD2LNq16a; + Opc2 = ARM::VLD2LNq16b; + RegVT = MVT::v4i16; + break; + case MVT::v4f32: + Opc = ARM::VLD2LNq32a; + Opc2 = ARM::VLD2LNq32b; + RegVT = MVT::v2f32; + break; + case MVT::v4i32: + Opc = ARM::VLD2LNq32a; + Opc2 = ARM::VLD2LNq32b; + RegVT = MVT::v2i32; + break; } SDValue Chain = N->getOperand(0); - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, - N->getOperand(3), N->getOperand(4), - N->getOperand(5), Chain }; - return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7); + unsigned Lane = cast<ConstantSDNode>(N->getOperand(5))->getZExtValue(); + unsigned NumElts = RegVT.getVectorNumElements(); + int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1; + + SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT, + N->getOperand(3)); + SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT, + N->getOperand(4)); + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, + getI32Imm(Lane % NumElts), Chain }; + SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2, + dl, RegVT, RegVT, MVT::Other, + Ops, 7); + SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT, + N->getOperand(3), + SDValue(VLdLn, 0)); + SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT, + N->getOperand(4), + SDValue(VLdLn, 1)); + Chain = SDValue(VLdLn, 2); + ReplaceUses(SDValue(N, 0), Q0); + ReplaceUses(SDValue(N, 1), Q1); + ReplaceUses(SDValue(N, 2), Chain); + return NULL; } case Intrinsic::arm_neon_vld3lane: { diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index d2231bf160..2bf09e2d58 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -266,16 +266,24 @@ def VLD4q32b : VLD4WB<0b1000, "vld4.32">; // FIXME: Not yet implemented. // VLD2LN : Vector Load (single 2-element structure to one lane) -class VLD2LND<bits<4> op11_8, string OpcodeStr> +class VLD2LN<bits<4> op11_8, string OpcodeStr> : NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"), "$src1 = $dst1, $src2 = $dst2", []>; -def VLD2LNd8 : VLD2LND<0b0001, "vld2.8">; -def VLD2LNd16 : VLD2LND<0b0101, "vld2.16">; -def VLD2LNd32 : VLD2LND<0b1001, "vld2.32">; +def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">; +def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">; +def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">; + +// vld2 to double-spaced even registers. +def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">; +def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">; + +// vld2 to double-spaced odd registers. +def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">; +def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">; // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LND<bits<4> op11_8, string OpcodeStr> diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp index 19ff0b3671..85dec6005e 100644 --- a/lib/Target/ARM/NEONPreAllocPass.cpp +++ b/lib/Target/ARM/NEONPreAllocPass.cpp @@ -57,6 +57,22 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs, NumRegs = 2; return true; + case ARM::VLD2LNq16a: + case ARM::VLD2LNq32a: + FirstOpnd = 0; + NumRegs = 2; + Offset = 0; + Stride = 2; + return true; + + case ARM::VLD2LNq16b: + case ARM::VLD2LNq32b: + FirstOpnd = 0; + NumRegs = 2; + Offset = 1; + Stride = 2; + return true; + case ARM::VLD2q8: case ARM::VLD2q16: case ARM::VLD2q32: |