diff options
Diffstat (limited to 'lib')
45 files changed, 413 insertions, 396 deletions
diff --git a/lib/CodeGen/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter.cpp index fa68541249..b3643129d9 100644 --- a/lib/CodeGen/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter.cpp @@ -18,6 +18,7 @@ #include "llvm/Module.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Mangler.h" #include "llvm/Support/MathExtras.h" diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp index 6cf253d2ff..550b52b1ff 100644 --- a/lib/CodeGen/Collector.cpp +++ b/lib/CodeGen/Collector.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index be3dd55fc8..46cdec7bd6 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -23,8 +23,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -772,7 +772,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit, MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI, unsigned Slot, int LdSlot, bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete, - VirtRegMap &vrm, SSARegMap *RegMap, + VirtRegMap &vrm, MachineRegisterInfo &RegInfo, const TargetRegisterClass* rc, SmallVector<int, 4> &ReMatIds, unsigned &NewVReg, bool &HasDef, bool &HasUse, @@ -869,7 +869,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit, // Create a new virtual register for the spill interval. bool CreatedNewVReg = false; if (NewVReg == 0) { - NewVReg = RegMap->createVirtualRegister(rc); + NewVReg = RegInfo.createVirtualRegister(rc); vrm.grow(); CreatedNewVReg = true; } @@ -971,7 +971,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI, unsigned Slot, int LdSlot, bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete, - VirtRegMap &vrm, SSARegMap *RegMap, + VirtRegMap &vrm, MachineRegisterInfo &RegInfo, const TargetRegisterClass* rc, SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo, @@ -1043,7 +1043,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, bool CanFold = rewriteInstructionForSpills(li, TrySplit, I->valno->id, index, end, MI, ReMatOrigDefMI, ReMatDefMI, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, - CanDelete, vrm, RegMap, rc, ReMatIds, NewVReg, + CanDelete, vrm, RegInfo, rc, ReMatIds, NewVReg, HasDef, HasUse, loopInfo, MBBVRegsMap, NewLIs); if (!HasDef && !HasUse) continue; @@ -1189,8 +1189,8 @@ addIntervalsForSpills(const LiveInterval &li, std::map<unsigned, std::vector<SRInfo> > RestoreIdxes; std::map<unsigned,unsigned> MBBVRegsMap; std::vector<LiveInterval*> NewLIs; - SSARegMap *RegMap = mf_->getSSARegMap(); - const TargetRegisterClass* rc = RegMap->getRegClass(li.reg); + MachineRegisterInfo &RegInfo = mf_->getRegInfo(); + const TargetRegisterClass* rc = RegInfo.getRegClass(li.reg); unsigned NumValNums = li.getNumValNums(); SmallVector<MachineInstr*, 4> ReMatDefs; @@ -1235,13 +1235,13 @@ addIntervalsForSpills(const LiveInterval &li, // Note ReMatOrigDefMI has already been deleted. rewriteInstructionsForSpills(li, false, I, NULL, ReMatDefMI, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, - false, vrm, RegMap, rc, ReMatIds, loopInfo, + false, vrm, RegInfo, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, MBBVRegsMap, NewLIs); } else { rewriteInstructionsForSpills(li, false, I, NULL, 0, Slot, 0, false, false, false, - false, vrm, RegMap, rc, ReMatIds, loopInfo, + false, vrm, RegInfo, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, MBBVRegsMap, NewLIs); } @@ -1309,7 +1309,7 @@ addIntervalsForSpills(const LiveInterval &li, (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG)); rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, - CanDelete, vrm, RegMap, rc, ReMatIds, loopInfo, + CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, MBBVRegsMap, NewLIs); } diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index c4af6a86c6..e1ae37cad2 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -28,6 +28,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -537,8 +538,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { // it as using all of the live-out values in the function. if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { MachineInstr *Ret = &MBB->back(); - for (MachineFunction::liveout_iterator I = MF->liveout_begin(), - E = MF->liveout_end(); I != E; ++I) { + for (MachineRegisterInfo::liveout_iterator + I = MF->getRegInfo().liveout_begin(), + E = MF->getRegInfo().liveout_end(); I != E; ++I) { assert(MRegisterInfo::isPhysicalRegister(*I) && "Cannot have a live-in virtual register!"); HandlePhysRegUse(*I, Ret); diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index a0db5c5865..668a9e5540 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -12,7 +12,7 @@ #include "llvm/Function.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -83,7 +83,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { if (MRegisterInfo::isPhysicalRegister(DstReg)) { TRC = getPhysicalRegisterRegClass(MRI, DstReg); } else { - TRC = MF.getSSARegMap()->getRegClass(DstReg); + TRC = MF.getRegInfo().getRegClass(DstReg); } assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && "Extract subreg and Dst must be of same register class"); @@ -155,7 +155,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { if (MRegisterInfo::isPhysicalRegister(InsReg)) { TRC1 = getPhysicalRegisterRegClass(MRI, InsReg); } else { - TRC1 = MF.getSSARegMap()->getRegClass(InsReg); + TRC1 = MF.getRegInfo().getRegClass(InsReg); } MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); @@ -179,7 +179,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { if (MRegisterInfo::isPhysicalRegister(DstReg)) { TRC0 = getPhysicalRegisterRegClass(MRI, DstReg); } else { - TRC0 = MF.getSSARegMap()->getRegClass(DstReg); + TRC0 = MF.getRegInfo().getRegClass(DstReg); } assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && "Insert superreg and Dst must be of same register class"); @@ -204,7 +204,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { if (MRegisterInfo::isPhysicalRegister(InsReg)) { TRC1 = getPhysicalRegisterRegClass(MRI, InsReg); } else { - TRC1 = MF.getSSARegMap()->getRegClass(InsReg); + TRC1 = MF.getRegInfo().getRegClass(InsReg); } MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp index 037e3e483f..595159b15f 100644 --- a/lib/CodeGen/MachineFunction.cpp +++ b/lib/CodeGen/MachineFunction.cpp @@ -14,12 +14,12 @@ //===----------------------------------------------------------------------===// #include "llvm/DerivedTypes.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" @@ -122,11 +122,10 @@ void ilist_traits<MachineBasicBlock>::transferNodesFromList( MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM) : Annotation(MF_AID), Fn(F), Target(TM) { - SSARegMapping = new SSARegMap(); + RegInfo = new MachineRegisterInfo(*TM.getRegisterInfo()); MFInfo = 0; FrameInfo = new MachineFrameInfo(); ConstantPool = new MachineConstantPool(TM.getTargetData()); - UsedPhysRegs.resize(TM.getRegisterInfo()->getNumRegs()); // Set up jump table. const TargetData &TD = *TM.getTargetData(); @@ -141,7 +140,7 @@ MachineFunction::MachineFunction(const Function *F, MachineFunction::~MachineFunction() { BasicBlocks.clear(); - delete SSARegMapping; + delete RegInfo; delete MFInfo; delete FrameInfo; delete ConstantPool; @@ -208,9 +207,10 @@ void MachineFunction::print(std::ostream &OS) const { const MRegisterInfo *MRI = getTarget().getRegisterInfo(); - if (!livein_empty()) { + if (!RegInfo->livein_empty()) { OS << "Live Ins:"; - for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) { + for (MachineRegisterInfo::livein_iterator + I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { if (MRI) OS << " " << MRI->getName(I->first); else @@ -221,9 +221,10 @@ void MachineFunction::print(std::ostream &OS) const { } OS << "\n"; } - if (!liveout_empty()) { + if (!RegInfo->liveout_empty()) { OS << "Live Outs:"; - for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) + for (MachineRegisterInfo::liveout_iterator + I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I) if (MRI) OS << " " << MRI->getName(*I); else @@ -324,11 +325,6 @@ MachineFunction& MachineFunction::get(const Function *F) return *mc; } -void MachineFunction::clearSSARegMap() { - delete SSARegMapping; - SSARegMapping = 0; -} - //===----------------------------------------------------------------------===// // MachineFrameInfo implementation //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index d843b27c49..95c768d72c 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/Value.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp new file mode 100644 index 0000000000..19c09eee51 --- /dev/null +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -0,0 +1,20 @@ +//===-- MachineRegisterInfo.cpp -------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Implementation of the MachineRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/MachineRegisterInfo.h" +using namespace llvm; + +MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) { + VRegInfo.reserve(256); + UsedPhysRegs.resize(MRI.getNumRegs()); +} diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 480ba939b0..764e89b6da 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/STLExtras.h" @@ -127,8 +127,8 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, // Create a new register for the incoming PHI arguments. MachineFunction &MF = *MBB.getParent(); - const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg); - unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC); + const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); + unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC); // Insert a register to register copy in the top of the current block (but // after any remaining phi nodes) which copies the new incoming register diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 3f62630b3b..d1f796d47d 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -20,6 +20,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MRegisterInfo.h" @@ -48,9 +50,8 @@ namespace { // Get MachineModuleInfo so that we can track the construction of the // frame. - if (MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>()) { + if (MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>()) Fn.getFrameInfo()->setMachineModuleInfo(MMI); - } // Allow the target machine to make some adjustments to the function // e.g. UsedPhysRegs before calculateCalleeSavedRegisters. @@ -174,13 +175,13 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) { std::vector<CalleeSavedInfo> CSI; for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; - if (Fn.isPhysRegUsed(Reg)) { + if (Fn.getRegInfo().isPhysRegUsed(Reg)) { // If the reg is modified, save it! CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i])); } else { for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { // Check alias registers too. - if (Fn.isPhysRegUsed(*AliasSet)) { + if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) { CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i])); break; } diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index 3e9254ab9d..5c894729a7 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -32,8 +32,8 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" @@ -326,7 +326,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB, // register. We only need to spill it into its stack slot if it has been // modified. if (isVirtRegModified(VirtReg)) { - const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); DOUT << " to stack slot #" << FrameIndex; RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); @@ -418,7 +418,7 @@ unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) { /// unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I, unsigned VirtReg) { - const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); // First check to see if we have a free register of the requested type... unsigned PhysReg = getFreeReg(RC); @@ -512,7 +512,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI // Otherwise, if we have free physical registers available to hold the // value, use them. - const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); unsigned PhysReg = getFreeReg(RC); int FrameIndex = getStackSpaceFor(VirtReg, RC); @@ -545,7 +545,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); ++NumLoads; // Update statistics - MF->setPhysRegUsed(PhysReg); + MF->getRegInfo().setPhysRegUsed(PhysReg); MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register return MI; } @@ -624,16 +624,17 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // If this is the first basic block in the machine function, add live-in // registers as active. if (&MBB == &*MF->begin()) { - for (MachineFunction::livein_iterator I = MF->livein_begin(), - E = MF->livein_end(); I != E; ++I) { + for (MachineRegisterInfo::livein_iterator + I = MF->getRegInfo().livein_begin(), + E = MF->getRegInfo().livein_end(); I != E; ++I) { unsigned Reg = I->first; - MF->setPhysRegUsed(Reg); + MF->getRegInfo().setPhysRegUsed(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now - MF->setPhysRegUsed(*AliasSet); + MF->getRegInfo().setPhysRegUsed(*AliasSet); } } } @@ -731,14 +732,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // larger registers). Ignore. if (isReadModWriteImplicitDef(MI, MO.getReg())) continue; - MF->setPhysRegUsed(Reg); + MF->getRegInfo().setPhysRegUsed(Reg); spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg PhysRegsUsed[Reg] = 0; // It is free and reserved now for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now - MF->setPhysRegUsed(*AliasSet); + MF->getRegInfo().setPhysRegUsed(*AliasSet); } } } @@ -753,12 +754,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { spillPhysReg(MBB, MI, Reg, true); PhysRegsUsed[Reg] = 0; // It is free and reserved now } - MF->setPhysRegUsed(Reg); + MF->getRegInfo().setPhysRegUsed(Reg); for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now - MF->setPhysRegUsed(*AliasSet); + MF->getRegInfo().setPhysRegUsed(*AliasSet); } } } @@ -786,7 +787,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // If DestVirtReg already has a value, use it. if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) DestPhysReg = chooseReg(MBB, MI, DestVirtReg); - MF->setPhysRegUsed(DestPhysReg); + MF->getRegInfo().setPhysRegUsed(DestPhysReg); markVirtRegModified(DestVirtReg); MI->getOperand(i).setReg(DestPhysReg); // Assign the output register } @@ -868,9 +869,10 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) { // initialize the virtual->physical register map to have a 'null' // mapping for all virtual registers - Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg()); - StackSlotForVirtReg.grow(MF->getSSARegMap()->getLastVirtReg()); - VirtRegModified.resize(MF->getSSARegMap()->getLastVirtReg() - MRegisterInfo::FirstVirtualRegister + 1,0); + Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg()); + StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg()); + VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() - + MRegisterInfo::FirstVirtualRegister + 1, 0); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 7cf4ddf27d..17d416a4a6 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -19,10 +19,10 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -64,7 +64,7 @@ namespace { const TargetMachine* tm_; const MRegisterInfo* mri_; const TargetInstrInfo* tii_; - SSARegMap *regmap_; + MachineRegisterInfo *reginfo_; BitVector allocatableRegs_; LiveIntervals* li_; const MachineLoopInfo *loopInfo; @@ -230,7 +230,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { if (Reg == SrcReg) return Reg; - const TargetRegisterClass *RC = regmap_->getRegClass(cur.reg); + const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg); if (!RC->contains(SrcReg)) return Reg; @@ -251,7 +251,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) { tm_ = &fn.getTarget(); mri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); - regmap_ = mf_->getSSARegMap(); + reginfo_ = &mf_->getRegInfo(); allocatableRegs_ = mri_->getAllocatableSet(fn); li_ = &getAnalysis<LiveIntervals>(); loopInfo = &getAnalysis<MachineLoopInfo>(); @@ -296,7 +296,7 @@ void RALinScan::initIntervalSets() for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { if (MRegisterInfo::isPhysicalRegister(i->second.reg)) { - mf_->setPhysRegUsed(i->second.reg); + reginfo_->setPhysRegUsed(i->second.reg); fixed_.push_back(std::make_pair(&i->second, i->second.begin())); } else unhandled_.push(&i->second); @@ -508,7 +508,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) std::vector<std::pair<unsigned, float> > SpillWeightsToAdd; unsigned StartPosition = cur->beginNumber(); - const TargetRegisterClass *RC = regmap_->getRegClass(cur->reg); + const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg); const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC); // If this live interval is defined by a move instruction and its source is @@ -540,7 +540,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) unsigned Reg = i->first->reg; assert(MRegisterInfo::isVirtualRegister(Reg) && "Can only allocate virtual registers!"); - const TargetRegisterClass *RegRC = regmap_->getRegClass(Reg); + const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg); // If this is not in a related reg class to the register we're allocating, // don't check it. if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && @@ -838,7 +838,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0); unsigned MaxInactiveCount = 0; - const TargetRegisterClass *RC = regmap_->getRegClass(cur->reg); + const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg); const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC); for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end(); @@ -849,7 +849,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { // If this is not in a related reg class to the register we're allocating, // don't check it. - const TargetRegisterClass *RegRC = regmap_->getRegClass(reg); + const TargetRegisterClass *RegRC = reginfo_->getRegClass(reg); if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) { reg = vrm_->getPhys(reg); ++inactiveCounts[reg]; diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index 076af6dd48..8c38cd06f9 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -17,8 +17,8 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" @@ -49,7 +49,7 @@ namespace { private: const TargetMachine *TM; MachineFunction *MF; - const MRegisterInfo *RegInfo; + const MRegisterInfo *MRI; LiveVariables *LV; // StackSlotForVirtReg - Maps virtual regs to the frame index where these @@ -155,7 +155,7 @@ namespace { /// bool areRegsEqual(unsigned R1, unsigned R2) const { if (R1 == R2) return true; - for (const unsigned *AliasSet = RegInfo->getAliasSet(R2); + for (const unsigned *AliasSet = MRI->getAliasSet(R2); *AliasSet; ++AliasSet) { if (*AliasSet == R1) return true; } @@ -274,7 +274,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB, assert(VirtReg && "Spilling a physical register is illegal!" " Must not have appropriate kill for the register or use exists beyond" " the intended one."); - DOUT << " Spilling register " << RegInfo->getName(PhysReg) + DOUT << " Spilling register " << MRI->getName(PhysReg) << " containing %reg" << VirtReg; if (!isVirtRegModified(VirtReg)) DOUT << " which has not been modified, so no store necessary!"; @@ -283,10 +283,10 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB, // register. We only need to spill it into its stack slot if it has been // modified. if (isVirtRegModified(VirtReg)) { - const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); DOUT << " to stack slot #" << FrameIndex; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); + MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); ++NumStores; // Update statistics } @@ -311,7 +311,7 @@ void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, } else { // If the selected register aliases any other registers, we must make // sure that one of the aliases isn't alive. - for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. PhysRegsUsed[*AliasSet] != -2) // If allocatable. @@ -344,7 +344,7 @@ bool RALocal::isPhysRegAvailable(unsigned PhysReg) const { // If the selected register aliases any other allocated registers, it is // not free! - for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use? return false; // Can't use this reg then. @@ -376,7 +376,7 @@ unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) { /// unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I, unsigned VirtReg) { - const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); // First check to see if we have a free register of the requested type... unsigned PhysReg = getFreeReg(RC); @@ -407,7 +407,7 @@ unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I, } else { // If one of the registers aliased to the current register is // compatible, use it. - for (const unsigned *AliasIt = RegInfo->getAliasSet(R); + for (const unsigned *AliasIt = MRI->getAliasSet(R); *AliasIt; ++AliasIt) { if (RC->contains(*AliasIt) && // If this is pinned down for some reason, don't use it. For @@ -465,7 +465,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, // Otherwise, we need to fold it into the current instruction, or reload it. // If we have registers available to hold the value, use them. - const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); unsigned PhysReg = getFreeReg(RC); int FrameIndex = getStackSpaceFor(VirtReg, RC); @@ -475,7 +475,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, // If we can fold this spill into this instruction, do so now. SmallVector<unsigned, 2> Ops; Ops.push_back(OpNum); - if (MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) { + if (MachineInstr* FMI = MRI->foldMemoryOperand(MI, Ops, FrameIndex)) { ++NumFolded; // Since we changed the address of MI, make sure to update live variables // to know that the new instruction has the properties of the old one. @@ -492,13 +492,13 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded DOUT << " Reloading %reg" << VirtReg << " into " - << RegInfo->getName(PhysReg) << "\n"; + << MRI->getName(PhysReg) << "\n"; // Add move instruction(s) - RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); + MRI->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); ++NumLoads; // Update statistics - MF->setPhysRegUsed(PhysReg); + MF->getRegInfo().setPhysRegUsed(PhysReg); MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register return MI; } @@ -538,18 +538,18 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // If this is the first basic block in the machine function, add live-in // registers as active. if (&MBB == &*MF->begin()) { - for (MachineFunction::livein_iterator I = MF->livein_begin(), - E = MF->livein_end(); I != E; ++I) { + for (MachineRegisterInfo::livein_iterator I=MF->getRegInfo().livein_begin(), + E = MF->getRegInfo().livein_end(); I != E; ++I) { unsigned Reg = I->first; - MF->setPhysRegUsed(Reg); + MF->getRegInfo().setPhysRegUsed(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now AddToPhysRegsUseOrder(Reg); - for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { AddToPhysRegsUseOrder(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now - MF->setPhysRegUsed(*AliasSet); + MF->getRegInfo().setPhysRegUsed(*AliasSet); } } } @@ -561,9 +561,9 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; DOUT << " Regs have values: "; - for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) + for (unsigned i = 0; i != MRI->getNumRegs(); ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) - DOUT << "[" << RegInfo->getName(i) + DOUT << "[" << MRI->getName(i) << ",%reg" << PhysRegsUsed[i] << "] "; DOUT << "\n"); @@ -625,14 +625,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { } if (PhysReg) { - DOUT << " Last use of " << RegInfo->getName(PhysReg) + DOUT << " Last use of " << MRI->getName(PhysReg) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg); + for (const unsigned *AliasSet = MRI->getSubRegisters(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { DOUT << " Last use of " - << RegInfo->getName(*AliasSet) + << MRI->getName(*AliasSet) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(*AliasSet); } @@ -653,15 +653,15 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // larger registers). Ignore. if (isReadModWriteImplicitDef(MI, MO.getReg())) continue; - MF->setPhysRegUsed(Reg); + MF->getRegInfo().setPhysRegUsed(Reg); spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg PhysRegsUsed[Reg] = 0; // It is free and reserved now AddToPhysRegsUseOrder(Reg); - for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { - MF->setPhysRegUsed(*AliasSet); + MF->getRegInfo().setPhysRegUsed(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now AddToPhysRegsUseOrder(*AliasSet); } @@ -679,13 +679,13 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { AddToPhysRegsUseOrder(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now } - MF->setPhysRegUsed(Reg); - for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + MF->getRegInfo().setPhysRegUsed(Reg); + for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { AddToPhysRegsUseOrder(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now - MF->setPhysRegUsed(*AliasSet); + MF->getRegInfo().setPhysRegUsed(*AliasSet); } } } @@ -713,7 +713,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // If DestVirtReg already has a value, use it. if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) DestPhysReg = getReg(MBB, MI, DestVirtReg); - MF->setPhysRegUsed(DestPhysReg); + MF->getRegInfo().setPhysRegUsed(DestPhysReg); markVirtRegModified(DestVirtReg); MI->getOperand(i).setReg(DestPhysReg); // Assign the output register } @@ -736,14 +736,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { } if (PhysReg) { - DOUT << " Register " << RegInfo->getName(PhysReg) + DOUT << " Register " << MRI->getName(PhysReg) << " [%reg" << VirtReg << "] is never used, removing it frame live list\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { - DOUT << " Register " << RegInfo->getName(*AliasSet) + DOUT << " Register " << MRI->getName(*AliasSet) << " [%reg" << *AliasSet << "] is never used, removing it frame live list\n"; removePhysReg(*AliasSet); @@ -764,7 +764,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); // Spill all physical registers holding virtual registers now. - for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) + for (unsigned i = 0, e = MRI->getNumRegs(); i != e; ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) if (unsigned VirtReg = PhysRegsUsed[i]) spillVirtReg(MBB, MI, VirtReg, i); @@ -775,7 +775,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // This checking code is very expensive. bool AllOk = true; for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i) + e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) if (unsigned PR = Virt2PhysRegMap[i]) { cerr << "Register still mapped: " << i << " -> " << PR << "\n"; AllOk = false; @@ -796,16 +796,16 @@ bool RALocal::runOnMachineFunction(MachineFunction &Fn) { DOUT << "Machine Function " << "\n"; MF = &Fn; TM = &Fn.getTarget(); - RegInfo = TM->getRegisterInfo(); + MRI = TM->getRegisterInfo(); LV = &getAnalysis<LiveVariables>(); - PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); + PhysRegsUsed.assign(MRI->getNumRegs(), -1); // At various places we want to efficiently check to see whether a register // is allocatable. To handle this, we mark all unallocatable registers as // being pinned down, permanently. { - BitVector Allocable = RegInfo->getAllocatableSet(Fn); + BitVector Allocable = MRI->getAllocatableSet(Fn); for (unsigned i = 0, e = Allocable.size(); i != e; ++i) if (!Allocable[i]) PhysRegsUsed[i] = -2; // Mark the reg unallocable. @@ -813,7 +813,7 @@ bool RALocal::runOnMachineFunction(MachineFunction &Fn) { // initialize the virtual->physical register map to have a 'null' // mapping for all virtual registers - Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg()); + Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg()); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index f9923a51f2..a60c63c28e 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -18,8 +18,8 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -44,7 +44,7 @@ namespace { private: MachineFunction *MF; const TargetMachine *TM; - const MRegisterInfo *RegInfo; + const MRegisterInfo *MRI; // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // these values are spilled @@ -119,7 +119,7 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); @@ -129,7 +129,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { unsigned PhysReg = *(RI+regIdx); if (!RegsUsed[PhysReg]) { - MF->setPhysRegUsed(PhysReg); + MF->getRegInfo().setPhysRegUsed(PhysReg); return PhysReg; } } @@ -138,25 +138,25 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned VirtReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIdx = getStackSpaceFor(VirtReg, RC); unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) ++NumLoads; - RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); return PhysReg; } void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned VirtReg, unsigned PhysReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) ++NumStores; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC); + MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC); } @@ -166,7 +166,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // Made to combat the incorrect allocation of r2 = add r1, r1 std::map<unsigned, unsigned> Virt2PhysRegMap; - RegsUsed.resize(RegInfo->getNumRegs()); + RegsUsed.resize(MRI->getNumRegs()); // This is a preliminary pass that will invalidate any registers that are // used by the instruction (including implicit uses). @@ -181,7 +181,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { if (Desc.ImplicitDefs) { for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { RegsUsed[*Regs] = true; - MF->setPhysRegUsed(*Regs); + MF->getRegInfo().setPhysRegUsed(*Regs); } } @@ -237,7 +237,7 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { DOUT << "Machine Function\n"; MF = &Fn; TM = &MF->getTarget(); - RegInfo = TM->getRegisterInfo(); + MRI = TM->getRegisterInfo(); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index b7fa207895..e1540ea1d2 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -15,6 +15,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 53fec718ff..ce0707423e 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -27,6 +27,13 @@ #include "llvm/Support/MathExtras.h" using namespace llvm; +ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, + const TargetMachine &tm) + : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { + TII = TM.getInstrInfo(); + MRI = TM.getRegisterInfo(); + ConstPool = BB->getParent()->getConstantPool(); +} /// CheckForPhysRegDependency - Check if the dependency between def and use of /// a specified operand is a physical register dependency. If so, returns the @@ -341,7 +348,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, const TargetRegisterClass *TRC = 0; // Figure out the register class to create for the destreg. if (VRBase) - TRC = RegMap->getRegClass(VRBase); + TRC = RegInfo.getRegClass(VRBase); else TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); @@ -351,7 +358,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, VRBase = SrcReg; } else { // Create the reg, emit the copy. - VRBase = RegMap->createVirtualRegister(TRC); + VRBase = RegInfo.createVirtualRegister(TRC); MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); } @@ -390,7 +397,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, if (VRBase == 0) { const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); assert(RC && "Isn't a register operand!"); - VRBase = RegMap->createVirtualRegister(RC); + VRBase = RegInfo.createVirtualRegister(RC); MI->addOperand(MachineOperand::CreateReg(VRBase, true)); } @@ -437,7 +444,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - const TargetRegisterClass *VRC = RegMap->getRegClass(VReg); + const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg); if (VRC != RC) { cerr << "Register class of operand and regclass of use don't agree!\n"; #ifndef NDEBUG @@ -501,7 +508,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - assert(RegMap->getRegClass(VReg) == RC && + assert(RegInfo.getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); } } @@ -565,18 +572,18 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, // Figure out the register class to create for the destreg. unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); - const TargetRegisterClass *TRC = RegMap->getRegClass(VReg); + const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg); const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx); if (VRBase) { // Grab the destination register const TargetRegisterClass *DRC = 0; - DRC = RegMap->getRegClass(VRBase); + DRC = RegInfo.getRegClass(VRBase); assert(SRC == DRC && "Source subregister and destination must have the same class"); } else { // Create the reg - VRBase = RegMap->createVirtualRegister(SRC); + VRBase = RegInfo.createVirtualRegister(SRC); } // Add def, source, and subreg index @@ -626,13 +633,12 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, // Figure out the register class to create for the destreg. const TargetRegisterClass *TRC = 0; if (VRBase) { - TRC = RegMap->getRegClass(VRBase); + TRC = RegInfo.getRegClass(VRBase); } else { - TRC = getSuperregRegisterClass(RegMap->getRegClass(SubReg), - SubIdx, + TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx, Node->getValueType(0)); assert(TRC && "Couldn't determine register class for insert_subreg"); - VRBase = RegMap->createVirtualRegister(TRC); // Create the reg + VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg } MI->addOperand(MachineOperand::CreateReg(VRBase, true)); @@ -740,7 +746,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, const TargetRegisterClass *TRC = 0; // Get the target register class if (MRegisterInfo::isVirtualRegister(InReg)) - TRC = RegMap->getRegClass(InReg); + TRC = RegInfo.getRegClass(InReg); else TRC = MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), @@ -847,7 +853,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM } else { // Copy from physical register. assert(I->Reg && "Unknown physical register!"); - unsigned VRBase = RegMap->createVirtualRegister(SU->CopyDstRC); + unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC); bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)); assert(isNew && "Node emitted out of order - early"); MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, @@ -864,10 +870,10 @@ void ScheduleDAG::EmitSchedule() { // block before emitting the code for the block. MachineFunction &MF = DAG.getMachineFunction(); if (&MF.front() == BB) { - for (MachineFunction::livein_iterator LI = MF.livein_begin(), - E = MF.livein_end(); LI != E; ++LI) + for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(), + E = RegInfo.livein_end(); LI != E; ++LI) if (LI->second) { - const TargetRegisterClass *RC = RegMap->getRegClass(LI->second); + const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, LI->first, RC, RC); } @@ -906,11 +912,6 @@ void ScheduleDAG::dumpSchedule() const { /// Run - perform scheduling. /// MachineBasicBlock *ScheduleDAG::Run() { - TII = TM.getInstrInfo(); - MRI = TM.getRegisterInfo(); - RegMap = BB->getParent()->getSSARegMap(); - ConstPool = BB->getParent()->getConstantPool(); - Schedule(); return BB; } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index cf24e46e55..5c7422c97a 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -22,7 +22,6 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 6ea7c80687..7ed8bc8a55 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -18,7 +18,6 @@ #define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 52d185b5d1..13d3f9720f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -26,14 +26,14 @@ #include "llvm/Intrinsics.h" #include "llvm/IntrinsicInst.h" #include "llvm/ParameterAttributes.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" @@ -166,7 +166,7 @@ namespace llvm { TargetLowering &TLI; Function &Fn; MachineFunction &MF; - SSARegMap *RegMap; + MachineRegisterInfo &RegInfo; FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF); @@ -189,7 +189,7 @@ namespace llvm { #endif unsigned MakeReg(MVT::ValueType VT) { - return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); + return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); } /// isExportedInst - Return true if the specified value is an instruction @@ -244,7 +244,7 @@ static bool isOnlyUsedInEntryBlock(Argument *A) { FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, Function &fn, MachineFunction &mf) - : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) { + : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) { // Create a vreg for each argument register that is not dead and is used // outside of the entry block for the function. @@ -3348,9 +3348,9 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, ValueVT = RegVT; // Create the appropriate number of virtual registers. - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); for (; NumRegs; --NumRegs) - Regs.push_back(RegMap->createVirtualRegister(PhysReg.second)); + Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs); @@ -4363,7 +4363,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { //===----------------------------------------------------------------------===// unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { - return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); + return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); } void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { @@ -4378,7 +4378,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) { AA = &getAnalysis<AliasAnalysis>(); MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine()); - RegMap = MF.getSSARegMap(); + RegInfo = &MF.getRegInfo(); DOUT << "\n\n\n=== " << Fn.getName() << "\n"; FunctionLoweringInfo FuncInfo(TLI, Fn, MF); @@ -4395,9 +4395,9 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) { // Add function live-ins to entry block live-in set. BasicBlock *EntryBB = &Fn.getEntryBlock(); BB = FuncInfo.MBBMap[EntryBB]; - if (!MF.livein_empty()) - for (MachineFunction::livein_iterator I = MF.livein_begin(), - E = MF.livein_end(); I != E; ++I) + if (!RegInfo->livein_empty()) + for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), + E = RegInfo->livein_end(); I != E; ++I) BB->addLiveIn(I->first); #ifndef NDEBUG diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index e4a8b944f1..da8b39fb2d 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -21,10 +21,9 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/RegisterCoalescer.h" -#include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" @@ -283,7 +282,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { // If this is a extract_subreg where dst is a physical register, e.g. // cl = EXTRACT_SUBREG reg1024, 1 // then create and update the actual physical register allocated to RHS. - const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repSrcReg); + const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg); for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg); unsigned SR = *SRs; ++SRs) { if (repDstReg == mri_->getSubReg(SR, SubIdx) && @@ -313,7 +312,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { } else { unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM; unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM; - const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repDstReg); + const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repDstReg); unsigned Threshold = allocatableRCRegs_[RC].count(); // Be conservative. If both sides are virtual registers, do not coalesce // if this will cause a high use density interval to target a smaller set @@ -395,7 +394,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg; unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg; - const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg); + const TargetRegisterClass *RC = mf_->getRegInfo().getRegClass(JoinVReg); unsigned Threshold = allocatableRCRegs_[RC].count() * 2; if (TheCopy.isBackEdge) Threshold *= 2; // Favors back edge copies. @@ -1239,13 +1238,13 @@ bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, if (MRegisterInfo::isPhysicalRegister(RegA)) { assert(MRegisterInfo::isVirtualRegister(RegB) && "Shouldn't consider two physregs!"); - return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); + return !mf_->getRegInfo().getRegClass(RegB)->contains(RegA); } // Compare against the regclass for the second reg. - const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); + const TargetRegisterClass *RegClass = mf_->getRegInfo().getRegClass(RegA); if (MRegisterInfo::isVirtualRegister(RegB)) - return RegClass != mf_->getSSARegMap()->getRegClass(RegB); + return RegClass != mf_->getRegInfo().getRegClass(RegB); else return !RegClass->contains(RegB); } @@ -1254,8 +1253,8 @@ bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, /// cycles Start and End. It also returns the use operand by reference. It /// returns NULL if there are no uses. MachineInstr * -SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg, - MachineOperand *&MOU) { +SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, + unsigned Reg, MachineOperand *&MOU) { int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; int s = Start; while (e >= s) { @@ -1390,9 +1389,9 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { E = mri_->regclass_end(); I != E; ++I) allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I))); - SSARegMap *RegMap = mf_->getSSARegMap(); - r2rMap_.grow(RegMap->getLastVirtReg()); - r2rRevMap_.grow(RegMap->getLastVirtReg()); + MachineRegisterInfo &RegInfo = mf_->getRegInfo(); + r2rMap_.grow(RegInfo.getLastVirtReg()); + r2rRevMap_.grow(RegInfo.getLastVirtReg()); // Join (coalesce) intervals if requested. IndexedMap<unsigned, VirtReg2IndexFunctor> RegSubIdxMap; @@ -1413,7 +1412,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { // Transfer sub-registers info to SSARegMap now that coalescing information // is complete. - RegSubIdxMap.grow(mf_->getSSARegMap()->getLastVirtReg()+1); + RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1); while (!SubRegIdxes.empty()) { std::pair<unsigned, unsigned> RI = SubRegIdxes.back(); SubRegIdxes.pop_back(); diff --git a/lib/CodeGen/StrongPHIElimination.cpp b/lib/CodeGen/StrongPHIElimination.cpp index d7360840e2..1a1f77c1c6 100644 --- a/lib/CodeGen/StrongPHIElimination.cpp +++ b/lib/CodeGen/StrongPHIElimination.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DepthFirstIterator.h" diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 1ffee3f52a..4f92bdb6ca 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -33,7 +33,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -192,7 +192,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { } InstructionRearranged: - const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); + const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA); MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); MachineBasicBlock::iterator prevMi = prior(mi); diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 80fa71a30b..9100054169 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -21,7 +21,7 @@ #include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" @@ -69,7 +69,7 @@ VirtRegMap::VirtRegMap(MachineFunction &mf) } void VirtRegMap::grow() { - unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg(); + unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); Virt2PhysMap.grow(LastVirtReg); Virt2StackSlotMap.grow(LastVirtReg); Virt2ReMatIdMap.grow(LastVirtReg); @@ -82,7 +82,7 @@ int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { assert(MRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); - const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); + const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment()); Virt2StackSlotMap[virtReg] = frameIndex; @@ -139,14 +139,14 @@ void VirtRegMap::print(std::ostream &OS) const { OS << "********** REGISTER MAP **********\n"; for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { + e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; } for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) + e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; OS << '\n'; @@ -197,7 +197,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { if (!VRM.isAssignedReg(VirtReg)) { int StackSlot = VRM.getStackSlot(VirtReg); const TargetRegisterClass* RC = - MF.getSSARegMap()->getRegClass(VirtReg); + MF.getRegInfo().getRegClass(VirtReg); if (MO.isUse() && std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) @@ -214,10 +214,10 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { ++NumStores; } } - MF.setPhysRegUsed(PhysReg); + MF.getRegInfo().setPhysRegUsed(PhysReg); MI.getOperand(i).setReg(PhysReg); } else { - MF.setPhysRegUsed(MO.getReg()); + MF.getRegInfo().setPhysRegUsed(MO.getReg()); } } @@ -240,17 +240,18 @@ namespace { /// blocks that have low register pressure (the vreg may be spilled due to /// register pressure in other blocks). class VISIBILITY_HIDDEN LocalSpiller : public Spiller { - SSARegMap *RegMap; + MachineRegisterInfo *RegInfo; const MRegisterInfo *MRI; const TargetInstrInfo *TII; public: bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { - RegMap = MF.getSSARegMap(); + RegInfo = &MF.getRegInfo(); MRI = MF.getTarget().getRegisterInfo(); TII = MF.getTarget().getInstrInfo(); DOUT << "\n**** Local spiller rewriting function '" << MF.getFunction()->getName() << "':\n"; - DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n"; + DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" + " ****\n"; DEBUG(MF.dump()); for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); @@ -672,7 +673,7 @@ namespace { // to undo a previous reuse. MachineBasicBlock *MBB = MI->getParent(); const TargetRegisterClass *AliasRC = - MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); + MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); // Copy Op out of the vector and remove it, we're going to insert an // explicit load for it. @@ -971,14 +972,15 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (!VRM.getPreSplitReg(VirtReg)) continue; // Split interval spilled again. unsigned Phys = VRM.getPhys(VirtReg); - MF.setPhysRegUsed(Phys); + RegInfo->setPhysRegUsed(Phys); if (VRM.isReMaterialized(VirtReg)) { MRI->reMaterialize(MBB, &MI, Phys, VRM.getReMaterializedMI(VirtReg)); ++NumReMats; } else { - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); - MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), + RC); ++NumLoads; } // This invalidates Phys. @@ -997,7 +999,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { bool isKill = SpillRegs[i].second; if (!VRM.getPreSplitReg(VirtReg)) continue; // Split interval spilled again. - const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); unsigned Phys = VRM.getPhys(VirtReg); int StackSlot = VRM.getStackSlot(VirtReg); MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); @@ -1021,7 +1023,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (MRegisterInfo::isPhysicalRegister(VirtReg)) { // Ignore physregs for spilling, but remember that it is used by this // function. - MF.setPhysRegUsed(VirtReg); + RegInfo->setPhysRegUsed(VirtReg); continue; } @@ -1032,7 +1034,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (VRM.isAssignedReg(VirtReg)) { // This virtual register was assigned a physreg! unsigned Phys = VRM.getPhys(VirtReg); - MF.setPhysRegUsed(Phys); + RegInfo->setPhysRegUsed(Phys); if (MO.isDef()) ReusedOperands.markClobbered(Phys); unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys; @@ -1064,7 +1066,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // the right register file. if (PhysReg && (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); if (!RC->contains(PhysReg)) PhysReg = 0; } @@ -1177,8 +1179,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { continue; } - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); - MF.setPhysRegUsed(DesignatedReg); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + RegInfo->setPhysRegUsed(DesignatedReg); ReusedOperands.markClobbered(DesignatedReg); MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); @@ -1209,13 +1211,13 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, Spills, MaybeDeadStores, RegKills, KillOps, VRM); - MF.setPhysRegUsed(PhysReg); + RegInfo->setPhysRegUsed(PhysReg); ReusedOperands.markClobbered(PhysReg); if (DoReMat) { MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); ++NumReMats; } else { - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); ++NumLoads; } @@ -1265,7 +1267,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { DOUT << "Promoted Load To Copy: " << MI; if (DestReg != InReg) { - const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); // Revisit the copy so we make sure to notice the effects of the // operation on the destreg (either needing to RA it if it's @@ -1310,8 +1312,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); SmallVector<MachineInstr*, 4> NewMIs; // We can reuse this physreg as long as we are allowed to clobber - // the value and there isn't an earlier def that has already clobbered the - // physreg. + // the value and there isn't an earlier def that has already clobbered + // the physreg. if (PhysReg && !TII->isStoreToStackSlot(&MI, SS) && // Not profitable! DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 && @@ -1425,7 +1427,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // The only vregs left are stack slot definitions. int StackSlot = VRM.getStackSlot(VirtReg); - const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); // If this def is part of a two-address operand, make sure to execute // the store from the correct physical register. @@ -1449,7 +1451,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { } } - MF.setPhysRegUsed(PhysReg); + RegInfo->setPhysRegUsed(PhysReg); unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; ReusedOperands.markClobbered(RReg); MI.getOperand(i).setReg(RReg); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index f56043f5fd..9b6825d1b2 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Debug.h" diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0415e19c0c..4d8a2372d0 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -24,12 +24,13 @@ #include "llvm/Constants.h" #include "llvm/Instruction.h" #include "llvm/Intrinsics.h" +#include "llvm/GlobalValue.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" #include "llvm/Support/MathExtras.h" @@ -685,16 +686,16 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { Op.getValue(1), Sign); } Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); - if (DAG.getMachineFunction().liveout_empty()) - DAG.getMachineFunction().addLiveOut(ARM::R0); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); break; case 5: Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. - if (DAG.getMachineFunction().liveout_empty()) { - DAG.getMachineFunction().addLiveOut(ARM::R0); - DAG.getMachineFunction().addLiveOut(ARM::R1); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); } break; } @@ -917,7 +918,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); SDOperand Root = Op.getOperand(0); std::vector<SDOperand> ArgValues; - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); static const unsigned GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 @@ -935,20 +936,20 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, SDOperand ArgValue; if (ObjGPRs == 1) { - unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); vRegs[NumGPRs] = VReg; ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); if (ObjectVT == MVT::f32) ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); } else if (ObjGPRs == 2) { - unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); vRegs[NumGPRs] = VReg; ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); - VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); + VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); vRegs[NumGPRs+1] = VReg; SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); @@ -1002,7 +1003,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { }; MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); @@ -1019,8 +1020,8 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { SmallVector<SDOperand, 4> MemOps; for (; NumGPRs < 4; ++NumGPRs) { - unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 979410a58f..8328cef934 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" @@ -1206,14 +1207,14 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; bool Spilled = false; - if (MF.isPhysRegUsed(Reg)) { + if (MF.getRegInfo().isPhysRegUsed(Reg)) { AFI->setCSRegisterIsSpilled(Reg); Spilled = true; CanEliminateFrame = false; } else { // Check alias registers too. for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { - if (MF.isPhysRegUsed(*Aliases)) { + if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { Spilled = true; CanEliminateFrame = false; } @@ -1286,7 +1287,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. // Spill LR as well so we can fold BX_RET to the registers restore (LDM). if (!LRSpilled && CS1Spilled) { - MF.setPhysRegUsed(ARM::LR); + MF.getRegInfo().setPhysRegUsed(ARM::LR); AFI->setCSRegisterIsSpilled(ARM::LR); NumGPRSpills++; UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), @@ -1298,7 +1299,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // Darwin ABI requires FP to point to the stack slot that contains the // previous FP. if (STI.isTargetDarwin() || hasFP(MF)) { - MF.setPhysRegUsed(FramePtr); + MF.getRegInfo().setPhysRegUsed(FramePtr); NumGPRSpills++; } @@ -1312,7 +1313,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, unsigned Reg = UnspilledCS1GPRs[i]; // Don't spiil high register if the function is thumb if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { - MF.setPhysRegUsed(Reg); + MF.getRegInfo().setPhysRegUsed(Reg); AFI->setCSRegisterIsSpilled(Reg); if (!isReservedReg(MF, Reg)) ExtraCSSpill = true; @@ -1322,7 +1323,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumbFunction()) { unsigned Reg = UnspilledCS2GPRs.front(); - MF.setPhysRegUsed(Reg); + MF.getRegInfo().setPhysRegUsed(Reg); AFI->setCSRegisterIsSpilled(Reg); if (!isReservedReg(MF, Reg)) ExtraCSSpill = true; @@ -1378,7 +1379,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } if (Extras.size() && NumExtras == 0) { for (unsigned i = 0, e = Extras.size(); i != e; ++i) { - MF.setPhysRegUsed(Extras[i]); + MF.getRegInfo().setPhysRegUsed(Extras[i]); AFI->setCSRegisterIsSpilled(Extras[i]); } } else { @@ -1392,7 +1393,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } if (ForceLRSpill) { - MF.setPhysRegUsed(ARM::LR); + MF.getRegInfo().setPhysRegUsed(ARM::LR); AFI->setCSRegisterIsSpilled(ARM::LR); AFI->setLRIsSpilledForFarJump(true); } @@ -1446,9 +1447,9 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { if (isThumb) { // Check if R3 is live in. It might have to be used as a scratch register. - for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); - I != E; ++I) { - if ((*I).first == ARM::R3) { + for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(), + E = MF.getRegInfo().livein_end(); I != E; ++I) { + if (I->first == ARM::R3) { AFI->setR3IsLiveIn(true); break; } diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 4b756b6582..0490f88bb4 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" @@ -200,10 +200,9 @@ private: /// GOT address into a register. /// SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { - MachineFunction* MF = BB->getParent(); unsigned GP = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R29) { GP = ii->second; break; @@ -216,10 +215,9 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { /// getRASaveReg - Grab the return address /// SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { - MachineFunction* MF = BB->getParent(); unsigned RA = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R26) { RA = ii->second; break; diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 295b456c0d..a37e8861bb 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -16,8 +16,9 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Module.h" @@ -30,8 +31,8 @@ using namespace llvm; static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) { assert(RC->contains(PReg) && "Not the correct regclass!"); - unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); - MF.addLiveIn(PReg, VReg); + unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); + MF.getRegInfo().addLiveIn(PReg, VReg); return VReg; } @@ -312,8 +313,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { ArgReg = Alpha::F0; } Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); - if (DAG.getMachineFunction().liveout_empty()) - DAG.getMachineFunction().addLiveOut(ArgReg); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) + DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg); break; } } diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index acd0c8bbfc..73e46fff1b 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -20,7 +20,6 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 941cde1237..7893e677fb 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -20,8 +20,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Intrinsics.h" @@ -902,7 +902,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SmallVector<SDOperand, 8> ArgValues; SDOperand Root = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; @@ -932,8 +932,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) } case MVT::i8: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R8CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R8CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i8); ++ArgRegIdx; } else { @@ -942,8 +942,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::i16: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R16CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R16CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i16); ++ArgRegIdx; } else { @@ -952,8 +952,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::i32: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); ++ArgRegIdx; } else { @@ -962,8 +962,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::i64: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R64CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); ++ArgRegIdx; } else { @@ -972,8 +972,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::f32: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R32FPRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32FPRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f32); ++ArgRegIdx; } else { @@ -982,8 +982,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::f64: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R64FPRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64FPRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f64); ++ArgRegIdx; } else { @@ -996,8 +996,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) case MVT::v8i16: case MVT::v16i8: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); ++ArgRegIdx; } else { @@ -1037,8 +1037,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) // result of va_next. SmallVector<SDOperand, 8> MemOps; for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::GPRCRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); @@ -1294,9 +1294,9 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { // If this is the first return lowered for this function, add the regs to the // liveout set for the function. - if (DAG.getMachineFunction().liveout_empty()) { + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { for (unsigned i = 0; i != RVLocs.size(); ++i) - DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } SDOperand Chain = Op.getOperand(0); @@ -1785,8 +1785,8 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { if (EltsFromV2 == 1 && monotonic) { // Compute mask and shuffle MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); - unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 SDOperand InitTempReg = @@ -1893,12 +1893,12 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { // the wacky side case MVT::v8i16: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SDOperand Chain = Op.getOperand(0); SDOperand rA = Op.getOperand(0); SDOperand rB = Op.getOperand(1); - unsigned FSMBIreg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - unsigned HiProdReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); + unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); SDOperand FSMBOp = DAG.getCopyToReg(Chain, FSMBIreg, @@ -1929,16 +1929,16 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { // intermediate products. case MVT::v16i8: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SDOperand Chain = Op.getOperand(0); SDOperand rA = Op.getOperand(0); SDOperand rB = Op.getOperand(1); SDOperand c8 = DAG.getConstant(8, MVT::i8); SDOperand c16 = DAG.getConstant(16, MVT::i8); - unsigned FSMBreg_2222 = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - unsigned LoProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - unsigned HiProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); + unsigned FSMBreg_2222 = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + unsigned LoProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + unsigned HiProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); SDOperand LLProd = DAG.getNode(SPUISD::MPY, MVT::v8i16, @@ -2024,7 +2024,7 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SDOperand A = Op.getOperand(0); SDOperand B = Op.getOperand(1); @@ -2033,11 +2033,11 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { unsigned VRegBR, VRegC; if (VT == MVT::f32) { - VRegBR = RegMap->createVirtualRegister(&SPU::R32FPRegClass); - VRegC = RegMap->createVirtualRegister(&SPU::R32FPRegClass); + VRegBR = RegInfo.createVirtualRegister(&SPU::R32FPRegClass); + VRegC = RegInfo.createVirtualRegister(&SPU::R32FPRegClass); } else { - VRegBR = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - VRegC = RegMap->createVirtualRegister(&SPU::VECREGRegClass); + VRegBR = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + VRegC = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); } // TODO: make sure we're feeding FPInterp the right arguments // Right now: fi B, frest(B) @@ -2066,18 +2066,6 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { DAG.getCopyFromReg(AxBRcpl, VRegC, VT))))); } -// Expands double-precision FDIV -// Expects two doubles as inputs X and Y, does a floating point -// reciprocal estimate, and three iterations of Newton-Raphson -// to increase accuracy. -//static SDOperand LowerFDIVf64(SDOperand Op, SelectionDAG &DAG) { -// MachineFunction &MF = DAG.getMachineFunction(); -// SSARegMap *RegMap = MF.getSSARegMap(); -// -// SDOperand X = Op.getOperand(0); -// SDOperand Y = Op.getOperand(1); -//} - static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { unsigned VT = Op.getValueType(); SDOperand N = Op.getOperand(0); @@ -2365,9 +2353,9 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { case MVT::i16: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); - unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R16CRegClass); + unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass); SDOperand N = Op.getOperand(0); SDOperand Elt0 = DAG.getConstant(0, MVT::i16); @@ -2397,10 +2385,10 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { case MVT::i32: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); - unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass); - unsigned SUM1_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass); + unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); + unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); SDOperand N = Op.getOperand(0); SDOperand Elt0 = DAG.getConstant(0, MVT::i32); diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 9f8dbeede7..ec886d5680 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -27,6 +27,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Target/TargetFrameInfo.h" @@ -670,15 +671,15 @@ void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, #if 0 // Save and clear the LR state. SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>(); - FI->setUsesLR(MF.isPhysRegUsed(LR)); + FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); #endif // Mark LR and SP unused, since the prolog spills them to stack and // we don't want anyone else to spill them for us. // // Also, unless R2 is really used someday, don't spill it automatically. - MF.setPhysRegUnused(SPU::R0); - MF.setPhysRegUnused(SPU::R1); - MF.setPhysRegUnused(SPU::R2); + MF.getRegInfo().setPhysRegUnused(SPU::R0); + MF.getRegInfo().setPhysRegUnused(SPU::R1); + MF.getRegInfo().setPhysRegUnused(SPU::R2); } void SPURegisterInfo::emitPrologue(MachineFunction &MF) const diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 0d9aeb3ac4..af31aaf555 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -18,7 +18,6 @@ #include "IA64ISelLowering.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index c02cd1bcc7..b6b6c256e4 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" using namespace llvm; @@ -148,9 +148,9 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { MachineFrameInfo *MFI = MF.getFrameInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); MachineBasicBlock& BB = MF.front(); @@ -182,10 +182,11 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // see intel ABI docs) case MVT::f64: //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]); - MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn + MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]); + // mark this reg as liveIn // floating point args go into f8..f15 as-needed, the increment argVreg[count] = // is below..: - MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64)); + MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64)); // FP args go into f8..f15 as needed: (hence the ++) argPreg[count] = args_FP[used_FPArgs++]; argOpc[count] = IA64::FMOV; @@ -201,9 +202,10 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i32: case MVT::i64: //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]); - MF.addLiveIn(args_int[count]); // mark this register as liveIn + MF.getRegInfo().addLiveIn(args_int[count]); + // mark this register as liveIn argVreg[count] = - MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); argPreg[count] = args_int[count]; argOpc[count] = IA64::MOV; argt = newroot = @@ -232,7 +234,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Create a vreg to hold the output of (what will become) // the "alloc" instruction - VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now /* @@ -284,11 +286,11 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i16: case MVT::i32: case MVT::i64: - MF.addLiveOut(IA64::r8); + MF.getRegInfo().addLiveOut(IA64::r8); break; case MVT::f32: case MVT::f64: - MF.addLiveOut(IA64::F8); + MF.getRegInfo().addLiveOut(IA64::F8); break; } diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index e00625c974..b570824594 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -23,11 +23,11 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Support/CommandLine.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" using namespace llvm; @@ -328,8 +328,8 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { IA64::r126, IA64::r127 }; unsigned numStackedGPRsUsed=0; - for(int i=0; i<96; i++) { - if(MF.isPhysRegUsed(RegsInOrder[i])) + for (int i=0; i != 96; i++) { + if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i])) numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int) } diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 07330ee110..b2ad66670b 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mips-isel" - #include "Mips.h" #include "MipsISelLowering.h" #include "MipsMachineFunction.h" @@ -28,6 +27,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Compiler.h" @@ -127,12 +127,11 @@ InstructionSelectBasicBlock(SelectionDAG &SD) /// getGlobalBaseReg - Output the instructions required to put the /// GOT address into a register. -SDOperand MipsDAGToDAGISel::getGlobalBaseReg() -{ +SDOperand MipsDAGToDAGISel::getGlobalBaseReg() { MachineFunction* MF = BB->getParent(); unsigned GP = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(), + ee = MF->getRegInfo().livein_end(); ii != ee; ++ii) if (ii->first == Mips::GP) { GP = ii->second; break; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index d17c980b37..56527ebc33 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -25,8 +25,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Support/Debug.h" #include <queue> @@ -139,8 +139,8 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) { assert(RC->contains(PReg) && "Not the correct regclass!"); - unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); - MF.addLiveIn(PReg, VReg); + unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); + MF.getRegInfo().addLiveIn(PReg, VReg); return VReg; } @@ -596,10 +596,10 @@ LowerRET(SDOperand Op, SelectionDAG &DAG) // If this is the first return lowered for this function, add // the regs to the liveout set for the function. - if (DAG.getMachineFunction().liveout_empty()) { + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { for (unsigned i = 0; i != RVLocs.size(); ++i) if (RVLocs[i].isRegLoc()) - DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } // The chain is always operand #0 diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 767fd99914..2c5e3fcdd8 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -20,7 +20,7 @@ #include "PPCHazardRecognizers.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" @@ -224,11 +224,10 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // In this case, there will be virtual registers of vector type type created // by the scheduler. Detect them now. MachineFunction &Fn = MachineFunction::get(&F); - SSARegMap *RegMap = Fn.getSSARegMap(); bool HasVectorVReg = false; for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = RegMap->getLastVirtReg()+1; i != e; ++i) - if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) { + e = RegInfo->getLastVirtReg()+1; i != e; ++i) + if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { HasVectorVReg = true; break; } @@ -246,8 +245,8 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // Create two vregs - one to hold the VRSAVE register that is live-in to the // function and one for the value after having bits or'd into it. - unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); const TargetInstrInfo &TII = *TM.getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); @@ -287,14 +286,13 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = BB->getParent()->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); - SSARegMap *RegMap = BB->getParent()->getSSARegMap(); if (PPCLowering.getPointerTy() == MVT::i32) { - GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass); + GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR); BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg); } else { - GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass); + GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8); BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 0ac1682373..66915eb9ae 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -23,8 +23,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Intrinsics.h" @@ -1265,7 +1265,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, // MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SmallVector<SDOperand, 8> ArgValues; SDOperand Root = Op.getOperand(0); @@ -1329,8 +1329,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, // Double word align in ELF if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); if (GPR_idx != Num_GPR_Regs) { - unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - MF.addLiveIn(GPR[GPR_idx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); + RegInfo.addLiveIn(GPR[GPR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); ++GPR_idx; } else { @@ -1346,8 +1346,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, case MVT::i64: // PPC64 if (GPR_idx != Num_GPR_Regs) { - unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); - MF.addLiveIn(GPR[GPR_idx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); + RegInfo.addLiveIn(GPR[GPR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); ++GPR_idx; } else { @@ -1369,10 +1369,10 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, if (FPR_idx != Num_FPR_Regs) { unsigned VReg; if (ObjectVT == MVT::f32) - VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); + VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); else - VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); - MF.addLiveIn(FPR[FPR_idx], VReg); + VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); + RegInfo.addLiveIn(FPR[FPR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); ++FPR_idx; } else { @@ -1391,8 +1391,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, case MVT::v16i8: // Note that vector arguments in registers don't reserve stack space. if (VR_idx != Num_VR_Regs) { - unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); - MF.addLiveIn(VR[VR_idx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); + RegInfo.addLiveIn(VR[VR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); ++VR_idx; } else { @@ -1471,11 +1471,11 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { unsigned VReg; if (isPPC64) - VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); + VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); else - VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); - MF.addLiveIn(GPR[GPR_idx], VReg); + RegInfo.addLiveIn(GPR[GPR_idx], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); @@ -1499,9 +1499,9 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { unsigned VReg; - VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); + VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); - MF.addLiveIn(FPR[FPR_idx], VReg); + RegInfo.addLiveIn(FPR[FPR_idx], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); @@ -1905,9 +1905,9 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { // If this is the first return lowered for this function, add the regs to the // liveout set for the function. - if (DAG.getMachineFunction().liveout_empty()) { + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { for (unsigned i = 0; i != RVLocs.size(); ++i) - DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } SDOperand Chain = Op.getOperand(0); diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 84ff7edf19..3c8bc9f73e 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -26,6 +26,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -911,19 +912,21 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { unsigned UsedRegMask = 0; for (unsigned i = 0; i != 32; ++i) - if (MF->isPhysRegUsed(VRRegNo[i])) + if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) UsedRegMask |= 1 << (31-i); // Live in and live out values already must be in the mask, so don't bother // marking them. - for (MachineFunction::livein_iterator I = - MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { + for (MachineRegisterInfo::livein_iterator + I = MF->getRegInfo().livein_begin(), + E = MF->getRegInfo().livein_end(); I != E; ++I) { unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. } - for (MachineFunction::liveout_iterator I = - MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { + for (MachineRegisterInfo::liveout_iterator + I = MF->getRegInfo().liveout_begin(), + E = MF->getRegInfo().liveout_end(); I != E; ++I) { unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); if (VRRegNo[RegNo] == *I) // If this really is a vector reg. UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. @@ -1012,8 +1015,8 @@ void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // Save and clear the LR state. PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); unsigned LR = getRARegister(); - FI->setUsesLR(MF.isPhysRegUsed(LR)); - MF.setPhysRegUnused(LR); + FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); + MF.getRegInfo().setPhysRegUnused(LR); // Save R31 if necessary int FPSI = FI->getFramePointerSaveIndex(); @@ -1023,8 +1026,8 @@ void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, const MachineFrameInfo *MFI = MF.getFrameInfo(); // If the frame pointer save index hasn't been defined yet. - if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) - && IsELF32_ABI) { + if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && + IsELF32_ABI) { // Find out what the fix offset of the frame pointer save area. int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 040bcd5432..df63f20d85 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -19,9 +19,9 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Support/Debug.h" #include <queue> @@ -298,7 +298,7 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, std::vector<SDOperand> SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); std::vector<SDOperand> ArgValues; static const unsigned ArgRegs[] = { @@ -324,8 +324,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { if (CurArgReg < ArgRegEnd) ++CurArgReg; ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR - unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); - MF.addLiveIn(*CurArgReg++, VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); if (ObjectVT != MVT::i32) { unsigned AssertOp = ISD::AssertSext; @@ -362,8 +362,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR // FP value is passed in an integer register. - unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); - MF.addLiveIn(*CurArgReg++, VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); @@ -396,8 +396,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } else { SDOperand HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR - unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); - MF.addLiveIn(*CurArgReg++, VRegHi); + unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); @@ -407,8 +407,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SDOperand LoVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR - unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); - MF.addLiveIn(*CurArgReg++, VRegLo); + unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); @@ -437,8 +437,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { VarArgsFrameOffset = ArgOffset; for (; CurArgReg != ArgRegEnd; ++CurArgReg) { - unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); - MF.addLiveIn(*CurArgReg, VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + MF.getRegInfo().addLiveIn(*CurArgReg, VReg); SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); @@ -461,17 +461,17 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i8: case MVT::i16: case MVT::i32: - MF.addLiveOut(SP::I0); + MF.getRegInfo().addLiveOut(SP::I0); break; case MVT::i64: - MF.addLiveOut(SP::I0); - MF.addLiveOut(SP::I1); + MF.getRegInfo().addLiveOut(SP::I0); + MF.getRegInfo().addLiveOut(SP::I1); break; case MVT::f32: - MF.addLiveOut(SP::F0); + MF.getRegInfo().addLiveOut(SP::F0); break; case MVT::f64: - MF.addLiveOut(SP::D0); + MF.getRegInfo().addLiveOut(SP::D0); break; } diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index f36b80da11..354804ce5c 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -33,6 +33,7 @@ #include "X86InstrInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetInstrInfo.h" @@ -169,7 +170,7 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) { assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); for (unsigned i = 0; i <= 6; ++i) - if (MF.isPhysRegUsed(X86::FP0+i)) { + if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { FPIsUsed = true; break; } diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index fa34323828..8c5cd48e09 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -28,7 +28,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Compiler.h" @@ -504,7 +504,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() && MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && - ((clas = RegMap->getRegClass(I->getOperand(0).getReg())) == + ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == X86::RFP32RegisterClass || clas == X86::RFP64RegisterClass || clas == X86::RFP80RegisterClass)) { @@ -990,8 +990,8 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() { // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = BB->getParent()->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); - SSARegMap *RegMap = BB->getParent()->getSSARegMap(); - unsigned PC = RegMap->createVirtualRegister(X86::GR32RegisterClass); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); const TargetInstrInfo *TII = TM.getInstrInfo(); // Operand of MovePCtoStack is completely ignored by asm printer. It's @@ -1003,7 +1003,7 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() { // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external if (TM.getRelocationModel() == Reloc::PIC_ && Subtarget->isPICStyleGOT()) { - GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass); + GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg). addReg(PC). addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4d17f55a95..a4e69c54c4 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -30,8 +30,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Target/TargetOptions.h" @@ -703,10 +703,10 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { // If this is the first return lowered for this function, add the regs to the // liveout set for the function. - if (DAG.getMachineFunction().liveout_empty()) { + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { for (unsigned i = 0; i != RVLocs.size(); ++i) if (RVLocs[i].isRegLoc()) - DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } SDOperand Chain = Op.getOperand(0); @@ -933,8 +933,8 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) { assert(RC->contains(PReg) && "Not the correct regclass!"); - unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); - MF.addLiveIn(PReg, VReg); + unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); + MF.getRegInfo().addLiveIn(PReg, VReg); return VReg; } @@ -1754,7 +1754,7 @@ SDOperand X86TargetLowering::LowerX86_TailCallTo(SDOperand Op, Callee,InFlag); Callee = DAG.getRegister(Opc, getPointerTy()); // Add register as live out. - DAG.getMachineFunction().addLiveOut(Opc); + DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); } SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); @@ -5288,7 +5288,7 @@ SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG) StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr); - MF.addLiveOut(X86::ECX); + MF.getRegInfo().addLiveOut(X86::ECX); return DAG.getNode(X86ISD::EH_RETURN, MVT::Other, Chain, DAG.getRegister(X86::ECX, getPointerTy())); @@ -5802,7 +5802,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, // Load the old value of the high byte of the control word... unsigned OldCW = - F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass); + F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); // Set the high part to be round to zero... diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 3403f1c4d0..3470baa493 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -19,8 +19,8 @@ #include "X86TargetMachine.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/LiveVariables.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -316,11 +316,11 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, if (DisableLEA16) { // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. - SSARegMap *RegMap = MFI->getParent()->getSSARegMap(); + MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? X86::LEA64_32r : X86::LEA32r; - unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass); - unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass); + unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); + unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); MachineInstr *Ins = BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 07c25914a2..788bcc6c4a 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -26,7 +26,8 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetAsmInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -1843,8 +1844,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) { // Check, whether EAX is livein for this function bool isEAXAlive = false; - for (MachineFunction::livein_iterator II = MF.livein_begin(), - EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) { + for (MachineRegisterInfo::livein_iterator + II = MF.getRegInfo().livein_begin(), + EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) { unsigned Reg = II->first; isEAXAlive = (Reg == X86::EAX || Reg == X86::AX || Reg == X86::AH || Reg == X86::AL); @@ -1904,7 +1906,8 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); } else { MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth); + MachineLocation SPSrc(MachineLocation::VirtualFP, + -StackSize+stackGrowth); Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); } } else { |