diff options
Diffstat (limited to 'lib/Target')
34 files changed, 565 insertions, 707 deletions
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 528e5abdd3..ea41b6f822 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -18,10 +18,12 @@ #include "llvm/Instruction.h" #include "Support/CommandLine.h" #include "SchedPriorities.h" -#include <hash_set> #include <algorithm> #include <iterator> - +#include <ext/hash_set> +#include <iostream> +using std::cerr; +using std::vector; //************************* External Data Types *****************************/ @@ -353,11 +355,11 @@ private: unsigned int totalInstrCount; cycles_t curTime; cycles_t nextEarliestIssueTime; // next cycle we can issue - vector<hash_set<const SchedGraphNode*> > choicesForSlot; // indexed by slot# + vector<std::hash_set<const SchedGraphNode*> > choicesForSlot; // indexed by slot# vector<const SchedGraphNode*> choiceVec; // indexed by node ptr vector<int> numInClass; // indexed by sched class vector<cycles_t> nextEarliestStartTime; // indexed by opCode - hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches; + std::hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches; // indexed by branch node ptr public: @@ -419,7 +421,7 @@ public: return choiceVec[i]; } - inline hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) { + inline std::hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) { assert(slotNum < nslots); return choicesForSlot[slotNum]; } @@ -495,7 +497,7 @@ public: bool createIfMissing=false) { DelaySlotInfo* dinfo; - hash_map<const SchedGraphNode*, DelaySlotInfo* >::const_iterator + std::hash_map<const SchedGraphNode*, DelaySlotInfo* >::const_iterator I = delaySlotInfoForBranches.find(bn); if (I == delaySlotInfoForBranches.end()) { @@ -552,7 +554,7 @@ SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node, { if (schedInfo.numBubblesAfter(node->getOpCode()) > 0) { // Update next earliest time before which *nothing* can issue. - nextEarliestIssueTime = max(nextEarliestIssueTime, + nextEarliestIssueTime = std::max(nextEarliestIssueTime, curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode())); } @@ -603,7 +605,7 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue) unsigned numIssued; for (numIssued = 0; numIssued < maxIssue; numIssued++) { - int chosenSlot = -1, chosenNodeIndex = -1; + int chosenSlot = -1; for (unsigned s=startSlot; s < S.nslots; s++) if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1) { @@ -877,7 +879,7 @@ FindSlotChoices(SchedulingManager& S, assert(s < S.nslots && "No feasible slot for instruction?"); - highestSlotUsed = max(highestSlotUsed, (int) s); + highestSlotUsed = std::max(highestSlotUsed, (int) s); } assert(highestSlotUsed <= (int) S.nslots-1 && "Invalid slot used?"); @@ -961,7 +963,6 @@ FindSlotChoices(SchedulingManager& S, // Otherwise, just ignore the instruction. for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) { - bool foundLowerSlot = false; MachineOpCode opCode = S.getChoice(i)->getOpCode(); for (unsigned int s=startSlot; s < nslotsToUse; s++) if (S.schedInfo.instrCanUseSlot(opCode, s)) @@ -1001,15 +1002,15 @@ ChooseOneGroup(SchedulingManager& S) { for (cycles_t c = firstCycle; c <= S.getTime(); c++) { - cout << " Cycle " << c << " : Scheduled instructions:\n"; + cerr << " Cycle " << (long)c << " : Scheduled instructions:\n"; const InstrGroup* igroup = S.isched.getIGroup(c); for (unsigned int s=0; s < S.nslots; s++) { - cout << " "; + cerr << " "; if ((*igroup)[s] != NULL) - cout << * ((*igroup)[s])->getMachineInstr() << endl; + cerr << * ((*igroup)[s])->getMachineInstr() << "\n"; else - cout << "<none>" << endl; + cerr << "<none>\n"; } } } @@ -1056,9 +1057,9 @@ ForwardListSchedule(SchedulingManager& S) // an instruction can be issued, or the next earliest in which // one will be ready, or to the next cycle, whichever is latest. // - S.updateTime(max(S.getTime() + 1, - max(S.getEarliestIssueTime(), - S.schedPrio.getEarliestReadyTime()))); + S.updateTime(std::max(S.getTime() + 1, + std::max(S.getEarliestIssueTime(), + S.schedPrio.getEarliestReadyTime()))); } } @@ -1499,8 +1500,7 @@ ScheduleInstructionsWithSSA(Method* method, if (SchedDebugLevel >= Sched_PrintSchedGraphs) { - cout << endl << "*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING" - << endl; + cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; graphSet.dump(); } @@ -1513,7 +1513,7 @@ ScheduleInstructionsWithSSA(Method* method, const BasicBlock* bb = bbvec[0]; if (SchedDebugLevel >= Sched_PrintSchedTrace) - cout << endl << "*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n"; + cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n"; SchedPriorities schedPrio(method, graph); // expensive! SchedulingManager S(target, graph, schedPrio); @@ -1527,8 +1527,7 @@ ScheduleInstructionsWithSSA(Method* method, if (SchedDebugLevel >= Sched_PrintMachineCode) { - cout << endl - << "*** Machine instructions after INSTRUCTION SCHEDULING" << endl; + cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n"; MachineCodeForMethod::get(method).dump(); } diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index 9e9af5b80d..7c83e1a58c 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -23,10 +23,16 @@ #include "llvm/Target/MachineRegInfo.h" #include "llvm/iOther.h" #include "Support/StringExtras.h" +#include "Support/STLExtras.h" #include <algorithm> -#include <hash_map> #include <vector> +#include <iostream> +#include <ext/hash_map> +using std::vector; +using std::pair; +using std::hash_map; +using std::cerr; //*********************** Internal Data Structures *************************/ @@ -132,7 +138,7 @@ SchedGraphEdge::~SchedGraphEdge() } void SchedGraphEdge::dump(int indent=0) const { - cout << string(indent*2, ' ') << *this; + cerr << std::string(indent*2, ' ') << *this; } @@ -168,7 +174,7 @@ SchedGraphNode::~SchedGraphNode() } void SchedGraphNode::dump(int indent=0) const { - cout << string(indent*2, ' ') << *this; + cerr << std::string(indent*2, ' ') << *this; } @@ -222,21 +228,20 @@ SchedGraph::SchedGraph(const BasicBlock* bb, const TargetMachine& target) { bbVec.push_back(bb); - this->buildGraph(target); + buildGraph(target); } /*dtor*/ SchedGraph::~SchedGraph() { - for (iterator I=begin(); I != end(); ++I) + for (const_iterator I = begin(); I != end(); ++I) { - SchedGraphNode* node = (*I).second; + SchedGraphNode *node = I->second; // for each node, delete its out-edges - for (SchedGraphNode::iterator I = node->beginOutEdges(); - I != node->endOutEdges(); ++I) - delete *I; + std::for_each(node->beginOutEdges(), node->endOutEdges(), + deleter<SchedGraphEdge>); // then delete the node itself. delete node; @@ -247,24 +252,24 @@ SchedGraph::~SchedGraph() void SchedGraph::dump() const { - cout << " Sched Graph for Basic Blocks: "; + cerr << " Sched Graph for Basic Blocks: "; for (unsigned i=0, N=bbVec.size(); i < N; i++) { - cout << (bbVec[i]->hasName()? bbVec[i]->getName() : "block") + cerr << (bbVec[i]->hasName()? bbVec[i]->getName() : "block") << " (" << bbVec[i] << ")" << ((i == N-1)? "" : ", "); } - cout << endl << endl << " Actual Root nodes : "; + cerr << "\n\n Actual Root nodes : "; for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++) - cout << graphRoot->outEdges[i]->getSink()->getNodeId() + cerr << graphRoot->outEdges[i]->getSink()->getNodeId() << ((i == N-1)? "" : ", "); - cout << endl << " Graph Nodes:" << endl; + cerr << "\n Graph Nodes:\n"; for (const_iterator I=begin(); I != end(); ++I) - cout << endl << * (*I).second; + cerr << "\n" << *I->second; - cout << endl; + cerr << "\n"; } @@ -690,7 +695,7 @@ SchedGraph::addNonSSAEdgesForValue(const Instruction* instr, // this operand is a definition or use of value `instr' SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]); assert(node && "No node for machine instruction in this BB?"); - refVec.push_back(make_pair(node, o)); + refVec.push_back(std::make_pair(node, o)); } } @@ -747,8 +752,8 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, { int regNum = mop.getMachineRegNum(); if (regNum != target.getRegInfo().getZeroRegNum()) - regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, - i)); + regToRefVecMap[mop.getMachineRegNum()].push_back( + std::make_pair(node, i)); continue; // nothing more to do } @@ -762,7 +767,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, && "Do not expect any other kind of operand to be defined!"); const Instruction* defInstr = cast<Instruction>(mop.getVRegValue()); - valueToDefVecMap[defInstr].push_back(make_pair(node, i)); + valueToDefVecMap[defInstr].push_back(std::make_pair(node, i)); } // @@ -774,7 +779,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, if (const Instruction* defInstr = dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i))) { - valueToDefVecMap[defInstr].push_back(make_pair(node, -i)); + valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i)); } } @@ -860,7 +865,6 @@ SchedGraph::buildNodesforBB(const TargetMachine& target, void SchedGraph::buildGraph(const TargetMachine& target) { - const MachineInstrInfo& mii = target.getInstrInfo(); const BasicBlock* bb = bbVec[0]; assert(bbVec.size() == 1 && "Only handling a single basic block here"); @@ -966,24 +970,22 @@ SchedGraphSet::SchedGraphSet(const Method* _method, SchedGraphSet::~SchedGraphSet() { // delete all the graphs - for (iterator I=begin(); I != end(); ++I) - delete (*I).second; + for (const_iterator I = begin(); I != end(); ++I) + delete I->second; } void SchedGraphSet::dump() const { - cout << "======== Sched graphs for method `" - << (method->hasName()? method->getName() : "???") - << "' ========" << endl << endl; + cerr << "======== Sched graphs for method `" << method->getName() + << "' ========\n\n"; for (const_iterator I=begin(); I != end(); ++I) - (*I).second->dump(); + I->second->dump(); - cout << endl << "====== End graphs for method `" - << (method->hasName()? method->getName() : "") - << "' ========" << endl << endl; + cerr << "\n====== End graphs for method `" << method->getName() + << "' ========\n\n"; } @@ -1000,8 +1002,7 @@ SchedGraphSet::buildGraphsForMethod(const Method *method, -ostream& -operator<<(ostream& os, const SchedGraphEdge& edge) +std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge) { os << "edge [" << edge.src->getNodeId() << "] -> [" << edge.sink->getNodeId() << "] : "; @@ -1015,33 +1016,30 @@ operator<<(ostream& os, const SchedGraphEdge& edge) default: assert(0); break; } - os << " : delay = " << edge.minDelay << endl; + os << " : delay = " << edge.minDelay << "\n"; return os; } -ostream& -operator<<(ostream& os, const SchedGraphNode& node) +std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node) { - os << string(8, ' ') + os << std::string(8, ' ') << "Node " << node.nodeId << " : " - << "latency = " << node.latency << endl << string(12, ' '); + << "latency = " << node.latency << "\n" << std::string(12, ' '); if (node.getMachineInstr() == NULL) - os << "(Dummy node)" << endl; + os << "(Dummy node)\n"; else { - os << *node.getMachineInstr() << endl << string(12, ' '); - os << node.inEdges.size() << " Incoming Edges:" << endl; + os << *node.getMachineInstr() << "\n" << std::string(12, ' '); + os << node.inEdges.size() << " Incoming Edges:\n"; for (unsigned i=0, N=node.inEdges.size(); i < N; i++) - os << string(16, ' ') << *node.inEdges[i]; + os << std::string(16, ' ') << *node.inEdges[i]; - os << string(12, ' ') << node.outEdges.size() - << " Outgoing Edges:" << endl; + os << std::string(12, ' ') << node.outEdges.size() + << " Outgoing Edges:\n"; for (unsigned i=0, N=node.outEdges.size(); i < N; i++) - { - os << string(16, ' ') << * node.outEdges[i]; - } + os << std::string(16, ' ') << *node.outEdges[i]; } return os; diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.h b/lib/Target/SparcV9/InstrSched/SchedGraph.h index a4567a5198..2890241d59 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.h +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.h @@ -24,7 +24,7 @@ #include "Support/NonCopyable.h" #include "Support/HashExtras.h" #include "Support/GraphTraits.h" -#include <hash_map> +#include <ext/hash_map> class Value; class Instruction; @@ -128,7 +128,7 @@ public: // // Debugging support // - friend ostream& operator<<(ostream& os, const SchedGraphEdge& edge); + friend std::ostream& operator<<(std::ostream& os, const SchedGraphEdge& edge); void dump (int indent=0) const; @@ -144,16 +144,16 @@ private: unsigned int nodeId; const BasicBlock* bb; const MachineInstr* minstr; - vector<SchedGraphEdge*> inEdges; - vector<SchedGraphEdge*> outEdges; + std::vector<SchedGraphEdge*> inEdges; + std::vector<SchedGraphEdge*> outEdges; int origIndexInBB; // original position of machine instr in BB int latency; public: - typedef vector<SchedGraphEdge*>:: iterator iterator; - typedef vector<SchedGraphEdge*>::const_iterator const_iterator; - typedef vector<SchedGraphEdge*>:: reverse_iterator reverse_iterator; - typedef vector<SchedGraphEdge*>::const_reverse_iterator const_reverse_iterator; + typedef std::vector<SchedGraphEdge*>:: iterator iterator; + typedef std::vector<SchedGraphEdge*>::const_iterator const_iterator; + typedef std::vector<SchedGraphEdge*>:: reverse_iterator reverse_iterator; + typedef std::vector<SchedGraphEdge*>::const_reverse_iterator const_reverse_iterator; public: // @@ -186,7 +186,7 @@ public: // // Debugging support // - friend ostream& operator<<(ostream& os, const SchedGraphNode& node); + friend std::ostream& operator<<(std::ostream& os, const SchedGraphNode& node); void dump (int indent=0) const; @@ -214,22 +214,23 @@ private: class SchedGraph : public NonCopyable, - private hash_map<const MachineInstr*, SchedGraphNode*> + private std::hash_map<const MachineInstr*, SchedGraphNode*> { private: - vector<const BasicBlock*> bbVec; // basic blocks included in the graph + std::vector<const BasicBlock*> bbVec; // basic blocks included in the graph SchedGraphNode* graphRoot; // the root and leaf are not inserted SchedGraphNode* graphLeaf; // in the hash_map (see getNumNodes()) + typedef std::hash_map<const MachineInstr*, SchedGraphNode*> map_base; public: - typedef hash_map<const MachineInstr*, SchedGraphNode*>::iterator iterator; - typedef hash_map<const MachineInstr*, SchedGraphNode*>::const_iterator const_iterator; + using map_base::iterator; + using map_base::const_iterator; public: // // Accessor methods // - const vector<const BasicBlock*>& getBasicBlocks() const { return bbVec; } + const std::vector<const BasicBlock*>& getBasicBlocks() const { return bbVec; } const unsigned int getNumNodes() const { return size()+2; } SchedGraphNode* getRoot() const { return graphRoot; } SchedGraphNode* getLeaf() const { return graphLeaf; } @@ -257,19 +258,9 @@ public: // Unordered iterators. // Return values is pair<const MachineIntr*,SchedGraphNode*>. // - iterator begin() { - return hash_map<const MachineInstr*, SchedGraphNode*>::begin(); - } - iterator end() { - return hash_map<const MachineInstr*, SchedGraphNode*>::end(); - } - const_iterator begin() const { - return hash_map<const MachineInstr*, SchedGraphNode*>::begin(); - } - const_iterator end() const { - return hash_map<const MachineInstr*, SchedGraphNode*>::end(); - } - + using map_base::begin; + using map_base::end; + // // Ordered iterators. // Return values is pair<const MachineIntr*,SchedGraphNode*>. @@ -308,13 +299,13 @@ private: void buildNodesforBB (const TargetMachine& target, const BasicBlock* bb, - vector<SchedGraphNode*>& memNodeVec, + std::vector<SchedGraphNode*>& memNod, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap); void findDefUseInfoAtInstr (const TargetMachine& target, SchedGraphNode* node, - vector<SchedGraphNode*>& memNodeVec, + std::vector<SchedGraphNode*>& memNode, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap); @@ -325,10 +316,10 @@ private: void addCDEdges (const TerminatorInst* term, const TargetMachine& target); - void addMemEdges (const vector<SchedGraphNode*>& memNodeVec, + void addMemEdges (const std::vector<SchedGraphNode*>& memNod, const TargetMachine& target); - void addCallCCEdges (const vector<SchedGraphNode*>& memNodeVec, + void addCallCCEdges (const std::vector<SchedGraphNode*>& memNod, MachineCodeForBasicBlock& bbMvec, const TargetMachine& target); @@ -347,14 +338,15 @@ private: class SchedGraphSet : public NonCopyable, - private hash_map<const BasicBlock*, SchedGraph*> + private std::hash_map<const BasicBlock*, SchedGraph*> { private: const Method* method; public: - typedef hash_map<const BasicBlock*, SchedGraph*>::iterator iterator; - typedef hash_map<const BasicBlock*, SchedGraph*>::const_iterator const_iterator; + typedef std::hash_map<const BasicBlock*, SchedGraph*> map_base; + using map_base::iterator; + using map_base::const_iterator; public: /*ctor*/ SchedGraphSet (const Method* _method, @@ -372,18 +364,8 @@ public: // // Iterators // - iterator begin() { - return hash_map<const BasicBlock*, SchedGraph*>::begin(); - } - iterator end() { - return hash_map<const BasicBlock*, SchedGraph*>::end(); - } - const_iterator begin() const { - return hash_map<const BasicBlock*, SchedGraph*>::begin(); - } - const_iterator end() const { - return hash_map<const BasicBlock*, SchedGraph*>::end(); - } + using map_base::begin; + using map_base::end; // // Debugging support @@ -544,14 +526,7 @@ template <> struct GraphTraits<const SchedGraph*> { }; -//************************ External Functions *****************************/ - - -ostream& operator<<(ostream& os, const SchedGraphEdge& edge); - -ostream& operator<<(ostream& os, const SchedGraphNode& node); - - -/***************************************************************************/ +std::ostream &operator<<(std::ostream& os, const SchedGraphEdge& edge); +std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node); #endif diff --git a/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp b/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp index 1769707238..8cde252115 100644 --- a/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp @@ -20,20 +20,17 @@ #include "SchedPriorities.h" #include "Support/PostOrderIterator.h" - +#include <iostream> +using std::cerr; SchedPriorities::SchedPriorities(const Method* method, const SchedGraph* _graph) : curTime(0), graph(_graph), - methodLiveVarInfo(method), // expensive! - lastUseMap(), - nodeDelayVec(_graph->getNumNodes(),INVALID_LATENCY), //make errors obvious + methodLiveVarInfo(method), // expensive! + nodeDelayVec(_graph->getNumNodes(), INVALID_LATENCY), // make errors obvious earliestForNode(_graph->getNumNodes(), 0), earliestReadyTime(0), - candsAsHeap(), - candsAsSet(), - mcands(), nextToTry(candsAsHeap.begin()) { methodLiveVarInfo.analyze(); @@ -66,7 +63,7 @@ SchedPriorities::computeDelays(const SchedGraph* graph) E != node->endOutEdges(); ++E) { cycles_t sinkDelay = getNodeDelayRef((*E)->getSink()); - nodeDelay = max(nodeDelay, sinkDelay + (*E)->getMinDelay()); + nodeDelay = std::max(nodeDelay, sinkDelay + (*E)->getMinDelay()); } } getNodeDelayRef(node) = nodeDelay; @@ -87,20 +84,37 @@ SchedPriorities::initializeReadyHeap(const SchedGraph* graph) #undef TEST_HEAP_CONVERSION #ifdef TEST_HEAP_CONVERSION - cout << "Before heap conversion:" << endl; + cerr << "Before heap conversion:\n"; copy(candsAsHeap.begin(), candsAsHeap.end(), - ostream_iterator<NodeDelayPair*>(cout,"\n")); + ostream_iterator<NodeDelayPair*>(cerr,"\n")); #endif candsAsHeap.makeHeap(); #ifdef TEST_HEAP_CONVERSION - cout << "After heap conversion:" << endl; + cerr << "After heap conversion:\n"; copy(candsAsHeap.begin(), candsAsHeap.end(), - ostream_iterator<NodeDelayPair*>(cout,"\n")); + ostream_iterator<NodeDelayPair*>(cerr,"\n")); #endif } +void +SchedPriorities::insertReady(const SchedGraphNode* node) +{ + candsAsHeap.insert(node, nodeDelayVec[node->getNodeId()]); + candsAsSet.insert(node); + mcands.clear(); // ensure reset choices is called before any more choices + earliestReadyTime = std::min(earliestReadyTime, + earliestForNode[node->getNodeId()]); + + if (SchedDebugLevel >= Sched_PrintSchedTrace) + { + cerr << " Cycle " << (long)getTime() << ": " + << " Node " << node->getNodeId() << " is ready; " + << " Delay = " << (long)getNodeDelayRef(node) << "; Instruction: \n"; + cerr << " " << *node->getMachineInstr() << "\n"; + } +} void SchedPriorities::issuedReadyNodeAt(cycles_t curTime, @@ -116,7 +130,7 @@ SchedPriorities::issuedReadyNodeAt(cycles_t curTime, for (NodeHeap::const_iterator I=candsAsHeap.begin(); I != candsAsHeap.end(); ++I) if (candsAsHeap.getNode(I)) - earliestReadyTime = min(earliestReadyTime, + earliestReadyTime = std::min(earliestReadyTime, getEarliestForNodeRef(candsAsHeap.getNode(I))); } @@ -125,7 +139,7 @@ SchedPriorities::issuedReadyNodeAt(cycles_t curTime, E != node->endOutEdges(); ++E) { cycles_t& etime = getEarliestForNodeRef((*E)->getSink()); - etime = max(etime, curTime + (*E)->getMinDelay()); + etime = std::max(etime, curTime + (*E)->getMinDelay()); } } @@ -140,14 +154,14 @@ SchedPriorities::issuedReadyNodeAt(cycles_t curTime, //---------------------------------------------------------------------- inline int -SchedPriorities::chooseByRule1(vector<candIndex>& mcands) +SchedPriorities::chooseByRule1(std::vector<candIndex>& mcands) { return (mcands.size() == 1)? 0 // only one choice exists so take it : -1; // -1 indicates multiple choices } inline int -SchedPriorities::chooseByRule2(vector<candIndex>& mcands) +SchedPriorities::chooseByRule2(std::vector<candIndex>& mcands) { assert(mcands.size() >= 1 && "Should have at least one candidate here."); for (unsigned i=0, N = mcands.size(); i < N; i++) @@ -158,7 +172,7 @@ SchedPriorities::chooseByRule2(vector<candIndex>& mcands) } inline int -SchedPriorities::chooseByRule3(vector<candIndex>& mcands) +SchedPriorities::chooseByRule3(std::vector<candIndex>& mcands) { assert(mcands.size() >= 1 && "Should have at least one candidate here."); int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges(); @@ -224,7 +238,7 @@ SchedPriorities::getNextHighest(const SchedulingManager& S, void -SchedPriorities::findSetWithMaxDelay(vector<candIndex>& mcands, +SchedPriorities::findSetWithMaxDelay(std::vector<candIndex>& mcands, const SchedulingManager& S) { if (mcands.size() == 0 && nextToTry != candsAsHeap.end()) @@ -240,12 +254,12 @@ SchedPriorities::findSetWithMaxDelay(vector<candIndex>& mcands, if (SchedDebugLevel >= Sched_PrintSchedTrace) { - cout << " Cycle " << this->getTime() << ": " - << "Next highest delay = " << maxDelay << " : " + cerr << " Cycle " << (long)getTime() << ": " + << "Next highest delay = " << (long)maxDelay << " : " << mcands.size() << " Nodes with this delay: "; for (unsigned i=0; i < mcands.size(); i++) - cout << candsAsHeap.getNode(mcands[i])->getNodeId() << ", "; - cout << endl; + cerr << candsAsHeap.getNode(mcands[i])->getNodeId() << ", "; + cerr << "\n"; } } } @@ -257,10 +271,10 @@ SchedPriorities::instructionHasLastUse(MethodLiveVarInfo& methodLiveVarInfo, { const MachineInstr* minstr = graphNode->getMachineInstr(); - hash_map<const MachineInstr*, bool>::const_iterator + std::hash_map<const MachineInstr*, bool>::const_iterator ui = lastUseMap.find(minstr); if (ui != lastUseMap.end()) - return (*ui).second; + return ui->second; // else check if instruction is a last use and save it in the hash_map bool hasLastUse = false; diff --git a/lib/Target/SparcV9/InstrSched/SchedPriorities.h b/lib/Target/SparcV9/InstrSched/SchedPriorities.h index 81a2e6a053..a8b3e23397 100644 --- a/lib/Target/SparcV9/InstrSched/SchedPriorities.h +++ b/lib/Target/SparcV9/InstrSched/SchedPriorities.h @@ -26,6 +26,7 @@ #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" #include "llvm/Target/MachineSchedInfo.h" #include <list> +#include <ostream> class Method; class MachineInstr; @@ -36,22 +37,22 @@ struct NodeDelayPair { const SchedGraphNode* node; cycles_t delay; NodeDelayPair(const SchedGraphNode* n, cycles_t d) : node(n), delay(d) {} - inline bool operator< (const NodeDelayPair& np) { return delay < np.delay; } + inline bool operator<(const NodeDelayPair& np) { return delay < np.delay; } }; inline bool NDPLessThan(const NodeDelayPair* np1, const NodeDelayPair* np2) { - return (np1->delay < np2->delay); + return np1->delay < np2->delay; } -class NodeHeap: public list<NodeDelayPair*>, public NonCopyable { +class NodeHeap: public std::list<NodeDelayPair*>, public NonCopyable { public: - typedef list<NodeDelayPair*>::iterator iterator; - typedef list<NodeDelayPair*>::const_iterator const_iterator; + typedef std::list<NodeDelayPair*>::iterator iterator; + typedef std::list<NodeDelayPair*>::const_iterator const_iterator; public: - /*ctor*/ NodeHeap () : list<NodeDelayPair*>(), _size(0) {} + /*ctor*/ NodeHeap () : std::list<NodeDelayPair*>(), _size(0) {} /*dtor*/ ~NodeHeap () {} inline unsigned int size () const { return _size; } @@ -89,7 +90,7 @@ public: iterator I=begin(); for ( ; I != end() && getDelay(I) >= delay; ++I) ; - list<NodeDelayPair*>::insert(I, ndp); + std::list<NodeDelayPair*>::insert(I, ndp); } _size++; } @@ -131,22 +132,22 @@ private: cycles_t curTime; const SchedGraph* graph; MethodLiveVarInfo methodLiveVarInfo; - hash_map<const MachineInstr*, bool> lastUseMap; - vector<cycles_t> nodeDelayVec; - vector<cycles_t> earliestForNode; + std::hash_map<const MachineInstr*, bool> lastUseMap; + std::vector<cycles_t> nodeDelayVec; + std::vector<cycles_t> earliestForNode; cycles_t earliestReadyTime; NodeHeap candsAsHeap; // candidate nodes, ready to go - hash_set<const SchedGraphNode*> candsAsSet; // same entries as candsAsHeap, + std::hash_set<const SchedGraphNode*> candsAsSet;//same entries as candsAsHeap, // but as set for fast lookup - vector<candIndex> mcands; // holds pointers into cands + std::vector<candIndex> mcands; // holds pointers into cands candIndex nextToTry; // next cand after the last // one tried in this cycle - int chooseByRule1 (vector<candIndex>& mcands); - int chooseByRule2 (vector<candIndex>& mcands); - int chooseByRule3 (vector<candIndex>& mcands); + int chooseByRule1 (std::vector<candIndex>& mcands); + int chooseByRule2 (std::vector<candIndex>& mcands); + int chooseByRule3 (std::vector<candIndex>& mcands); - void findSetWithMaxDelay (vector<candIndex>& mcands, + void findSetWithMaxDelay (std::vector<candIndex>& mcands, const SchedulingManager& S); void computeDelays (const SchedGraph* graph); @@ -169,36 +170,15 @@ private: }; -inline void -SchedPriorities::insertReady(const SchedGraphNode* node) -{ - candsAsHeap.insert(node, nodeDelayVec[node->getNodeId()]); - candsAsSet.insert(node); - mcands.clear(); // ensure reset choices is called before any more choices - earliestReadyTime = min(earliestReadyTime, - earliestForNode[node->getNodeId()]); - - if (SchedDebugLevel >= Sched_PrintSchedTrace) - { - cout << " Cycle " << this->getTime() << ": " - << " Node " << node->getNodeId() << " is ready; " - << " Delay = " << this->getNodeDelayRef(node) << "; Instruction: " - << endl; - cout << " " << *node->getMachineInstr() << endl; - } -} - inline void SchedPriorities::updateTime(cycles_t c) { curTime = c; nextToTry = candsAsHeap.begin(); mcands.clear(); } -inline ostream& operator<< (ostream& os, const NodeDelayPair* nd) { +inline std::ostream &operator<<(std::ostream &os, const NodeDelayPair* nd) { return os << "Delay for node " << nd->node->getNodeId() - << " = " << nd->delay << endl; + << " = " << (long)nd->delay << "\n"; } -/***************************************************************************/ - #endif diff --git a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp index ce3e2c3a3f..20cbe8d71b 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp @@ -31,6 +31,9 @@ #include "llvm/BasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" #include "Support/STLExtras.h" +#include <iostream> +using std::cerr; +using std::vector; //------------------------------------------------------------------------ // class InstrTreeNode @@ -119,21 +122,21 @@ void InstructionNode::dumpNode(int indent) const { for (int i=0; i < indent; i++) - cout << " "; + cerr << " "; - cout << getInstruction()->getOpcodeName(); + cerr << getInstruction()->getOpcodeName(); const vector<MachineInstr*> &mvec = getInstruction()->getMachineInstrVec(); if (mvec.size() > 0) - cout << "\tMachine Instructions: "; + cerr << "\tMachine Instructions: "; for (unsigned int i=0; i < mvec.size(); i++) { mvec[i]->dump(0); if (i < mvec.size() - 1) - cout << "; "; + cerr << "; "; } - cout << endl; + cerr << "\n"; } @@ -141,9 +144,9 @@ void VRegListNode::dumpNode(int indent) const { for (int i=0; i < indent; i++) - cout << " "; + cerr << " "; - cout << "List" << endl; + cerr << "List" << "\n"; } @@ -151,29 +154,29 @@ void VRegNode::dumpNode(int indent) const { for (int i=0; i < indent; i++) - cout << " "; + cerr << " "; - cout << "VReg " << getValue() << "\t(type " - << (int) getValue()->getValueType() << ")" << endl; + cerr << "VReg " << getValue() << "\t(type " + << (int) getValue()->getValueType() << ")" << "\n"; } void ConstantNode::dumpNode(int indent) const { for (int i=0; i < indent; i++) - cout << " "; + cerr << " "; - cout << "Constant " << getValue() << "\t(type " - << (int) getValue()->getValueType() << ")" << endl; + cerr << "Constant " << getValue() << "\t(type " + << (int) getValue()->getValueType() << ")" << "\n"; } void LabelNode::dumpNode(int indent) const { for (int i=0; i < indent; i++) - cout << " "; + cerr << " "; - cout << "Label " << getValue() << endl; + cerr << "Label " << getValue() << "\n"; } //------------------------------------------------------------------------ @@ -190,7 +193,7 @@ InstrForest::InstrForest(Method *M) InstrForest::~InstrForest() { - for (hash_map<const Instruction*, InstructionNode*>:: iterator I = begin(); + for (std::hash_map<const Instruction*,InstructionNode*>::iterator I = begin(); I != end(); ++I) delete (*I).second; } @@ -198,7 +201,7 @@ InstrForest::~InstrForest() void InstrForest::dump() const { - for (hash_set<InstructionNode*>::const_iterator I = treeRoots.begin(); + for (std::hash_set<InstructionNode*>::const_iterator I = treeRoots.begin(); I != treeRoots.end(); ++I) (*I)->dump(/*dumpChildren*/ 1, /*indent*/ 0); } diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp index b959c90ca3..ab489c507e 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp @@ -23,8 +23,8 @@ #include "llvm/iPHINode.h" #include "llvm/Target/MachineRegInfo.h" #include "Support/CommandLine.h" -#include <string.h> - +#include <iostream> +using std::cerr; //******************** Internal Data Declarations ************************/ @@ -84,17 +84,17 @@ SelectInstructionsForMethod(Method* method, TargetMachine &target) if (SelectDebugLevel >= Select_DebugInstTrees) { - cout << "\n\n*** Instruction trees for method " + cerr << "\n\n*** Instruction trees for method " << (method->hasName()? method->getName() : "") - << endl << endl; + << "\n\n"; instrForest.dump(); } // // Invoke BURG instruction selection for each tree // - const hash_set<InstructionNode*> &treeRoots = instrForest.getRootSet(); - for (hash_set<InstructionNode*>::const_iterator + const std::hash_set<InstructionNode*> &treeRoots = instrForest.getRootSet(); + for (std::hash_set<InstructionNode*>::const_iterator treeRootIter = treeRoots.begin(); treeRootIter != treeRoots.end(); ++treeRootIter) { @@ -138,8 +138,7 @@ SelectInstructionsForMethod(Method* method, TargetMachine &target) if (SelectDebugLevel >= Select_PrintMachineCode) { - cout << endl - << "*** Machine instructions after INSTRUCTION SELECTION" << endl; + cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n"; MachineCodeForMethod::get(method).dump(); } @@ -210,7 +209,7 @@ void InsertCode4AllPhisInMeth(Method *method, TargetMachine &target) { // insert the copy instruction to the predecessor BB - vector<MachineInstr*> CopyInstVec; + std::vector<MachineInstr*> CopyInstVec; MachineInstr *CpMI = target.getRegInfo().cpValue2Value(PN->getIncomingValue(i), PN); @@ -250,25 +249,18 @@ void InsertCode4AllPhisInMeth(Method *method, TargetMachine &target) { PHINode *PN = (PHINode *) (*IIt); - Value *PhiCpRes = new Value(PN->getType(), PN->getValueType()); - - string *Name = new string("PhiCp:"); - (*Name) += (int) PhiCpRes; - PhiCpRes->setName( *Name ); - + Value *PhiCpRes = new Value(PN->getType(), PN->getValueType(),"PhiCp:"); // for each incoming value of the phi, insert phi elimination // for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) { // insert the copy instruction to the predecessor BB - MachineInstr *CpMI = target.getRegInfo().cpValue2Value(PN->getIncomingValue(i), PhiCpRes); InsertPhiElimInst(PN->getIncomingBlock(i), CpMI); - } @@ -279,8 +271,6 @@ void InsertCode4AllPhisInMeth(Method *method, TargetMachine &target) { MachineCodeForBasicBlock& bbMvec = BB->getMachineInstrVec(); bbMvec.insert( bbMvec.begin(), CpMI2); - - } else break; // since PHI nodes can only be at the top @@ -338,7 +328,7 @@ PostprocessMachineCodeForTree(InstructionNode* instrNode, MachineCodeForVMInstr& mvec = vmInstr->getMachineInstrVec(); for (int i = (int) mvec.size()-1; i >= 0; i--) { - vector<MachineInstr*> loadConstVec = + std::vector<MachineInstr*> loadConstVec = FixConstantOperandsForInstr(vmInstr, mvec[i], target); if (loadConstVec.size() > 0) @@ -372,7 +362,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt, if (ruleForNode == 0) { - cerr << "Could not match instruction tree for instr selection" << endl; + cerr << "Could not match instruction tree for instr selection\n"; assert(0); return true; } diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp index 30d9c7eb78..34dd83b49e 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp @@ -22,7 +22,7 @@ #include "llvm/Instruction.h" #include "llvm/Type.h" #include "llvm/iMemory.h" - +using std::vector; //*************************** Local Functions ******************************/ diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp index d7e036b256..0ecf96cf13 100644 --- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp +++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp @@ -1,8 +1,13 @@ #include "llvm/Analysis/LiveVar/BBLiveVar.h" #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" #include "llvm/CodeGen/MachineInstr.h" + +/// BROKEN: Should not include sparc stuff directly into here #include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn +using std::cerr; +using std::endl; +using std::pair; //----------------------------------------------------------------------------- // Constructor @@ -39,7 +44,7 @@ void BBLiveVar::calcDefUseSets() if( DEBUG_LV > 1) { // debug msg cerr << " *Iterating over machine instr "; MInst->dump(); - cerr << endl; + cerr << "\n"; } // iterate over MI operands to find defs @@ -85,9 +90,9 @@ void BBLiveVar::calcDefUseSets() if( DEBUG_LV > 1) { // debug msg of level 2 cerr << " - phi operand "; printValue( ArgVal ); - cerr << " came from BB "; + cerr << " came from BB "; printValue( PhiArgMap[ ArgVal ]); - cerr<<endl; + cerr << "\n"; } } // if( IsPhi ) @@ -123,7 +128,7 @@ void BBLiveVar::addDef(const Value *Op) InSetChanged = true; if( DEBUG_LV > 1) { - cerr << " +Def: "; printValue( Op ); cerr << endl; + cerr << " +Def: "; printValue( Op ); cerr << "\n"; } } diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.h b/lib/Target/SparcV9/LiveVar/BBLiveVar.h index 6d7d4eb533..9ce56a88f6 100644 --- a/lib/Target/SparcV9/LiveVar/BBLiveVar.h +++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.h @@ -28,7 +28,7 @@ class BBLiveVar // map that contains phi args->BB they came // set by calcDefUseSets & used by setPropagate - hash_map<const Value *, const BasicBlock *, hashFuncValue> PhiArgMap; + std::hash_map<const Value *, const BasicBlock *> PhiArgMap; // method to propogate an InSet to OutSet of a predecessor bool setPropagate( LiveVarSet *const OutSetOfPred, diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp index 636359d1d0..5de35ff1be 100644 --- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp @@ -12,15 +12,15 @@ #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "Support/PostOrderIterator.h" - +#include <iostream> +using std::cout; +using std::endl; //************************** Constructor/Destructor *************************** -MethodLiveVarInfo::MethodLiveVarInfo(const Method *const M) : Meth(M), - BB2BBLVMap() -{ - assert(! M->isExternal() ); // cannot be a prototype decleration +MethodLiveVarInfo::MethodLiveVarInfo(const Method *const M) : Meth(M) { + assert(!M->isExternal() && "Cannot be a prototype declaration"); HasAnalyzed = false; // still we haven't called analyze() } @@ -55,8 +55,6 @@ MethodLiveVarInfo:: ~MethodLiveVarInfo() if( (*MI).first ) // delete all LiveVarSets in MInst2LVSetBI delete (*MI).second; } - - } diff --git a/lib/Target/SparcV9/LiveVar/ValueSet.cpp b/lib/Target/SparcV9/LiveVar/ValueSet.cpp index 6806d1c563..d176d9e53c 100644 --- a/lib/Target/SparcV9/LiveVar/ValueSet.cpp +++ b/lib/Target/SparcV9/LiveVar/ValueSet.cpp @@ -1,11 +1,14 @@ #include "llvm/Analysis/LiveVar/ValueSet.h" #include "llvm/ConstantVals.h" - +#include <iostream> +using std::cerr; +using std::endl; +using std::pair; +using std::hash_set; void printValue( const Value *const v) // func to print a Value { - if (v->hasName()) cerr << v << "(" << ((*v).getName()) << ") "; else if (Constant *C = dyn_cast<Constant>(v)) @@ -16,17 +19,13 @@ void printValue( const Value *const v) // func to print a Value //---------------- Method implementations -------------------------- - - -ValueSet:: ValueSet() : hash_set<const Value *, hashFuncValue> () { } - // for performing two set unions bool ValueSet::setUnion( const ValueSet *const set1) { const_iterator set1it; pair<iterator, bool> result; bool changed = false; - for( set1it = set1->begin() ; set1it != set1->end(); set1it++) { + for( set1it = set1->begin() ; set1it != set1->end(); ++set1it) { // for all all elements in set1 result = insert( *set1it ); // insert to this set if( result.second == true) changed = true; @@ -41,7 +40,7 @@ void ValueSet::setDifference( const ValueSet *const set1, const ValueSet *const set2) { const_iterator set1it, set2it; - for( set1it = set1->begin() ; set1it != set1->end(); set1it++) { + for( set1it = set1->begin() ; set1it != set1->end(); ++set1it) { // for all elements in set1 iterator set2it = set2->find( *set1it ); // find wether the elem is in set2 if( set2it == set2->end() ) // if the element is not in set2 @@ -53,7 +52,7 @@ void ValueSet::setDifference( const ValueSet *const set1, // for performing set subtraction void ValueSet::setSubtract( const ValueSet *const set1) { const_iterator set1it; - for( set1it = set1->begin() ; set1it != set1->end(); set1it++) + for( set1it = set1->begin() ; set1it != set1->end(); ++set1it) // for all elements in set1 erase( *set1it ); // erase that element from this set } @@ -62,7 +61,5 @@ void ValueSet::setSubtract( const ValueSet *const set1) { void ValueSet::printSet() const { // for printing a live variable set - const_iterator it; - for( it = begin() ; it != end(); it++) - printValue( *it ); + for_each(begin(), end(), printValue); } diff --git a/lib/Target/SparcV9/RegAlloc/IGNode.cpp b/lib/Target/SparcV9/RegAlloc/IGNode.cpp index 4e66d9a762..a225742052 100644 --- a/lib/Target/SparcV9/RegAlloc/IGNode.cpp +++ b/lib/Target/SparcV9/RegAlloc/IGNode.cpp @@ -1,12 +1,13 @@ #include "llvm/CodeGen/IGNode.h" - +#include <algorithm> +#include <iostream> +using std::cerr; //----------------------------------------------------------------------------- // Constructor //----------------------------------------------------------------------------- -IGNode::IGNode(LiveRange *const PLR, unsigned int Ind): Index(Ind), - AdjList(), - ParentLR(PLR) +IGNode::IGNode(LiveRange *const PLR, unsigned int Ind) : Index(Ind), + ParentLR(PLR) { OnStack = false; CurDegree = -1 ; @@ -23,11 +24,12 @@ void IGNode::pushOnStack() int neighs = AdjList.size(); if( neighs < 0) { - cout << "\nAdj List size = " << neighs; + cerr << "\nAdj List size = " << neighs; assert(0 && "Invalid adj list size"); } - for(int i=0; i < neighs; i++) (AdjList[i])->decCurDegree(); + for(int i=0; i < neighs; i++) + AdjList[i]->decCurDegree(); } //----------------------------------------------------------------------------- @@ -35,11 +37,9 @@ void IGNode::pushOnStack() // two IGNodes together. //----------------------------------------------------------------------------- void IGNode::delAdjIGNode(const IGNode *const Node) { - vector <IGNode *>::iterator It = AdjList.begin(); - - // find Node - for( ; It != AdjList.end() && (*It != Node); It++ ) ; + std::vector<IGNode *>::iterator It = + find(AdjList.begin(), AdjList.end(), Node); assert( It != AdjList.end() ); // the node must be there - - AdjList.erase( It ); + + AdjList.erase(It); } diff --git a/lib/Target/SparcV9/RegAlloc/IGNode.h b/lib/Target/SparcV9/RegAlloc/IGNode.h index 0f4cf9c82a..b89aea32b1 100644 --- a/lib/Target/SparcV9/RegAlloc/IGNode.h +++ b/lib/Target/SparcV9/RegAlloc/IGNode.h @@ -29,8 +29,6 @@ #include "llvm/CodeGen/RegAllocCommon.h" #include "llvm/CodeGen/LiveRange.h" - - //---------------------------------------------------------------------------- // Class IGNode // @@ -39,13 +37,11 @@ class IGNode { - private: - const int Index; // index within IGNodeList bool OnStack; // this has been pushed on to stack for coloring - vector<IGNode *> AdjList; // adjacency list for this live range + std::vector<IGNode *> AdjList; // adjacency list for this live range int CurDegree; // @@ -54,7 +50,6 @@ class IGNode // Decremented when a neighbor is pushed on to the stack. // After that, never incremented/set again nor used. - LiveRange *const ParentLR; // parent LR (cannot be a const) @@ -152,10 +147,4 @@ class IGNode }; - - - - - - #endif diff --git a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp index e18c9a7a34..0de7275acf 100644 --- a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp +++ b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp @@ -1,4 +1,7 @@ #include "llvm/CodeGen/InterferenceGraph.h" +#include "Support/STLExtras.h" +#include <iostream> +using std::cerr; //----------------------------------------------------------------------------- // Constructor: Records the RegClass and initalizes IGNodeList. @@ -11,7 +14,7 @@ InterferenceGraph::InterferenceGraph(RegClass *const RC) : RegCl(RC), IG = NULL; Size = 0; if( DEBUG_RA) { - cout << "Interference graph created!" << endl; + cerr << "Interference graph created!\n"; } } @@ -22,19 +25,12 @@ InterferenceGraph::InterferenceGraph(RegClass *const RC) : RegCl(RC), InterferenceGraph:: ~InterferenceGraph() { // delete the matrix - // - if( IG ) - delete []IG; + for(unsigned int r=0; r < IGNodeList.size(); ++r) + delete[] IG[r]; + delete[] IG; // delete all IGNodes in the IGNodeList - // - vector<IGNode *>::const_iterator IGIt = IGNodeList.begin(); - for(unsigned i=0; i < IGNodeList.size() ; ++i) { - - const IGNode *const Node = IGNodeList[i]; - if( Node ) delete Node; - } - + for_each(IGNodeList.begin(), IGNodeList.end(), deleter<IGNode>); } @@ -46,13 +42,13 @@ InterferenceGraph:: ~InterferenceGraph() { void InterferenceGraph::createGraph() { Size = IGNodeList.size(); - IG = (char **) new char *[Size]; + IG = new char*[Size]; for( unsigned int r=0; r < Size; ++r) IG[r] = new char[Size]; // init IG matrix for(unsigned int i=0; i < Size; i++) - for( unsigned int j=0; j < Size ; j++) + for(unsigned int j=0; j < Size; j++) IG[i][j] = 0; } @@ -61,9 +57,7 @@ void InterferenceGraph::createGraph() //----------------------------------------------------------------------------- void InterferenceGraph::addLRToIG(LiveRange *const LR) { - IGNode *Node = new IGNode(LR, IGNodeList.size() ); - IGNodeList.push_back( Node ); - + IGNodeList.push_back(new IGNode(LR, IGNodeList.size())); } @@ -92,12 +86,11 @@ void InterferenceGraph::setInterference(const LiveRange *const LR1, char *val; if( DEBUG_RA > 1) - cout << "setting intf for: [" << row << "][" << col << "]" << endl; + cerr << "setting intf for: [" << row << "][" << col << "]\n"; ( row > col) ? val = &IG[row][col]: val = &IG[col][row]; if( ! (*val) ) { // if this interf is not previously set - *val = 1; // add edges between nodes IGNode1->addAdjIGNode( IGNode2 ); IGNode2->addAdjIGNode( IGNode1 ); @@ -123,7 +116,10 @@ unsigned InterferenceGraph::getInterference(const LiveRange *const LR1, const unsigned int col = LR2->getUserIGNode()->getIndex(); char ret; - ( row > col) ? (ret = IG[row][col]) : (ret = IG[col][row]) ; + if (row > col) + ret = IG[row][col]; + else + ret = IG[col][row]; return ret; } @@ -148,9 +144,9 @@ void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *const LR1, assertIGNode( SrcNode ); if( DEBUG_RA > 1) { - cout << "Merging LRs: \""; LR1->printSet(); - cout << "\" and \""; LR2->printSet(); - cout << "\"" << endl; + cerr << "Merging LRs: \""; LR1->printSet(); + cerr << "\" and \""; LR2->printSet(); + cerr << "\"\n"; } unsigned SrcDegree = SrcNode->getNumOfNeighbors(); @@ -217,17 +213,16 @@ void InterferenceGraph::printIG() const for(unsigned int i=0; i < Size; i++) { const IGNode *const Node = IGNodeList[i]; - if( ! Node ) - continue; // skip empty rows - - cout << " [" << i << "] "; + if(Node) { + cerr << " [" << i << "] "; - for( unsigned int j=0; j < Size; j++) { - if( j >= i) break; - if( IG[i][j] ) cout << "(" << i << "," << j << ") "; + for( unsigned int j=0; j < i; j++) { + if(IG[i][j]) + cerr << "(" << i << "," << j << ") "; } - cout << endl; + cerr << "\n"; } + } } //---------------------------------------------------------------------------- @@ -235,21 +230,14 @@ void InterferenceGraph::printIG() const //---------------------------------------------------------------------------- void InterferenceGraph::printIGNodeList() const { - vector<IGNode *>::const_iterator IGIt = IGNodeList.begin(); // hash map iter - for(unsigned i=0; i < IGNodeList.size() ; ++i) { - const IGNode *const Node = IGNodeList[i]; - if( ! Node ) - continue; - - cout << " [" << Node->getIndex() << "] "; - (Node->getParentLR())->printSet(); - //int Deg = Node->getCurDegree(); - cout << "\t <# of Neighs: " << Node->getNumOfNeighbors() << ">" << endl; - + if (Node) { + cerr << " [" << Node->getIndex() << "] "; + Node->getParentLR()->printSet(); + //int Deg = Node->getCurDegree(); + cerr << "\t <# of Neighs: " << Node->getNumOfNeighbors() << ">\n"; + } } } - - diff --git a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h index 99dea8fbe0..408bee4558 100644 --- a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h +++ b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h @@ -1,4 +1,4 @@ -/* Title: InterferenceGraph.h +/* Title: InterferenceGraph.h -*- C++ -*- Author: Ruchira Sasanka Date: July 20, 01 Purpose: Interference Graph used for register coloring. @@ -24,7 +24,7 @@ #include "llvm/CodeGen/IGNode.h" -typedef vector <IGNode *> IGNodeListType; +typedef std::vector <IGNode *> IGNodeListType; class InterferenceGraph @@ -47,6 +47,8 @@ class InterferenceGraph // to create it after adding all IGNodes to the IGNodeList InterferenceGraph(RegClass *const RC); + ~InterferenceGraph(); + void createGraph(); void addLRToIG(LiveRange *const LR); @@ -65,12 +67,6 @@ class InterferenceGraph void printIG() const; void printIGNodeList() const; - - ~InterferenceGraph(); - - }; - #endif - diff --git a/lib/Target/SparcV9/RegAlloc/LiveRange.h b/lib/Target/SparcV9/RegAlloc/LiveRange.h index 778e070046..8034751da9 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRange.h +++ b/lib/Target/SparcV9/RegAlloc/LiveRange.h @@ -1,4 +1,4 @@ -/* Title: LiveRange.h +/* Title: LiveRange.h -*- C++ -*- Author: Ruchira Sasanka Date: July 25, 01 Purpose: To keep info about a live range. @@ -13,6 +13,7 @@ #include "llvm/Analysis/LiveVar/ValueSet.h" #include "llvm/Type.h" +#include <iostream> class RegClass; class IGNode; @@ -176,7 +177,7 @@ class LiveRange : public ValueSet if(SuggestedColor == -1 ) SuggestedColor = Col; else if (DEBUG_RA) - cerr << "Already has a suggested color " << Col << endl; + std::cerr << "Already has a suggested color " << Col << "\n"; } inline unsigned getSuggestedColor() const { diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp index 7fb688f55e..b66e6ef308 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp @@ -1,15 +1,15 @@ #include "llvm/CodeGen/LiveRangeInfo.h" +#include <iostream> +using std::cerr; //--------------------------------------------------------------------------- // Constructor //--------------------------------------------------------------------------- LiveRangeInfo::LiveRangeInfo(const Method *const M, const TargetMachine& tm, - vector<RegClass *> &RCL) - : Meth(M), LiveRangeMap(), - TM(tm), RegClassList(RCL), - MRI( tm.getRegInfo()), - CallRetInstrList() + std::vector<RegClass *> &RCL) + : Meth(M), LiveRangeMap(), TM(tm), + RegClassList(RCL), MRI(tm.getRegInfo()) { } @@ -17,33 +17,25 @@ LiveRangeInfo::LiveRangeInfo(const Method *const M, // Destructor: Deletes all LiveRanges in the LiveRangeMap //--------------------------------------------------------------------------- LiveRangeInfo::~LiveRangeInfo() { - LiveRangeMapType::iterator MI = LiveRangeMap.begin(); for( ; MI != LiveRangeMap.end() ; ++MI) { - if( (*MI).first ) { - - LiveRange *LR = (*MI).second; - - if( LR ) { - - // we need to be careful in deleting LiveRanges in LiveRangeMap - // since two/more Values in the live range map can point to the same - // live range. We have to make the other entries NULL when we delete - // a live range. - - LiveRange::iterator LI = LR->begin(); - - for( ; LI != LR->end() ; ++LI) { - LiveRangeMap[*LI] = NULL; - } + if (MI->first && MI->second) { + LiveRange *LR = MI->second; - delete LR; + // we need to be careful in deleting LiveRanges in LiveRangeMap + // since two/more Values in the live range map can point to the same + // live range. We have to make the other entries NULL when we delete + // a live range. - } + LiveRange::iterator LI = LR->begin(); + + for( ; LI != LR->end() ; ++LI) + LiveRangeMap[*LI] = 0; + + delete LR; } } - } @@ -82,7 +74,7 @@ void LiveRangeInfo::unionAndUpdateLRs(LiveRange *const L1, LiveRange *L2) L1->addSpillCost( L2->getSpillCost() ); // add the spill costs - delete ( L2 ); // delete L2 as it is no longer needed + delete L2; // delete L2 as it is no longer needed } @@ -96,7 +88,7 @@ void LiveRangeInfo::constructLiveRanges() { if( DEBUG_RA) - cout << "Consturcting Live Ranges ..." << endl; + cerr << "Consturcting Live Ranges ...\n"; // first find the live ranges for all incoming args of the method since // those LRs start from the start of the method @@ -108,14 +100,13 @@ void LiveRangeInfo::constructLiveRanges() for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument - LiveRange * ArgRange = new LiveRange(); // creates a new LR and const Value *const Val = (const Value *) *ArgIt; assert( Val); - ArgRange->add( Val ); // add the arg (def) to it - LiveRangeMap[ Val ] = ArgRange; + ArgRange->add(Val); // add the arg (def) to it + LiveRangeMap[Val] = ArgRange; // create a temp machine op to find the register class of value //const MachineOperand Op(MachineOperand::MO_VirtualRegister); @@ -125,8 +116,8 @@ void LiveRangeInfo::constructLiveRanges() if( DEBUG_RA > 1) { - cout << " adding LiveRange for argument "; - printValue( (const Value *) *ArgIt); cout << endl; + cerr << " adding LiveRange for argument "; + printValue((const Value *) *ArgIt); cerr << "\n"; } } @@ -140,7 +131,6 @@ void LiveRangeInfo::constructLiveRanges() Method::const_iterator BBI = Meth->begin(); // random iterator for BBs - for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order // Now find all LRs for machine the instructions. A new LR will be created @@ -150,8 +140,7 @@ void LiveRangeInfo::constructLiveRanges() // get the iterator for machine instructions const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec(); - MachineCodeForBasicBlock::const_iterator - MInstIterator = MIVec.begin(); + MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin(); // iterate over all the machine instructions in BB for( ; MInstIterator != MIVec.end(); MInstIterator++) { @@ -161,53 +150,46 @@ void LiveRangeInfo::constructLiveRanges() // Now if the machine instruction is a call/return instruction, // add it to CallRetInstrList for processing its implicit operands - if( (TM.getInstrInfo()).isReturn( MInst->getOpCode()) || - (TM.getInstrInfo()).isCall( MInst->getOpCode()) ) + if(TM.getInstrInfo().isReturn(MInst->getOpCode()) || + TM.getInstrInfo().isCall(MInst->getOpCode())) CallRetInstrList.push_back( MInst ); // iterate over MI operands to find defs - for( MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done(); ++OpI) { - - if( DEBUG_RA) { + for (MachineInstr::val_const_op_iterator OpI(MInst); !OpI.done(); ++OpI) { + if(DEBUG_RA) { MachineOperand::MachineOperandType OpTyp = OpI.getMachineOperand().getOperandType(); - if ( OpTyp == MachineOperand::MO_CCRegister) { - cout << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:"; + if (OpTyp == MachineOperand::MO_CCRegister) { + cerr << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:"; printValue( OpI.getMachineOperand().getVRegValue() ); - cout << endl; + cerr << "\n"; } } // create a new LR iff this operand is a def if( OpI.isDef() ) { - const Value *const Def = *OpI; - // Only instruction values are accepted for live ranges here - if( Def->getValueType() != Value::InstructionVal ) { - cout << "\n**%%Error: Def is not an instruction val. Def="; - printValue( Def ); cout << endl; + cerr << "\n**%%Error: Def is not an instruction val. Def="; + printValue( Def ); cerr << "\n"; continue; } - LiveRange *DefRange = LiveRangeMap[Def]; // see LR already there (because of multiple defs) - if( !DefRange) { // if it is not in LiveRangeMap - DefRange = new LiveRange(); // creates a new live range and DefRange->add( Def ); // add the instruction (def) to it LiveRangeMap[ Def ] = DefRange; // update the map if( DEBUG_RA > 1) { - cout << " creating a LR for def: "; - printValue(Def); cout << endl; + cerr << " creating a LR for def: "; + printValue(Def); cerr << "\n"; } // set the register class of the new live range @@ -221,7 +203,7 @@ void LiveRangeInfo::constructLiveRanges() if(isCC && DEBUG_RA) { - cout << "\a**created a LR for a CC reg:"; + cerr << "\a**created a LR for a CC reg:"; printValue( OpI.getMachineOperand().getVRegValue() ); } @@ -235,8 +217,8 @@ void LiveRangeInfo::constructLiveRanges() LiveRangeMap[ Def ] = DefRange; if( DEBUG_RA > 1) { - cout << " added to an existing LR for def: "; - printValue( Def ); cout << endl; + cerr << " added to an existing LR for def: "; + printValue( Def ); cerr << "\n"; } } @@ -256,7 +238,7 @@ void LiveRangeInfo::constructLiveRanges() suggestRegs4CallRets(); if( DEBUG_RA) - cout << "Initial Live Ranges constructed!" << endl; + cerr << "Initial Live Ranges constructed!\n"; } @@ -312,11 +294,8 @@ void LiveRangeInfo::suggestRegs4CallRets() //--------------------------------------------------------------------------- void LiveRangeInfo::coalesceLRs() { - - - if( DEBUG_RA) - cout << endl << "Coalscing LRs ..." << endl; + cerr << "\nCoalscing LRs ...\n"; Method::const_iterator BBI = Meth->begin(); // random iterator for BBs @@ -324,8 +303,7 @@ void LiveRangeInfo::coalesceLRs() // get the iterator for machine instructions const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec(); - MachineCodeForBasicBlock::const_iterator - MInstIterator = MIVec.begin(); + MachineCodeForBasicBlock::const_iterator MInstIterator = MIVec.begin(); // iterate over all the machine instructions in BB for( ; MInstIterator != MIVec.end(); ++MInstIterator) { @@ -333,9 +311,9 @@ void LiveRangeInfo::coalesceLRs() const MachineInstr * MInst = *MInstIterator; if( DEBUG_RA > 1) { - cout << " *Iterating over machine instr "; + cerr << " *Iterating over machine instr "; MInst->dump(); - cout << endl; + cerr << "\n"; } @@ -357,8 +335,8 @@ void LiveRangeInfo::coalesceLRs() //don't warn about labels if (!((*UseI)->getType())->isLabelType() && DEBUG_RA) { - cout<<" !! Warning: No LR for use "; printValue(*UseI); - cout << endl; + cerr<<" !! Warning: No LR for use "; printValue(*UseI); + cerr << "\n"; } continue; // ignore and continue } @@ -407,7 +385,7 @@ void LiveRangeInfo::coalesceLRs() } // for all BBs if( DEBUG_RA) - cout << endl << "Coalscing Done!" << endl; + cerr << "\nCoalscing Done!\n"; } @@ -421,11 +399,11 @@ void LiveRangeInfo::coalesceLRs() void LiveRangeInfo::printLiveRanges() { LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator - cout << endl << "Printing Live Ranges from Hash Map:" << endl; - for( ; HMI != LiveRangeMap.end() ; HMI ++ ) { - if( (*HMI).first && (*HMI).second ) { - cout <<" "; printValue((*HMI).first); cout << "\t: "; - ((*HMI).second)->printSet(); cout << endl; + cerr << "\nPrinting Live Ranges from Hash Map:\n"; + for( ; HMI != LiveRangeMap.end() ; ++HMI) { + if( HMI->first && HMI->second ) { + cerr <<" "; printValue((*HMI).first); cerr << "\t: "; + HMI->second->printSet(); cerr << "\n"; } } } diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h index 1eee1aea5e..9e7ef06fe2 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h @@ -1,4 +1,4 @@ -/* Title: LiveRangeInfo.h +/* Title: LiveRangeInfo.h -*- C++ -*- Author: Ruchira Sasanka Date: Jun 30, 01 Purpose: @@ -34,8 +34,8 @@ #include "llvm/CodeGen/RegClass.h" -typedef hash_map <const Value *, LiveRange *, hashFuncValue> LiveRangeMapType; -typedef vector <const MachineInstr *> CallRetInstrListType; +typedef std::hash_map<const Value*, LiveRange*> LiveRangeMapType; +typedef std::vector<const MachineInstr*> CallRetInstrListType; @@ -59,7 +59,7 @@ private: const TargetMachine& TM; // target machine description - vector<RegClass *> & RegClassList;// a vector containing register classess + std::vector<RegClass *> & RegClassList;// vector containing register classess const MachineRegInfo& MRI; // machine reg info @@ -82,7 +82,7 @@ public: LiveRangeInfo(const Method *const M, const TargetMachine& tm, - vector<RegClass *> & RCList); + std::vector<RegClass *> & RCList); // Destructor to destroy all LiveRanges in the LiveRange Map diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 7d6fbb7cc9..e2d455bad9 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -14,7 +14,9 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineFrameInfo.h" +#include <iostream> #include <math.h> +using std::cerr; // ***TODO: There are several places we add instructions. Validate the order @@ -35,18 +37,16 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags, PhyRegAlloc::PhyRegAlloc(Method *M, const TargetMachine& tm, MethodLiveVarInfo *const Lvi) - : RegClassList(), - TM(tm), - Meth(M), + : TM(tm), Meth(M), mcInfo(MachineCodeForMethod::get(M)), LVI(Lvi), LRI(M, tm, RegClassList), MRI( tm.getRegInfo() ), NumOfRegClasses(MRI.getNumOfRegClasses()), - AddedInstrMap(), LoopDepthCalc(M), ResColList() { + LoopDepthCalc(M) { // create each RegisterClass and put in RegClassList // - for( unsigned int rc=0; rc < NumOfRegClasses; rc++) + for(unsigned int rc=0; rc < NumOfRegClasses; rc++) RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), &ResColList) ); } @@ -69,7 +69,7 @@ PhyRegAlloc::~PhyRegAlloc() { //---------------------------------------------------------------------------- void PhyRegAlloc::createIGNodeListsAndIGs() { - if(DEBUG_RA ) cout << "Creating LR lists ..." << endl; + if(DEBUG_RA ) cerr << "Creating LR lists ...\n"; // hash map iterator LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); @@ -85,8 +85,8 @@ void PhyRegAlloc::createIGNodeListsAndIGs() if( !L) { if( DEBUG_RA) { - cout << "\n*?!?Warning: Null liver range found for: "; - printValue( (*HMI).first) ; cout << endl; + cerr << "\n*?!?Warning: Null liver range found for: "; + printValue(HMI->first); cerr << "\n"; } continue; } @@ -108,7 +108,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() RegClassList[ rc ]->createInterferenceGraph(); if( DEBUG_RA) - cout << "LRLists Created!" << endl; + cerr << "LRLists Created!\n"; } @@ -140,8 +140,8 @@ void PhyRegAlloc::addInterference(const Value *const Def, for( ; LIt != LVSet->end(); ++LIt) { if( DEBUG_RA > 1) { - cout << "< Def="; printValue(Def); - cout << ", Lvar="; printValue( *LIt); cout << "> "; + cerr << "< Def="; printValue(Def); + cerr << ", Lvar="; printValue( *LIt); cerr << "> "; } // get the live range corresponding to live var @@ -166,8 +166,8 @@ void PhyRegAlloc::addInterference(const Value *const Def, else if(DEBUG_RA > 1) { // we will not have LRs for values not explicitly allocated in the // instruction stream (e.g., constants) - cout << " warning: no live range for " ; - printValue( *LIt); cout << endl; } + cerr << " warning: no live range for " ; + printValue(*LIt); cerr << "\n"; } } @@ -203,7 +203,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst, } if( DEBUG_RA) - cout << "\n For call inst: " << *MInst; + cerr << "\n For call inst: " << *MInst; LiveVarSet::const_iterator LIt = LVSetAft->begin(); @@ -216,7 +216,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst, LiveRange *const LR = LRI.getLiveRangeForValue(*LIt ); if( LR && DEBUG_RA) { - cout << "\n\tLR Aft Call: "; + cerr << "\n\tLR Aft Call: "; LR->printSet(); } @@ -227,7 +227,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst, if( LR && (LR != RetValLR) ) { LR->setCallInterference(); if( DEBUG_RA) { - cout << "\n ++Added call interf for LR: " ; + cerr << "\n ++Added call interf for LR: " ; LR->printSet(); } } @@ -247,7 +247,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst, void PhyRegAlloc::buildInterferenceGraphs() { - if(DEBUG_RA) cout << "Creating interference graphs ..." << endl; + if(DEBUG_RA) cerr << "Creating interference graphs ...\n"; unsigned BBLoopDepthCost; Method::const_iterator BBI = Meth->begin(); // random iterator for BBs @@ -333,7 +333,7 @@ void PhyRegAlloc::buildInterferenceGraphs() addInterferencesForArgs(); if( DEBUG_RA) - cout << "Interference graphs calculted!" << endl; + cerr << "Interference graphs calculted!\n"; } @@ -411,8 +411,8 @@ void PhyRegAlloc::addInterferencesForArgs() addInterference( *ArgIt, InSet, false ); // add interferences between // args and LVars at start if( DEBUG_RA > 1) { - cout << " - %% adding interference for argument "; - printValue( (const Value *) *ArgIt); cout << endl; + cerr << " - %% adding interference for argument "; + printValue((const Value *)*ArgIt); cerr << "\n"; } } } @@ -510,7 +510,7 @@ void PhyRegAlloc::updateMachineCode() // delete this condition checking later (must assert if Val is null) if( !Val) { if (DEBUG_RA) - cout << "Warning: NULL Value found for operand" << endl; + cerr << "Warning: NULL Value found for operand\n"; continue; } assert( Val && "Value is NULL"); @@ -522,9 +522,9 @@ void PhyRegAlloc::updateMachineCode() // nothing to worry if it's a const or a label if (DEBUG_RA) { - cout << "*NO LR for operand : " << Op ; - cout << " [reg:" << Op.getAllocatedRegNum() << "]"; - cout << " in inst:\t" << *MInst << endl; + cerr << "*NO LR for operand : " << Op ; + cerr << " [reg:" << Op.getAllocatedRegNum() << "]"; + cerr << " in inst:\t" << *MInst << "\n"; } // if register is not allocated, mark register as invalid @@ -563,18 +563,16 @@ void PhyRegAlloc::updateMachineCode() // instruction, add them now. // if( AddedInstrMap[ MInst ] ) { - - deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore; + std::deque<MachineInstr *> &IBef = AddedInstrMap[MInst]->InstrnsBefore; if( ! IBef.empty() ) { - - deque<MachineInstr *>::iterator AdIt; + std::deque<MachineInstr *>::iterator AdIt; for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) { if( DEBUG_RA) { cerr << "For inst " << *MInst; - cerr << " PREPENDed instr: " << **AdIt << endl; + cerr << " PREPENDed instr: " << **AdIt << "\n"; } MInstIterator = MIVec.insert( MInstIterator, *AdIt ); @@ -600,7 +598,7 @@ void PhyRegAlloc::updateMachineCode() if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){ move2DelayedInstr(MInst, *(MInstIterator+delay) ); - if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot"; + if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot"; } else { @@ -609,11 +607,11 @@ void PhyRegAlloc::updateMachineCode() // Here we can add the "instructions after" to the current // instruction since there are no delay slots for this instruction - deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter; + std::deque<MachineInstr *> &IAft = AddedInstrMap[MInst]->InstrnsAfter; if( ! IAft.empty() ) { - deque<MachineInstr *>::iterator AdIt; + std::deque<MachineInstr *>::iterator AdIt; ++MInstIterator; // advance to the next instruction @@ -621,7 +619,7 @@ void PhyRegAlloc::updateMachineCode() if(DEBUG_RA) { cerr << "For inst " << *MInst; - cerr << " APPENDed instr: " << **AdIt << endl; + cerr << " APPENDed instr: " << **AdIt << "\n"; } MInstIterator = MIVec.insert( MInstIterator, *AdIt ); @@ -669,9 +667,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, RegClass *RC = LR->getRegClass(); const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB); - - int TmpOff = - mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) ); + mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) ); MachineInstr *MIBef=NULL, *AdIMid=NULL, *MIAft=NULL; @@ -854,13 +850,10 @@ int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC, return MRI.getUnifiedRegNum(RC->getID(), c); else assert( 0 && "FATAL: No free register could be found in reg class!!"); - + return 0; } - - - //---------------------------------------------------------------------------- // This method modifies the IsColorUsedArr of the register class passed to it. // It sets the bits corresponding to the registers used by this machine @@ -909,14 +902,10 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, LiveRange *const LRofImpRef = LRI.getLiveRangeForValue( MInst->getImplicitRef(z) ); - - if( LRofImpRef ) - if( LRofImpRef->hasColor() ) - IsColorUsedArr[ LRofImpRef->getColor() ] = true; + + if(LRofImpRef && LRofImpRef->hasColor()) + IsColorUsedArr[LRofImpRef->getColor()] = true; } - - - } @@ -936,9 +925,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI, const MachineInstr *DelayedMI) { - // "added after" instructions of the original instr - deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter; + std::deque<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI]->InstrnsAfter; // "added instructions" of the delayed instr AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI]; @@ -949,21 +937,15 @@ void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI, } // "added after" instructions of the delayed instr - deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter; + std::deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter; // go thru all the "added after instructions" of the original instruction // and append them to the "addded after instructions" of the delayed // instructions - - deque<MachineInstr *>::iterator OrigAdIt; - - for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) { - DelayedAft.push_back( *OrigAdIt ); - } + DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end()); // empty the "added after instructions" of the original instruction OrigAft.clear(); - } //---------------------------------------------------------------------------- @@ -973,14 +955,14 @@ void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI, void PhyRegAlloc::printMachineCode() { - cout << endl << ";************** Method "; - cout << Meth->getName() << " *****************" << endl; + cerr << "\n;************** Method " << Meth->getName() + << " *****************\n"; Method::const_iterator BBI = Meth->begin(); // random iterator for BBs for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order - cout << endl ; printLabel( *BBI); cout << ": "; + cerr << "\n"; printLabel( *BBI); cerr << ": "; // get the iterator for machine instructions MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec(); @@ -992,8 +974,8 @@ void PhyRegAlloc::printMachineCode() MachineInstr *const MInst = *MInstIterator; - cout << endl << "\t"; - cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString; + cerr << "\n\t"; + cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString; //for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) { @@ -1009,41 +991,39 @@ void PhyRegAlloc::printMachineCode() const Value *const Val = Op.getVRegValue () ; // ****this code is temporary till NULL Values are fixed if( ! Val ) { - cout << "\t<*NULL*>"; + cerr << "\t<*NULL*>"; continue; } // if a label or a constant - if( (Val->getValueType() == Value::BasicBlockVal) ) { - - cout << "\t"; printLabel( Op.getVRegValue () ); - } - else { + if(isa<BasicBlock>(Val) { + cerr << "\t"; printLabel( Op.getVRegValue () ); + } else { // else it must be a register value const int RegNum = Op.getAllocatedRegNum(); - cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum ); + cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum ); if (Val->hasName() ) - cout << "(" << Val->getName() << ")"; + cerr << "(" << Val->getName() << ")"; else - cout << "(" << Val << ")"; + cerr << "(" << Val << ")"; if( Op.opIsDef() ) - cout << "*"; + cerr << "*"; const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val); if( LROfVal ) if( LROfVal->hasSpillOffset() ) - cout << "$"; + cerr << "$"; } } else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) { - cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum()); + cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum()); } else - cout << "\t" << Op; // use dump field + cerr << "\t" << Op; // use dump field } @@ -1051,23 +1031,22 @@ void PhyRegAlloc::printMachineCode() unsigned NumOfImpRefs = MInst->getNumImplicitRefs(); if( NumOfImpRefs > 0 ) { - cout << "\tImplicit:"; + cerr << "\tImplicit:"; for(unsigned z=0; z < NumOfImpRefs; z++) { printValue( MInst->getImplicitRef(z) ); - cout << "\t"; + cerr << "\t"; } } } // for all machine instructions - - cout << endl; + cerr << "\n"; } // for all BBs - cout << endl; + cerr << "\n"; } @@ -1125,9 +1104,9 @@ void PhyRegAlloc::colorIncomingArgs() assert( FirstMI && "No machine instruction in entry BB"); AddedInstrns *AI = AddedInstrMap[ FirstMI ]; - if ( !AI ) { + if (!AI) { AI = new AddedInstrns(); - AddedInstrMap[ FirstMI ] = AI; + AddedInstrMap[FirstMI] = AI; } MRI.colorMethodArgs(Meth, LRI, AI ); @@ -1137,12 +1116,11 @@ void PhyRegAlloc::colorIncomingArgs() //---------------------------------------------------------------------------- // Used to generate a label for a basic block //---------------------------------------------------------------------------- -void PhyRegAlloc::printLabel(const Value *const Val) -{ - if( Val->hasName() ) - cout << Val->getName(); +void PhyRegAlloc::printLabel(const Value *const Val) { + if (Val->hasName()) + cerr << Val->getName(); else - cout << "Label" << Val; + cerr << "Label" << Val; } @@ -1155,7 +1133,7 @@ void PhyRegAlloc::printLabel(const Value *const Val) void PhyRegAlloc::markUnusableSugColors() { - if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl; + if(DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n"; // hash map iterator LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); @@ -1193,22 +1171,18 @@ void PhyRegAlloc::markUnusableSugColors() void PhyRegAlloc::allocateStackSpace4SpilledLRs() { - if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl; + if(DEBUG_RA ) cerr << "\nsetting LR stack offsets ...\n"; // hash map iterator LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin(); LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end(); for( ; HMI != HMIEnd ; ++HMI ) { - if( (*HMI).first ) { - LiveRange *L = (*HMI).second; // get the LiveRange - if(L) - if( ! L->hasColor() ) - - // NOTE: ** allocating the size of long Type ** - L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, - Type::LongTy)); - + if(HMI->first && HMI->second) { + LiveRange *L = HMI->second; // get the LiveRange + if( ! L->hasColor() ) + // NOTE: ** allocating the size of long Type ** + L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy)); } } // for all LR's in hash map } diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h index 9d34557b01..6871b2d28a 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h @@ -1,4 +1,4 @@ -/* Title: PhyRegAlloc.h +/* Title: PhyRegAlloc.h -*- C++ -*- Author: Ruchira Sasanka Date: Aug 20, 01 Purpose: This is the main entry point for register allocation. @@ -54,13 +54,11 @@ class AddedInstrns { public: - deque<MachineInstr *> InstrnsBefore; // Added insts BEFORE an existing inst - deque<MachineInstr *> InstrnsAfter; // Added insts AFTER an existing inst - - AddedInstrns() : InstrnsBefore(), InstrnsAfter() { } + std::deque<MachineInstr*> InstrnsBefore;// Added insts BEFORE an existing inst + std::deque<MachineInstr*> InstrnsAfter; // Added insts AFTER an existing inst }; -typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType; +typedef std::hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType; @@ -74,7 +72,7 @@ typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType; class PhyRegAlloc: public NonCopyable { - vector<RegClass *> RegClassList ; // vector of register classes + std::vector<RegClass *> RegClassList; // vector of register classes const TargetMachine &TM; // target machine const Method* Meth; // name of the method we work on MachineCodeForMethod& mcInfo; // descriptor for method's native code @@ -115,8 +113,7 @@ class PhyRegAlloc: public NonCopyable const BasicBlock *BB, const unsigned OpNum); - inline void constructLiveRanges() - { LRI.constructLiveRanges(); } + inline void constructLiveRanges() { LRI.constructLiveRanges(); } void colorIncomingArgs(); void colorCallRetArgs(); @@ -141,12 +138,9 @@ class PhyRegAlloc: public NonCopyable void addInterf4PseudoInstr(const MachineInstr *MInst); - public: - PhyRegAlloc(Method *const M, const TargetMachine& TM, MethodLiveVarInfo *const Lvi); - ~PhyRegAlloc(); // main method called for allocating registers diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp index 3918871d69..8ba6a15ad1 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp +++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp @@ -1,5 +1,6 @@ #include "llvm/CodeGen/RegClass.h" - +#include <iostream> +using std::cerr; //---------------------------------------------------------------------------- // This constructor inits IG. The actual matrix is created by a call to @@ -11,7 +12,7 @@ RegClass::RegClass(const Method *const M, : Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ), IG(this), IGNodeStack(), ReservedColorList(RCL) { if( DEBUG_RA) - cout << "Created Reg Class: " << RegClassID << endl; + cerr << "Created Reg Class: " << RegClassID << "\n"; IsColorUsedArr = new bool[ Mrc->getNumOfAllRegs() ]; } @@ -23,7 +24,7 @@ RegClass::RegClass(const Method *const M, //---------------------------------------------------------------------------- void RegClass::colorAllRegs() { - if(DEBUG_RA) cout << "Coloring IG of reg class " << RegClassID << " ...\n"; + if(DEBUG_RA) cerr << "Coloring IG of reg class " << RegClassID << " ...\n"; // pre-color IGNodes pushAllIGNodes(); // push all IG Nodes @@ -57,9 +58,9 @@ void RegClass::pushAllIGNodes() bool PushedAll = pushUnconstrainedIGNodes(); if( DEBUG_RA) { - cout << " Puhsed all-unconstrained IGNodes. "; - if( PushedAll ) cout << " No constrained nodes left."; - cout << endl; + cerr << " Puhsed all-unconstrained IGNodes. "; + if( PushedAll ) cerr << " No constrained nodes left."; + cerr << "\n"; } if( PushedAll ) // if NO constrained nodes left @@ -129,8 +130,8 @@ bool RegClass::pushUnconstrainedIGNodes() IGNode->pushOnStack(); // set OnStack and dec deg of neighs if (DEBUG_RA > 1) { - cout << " pushed un-constrained IGNode " << IGNode->getIndex() ; - cout << " on to stack" << endl; + cerr << " pushed un-constrained IGNode " << IGNode->getIndex() ; + cerr << " on to stack\n"; } } else pushedall = false; // we didn't push all live ranges @@ -215,16 +216,16 @@ void RegClass::colorIGNode(IGNode *const Node) } else { if( DEBUG_RA ) { - cout << " Node " << Node->getIndex(); - cout << " already colored with color " << Node->getColor() << endl; + cerr << " Node " << Node->getIndex(); + cerr << " already colored with color " << Node->getColor() << "\n"; } } if( !Node->hasColor() ) { if( DEBUG_RA ) { - cout << " Node " << Node->getIndex(); - cout << " - could not find a color (needs spilling)" << endl; + cerr << " Node " << Node->getIndex(); + cerr << " - could not find a color (needs spilling)\n"; } } diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.h b/lib/Target/SparcV9/RegAlloc/RegClass.h index d6cbaf892b..fe25986f40 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.h +++ b/lib/Target/SparcV9/RegAlloc/RegClass.h @@ -13,8 +13,9 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineRegInfo.h" #include <stack> +#include <iostream> -typedef vector<unsigned int> ReservedColorListType; +typedef std::vector<unsigned int> ReservedColorListType; //----------------------------------------------------------------------------- @@ -46,7 +47,7 @@ class RegClass InterferenceGraph IG; // Interference graph - constructed by // buildInterferenceGraph - stack <IGNode *> IGNodeStack; // the stack used for coloring + std::stack<IGNode *> IGNodeStack; // the stack used for coloring const ReservedColorListType *const ReservedColorList; // @@ -117,21 +118,14 @@ class RegClass inline void printIGNodeList() const { - cerr << "IG Nodes for Register Class " << RegClassID << ":" << endl; + std::cerr << "IG Nodes for Register Class " << RegClassID << ":" << "\n"; IG.printIGNodeList(); } inline void printIG() { - cerr << "IG for Register Class " << RegClassID << ":" << endl; + std::cerr << "IG for Register Class " << RegClassID << ":" << "\n"; IG.printIG(); } - }; - - - - - - #endif diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp index fb2888b05d..098da9074e 100644 --- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp +++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp @@ -22,16 +22,17 @@ #include "Support/StringExtras.h" #include "Support/HashExtras.h" #include <locale.h> +using std::string; namespace { class SparcAsmPrinter { - typedef hash_map<const Value*, int> ValIdMap; + typedef std::hash_map<const Value*, int> ValIdMap; typedef ValIdMap:: iterator ValIdMapIterator; typedef ValIdMap::const_iterator ValIdMapConstIterator; - ostream &toAsm; + std::ostream &toAsm; SlotCalculator Table; // map anonymous values to unique integer IDs ValIdMap valToIdMap; // used for values not handled by SlotCalculator const UltraSparc &Target; @@ -45,7 +46,7 @@ class SparcAsmPrinter { } CurSection; public: - inline SparcAsmPrinter(ostream &o, const Module *M, const UltraSparc &t) + inline SparcAsmPrinter(std::ostream &o, const Module *M, const UltraSparc &t) : toAsm(o), Table(SlotCalculator(M, true)), Target(t), CurSection(Unknown) { emitModule(M); } @@ -61,7 +62,7 @@ private : void printGlobalVariable( const GlobalVariable* GV); void printSingleConstant( const Constant* CV); void printConstantValueOnly(const Constant* CV); - void printConstant( const Constant* CV, string valID=string("")); + void printConstant( const Constant* CV, std::string valID = ""); unsigned int printOperands(const MachineInstr *MI, unsigned int opNum); void printOneOperand(const MachineOperand &Op); @@ -88,7 +89,7 @@ private : toAsm << "\n"; } - string getValidSymbolName(const string &S) { + std::string getValidSymbolName(const string &S) { string Result; // Symbol names in Sparc assembly language have these rules: @@ -318,7 +319,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &op) case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_UnextendedImmed: - toAsm << op.getImmedValue(); + toAsm << (long)op.getImmedValue(); break; default: @@ -351,7 +352,7 @@ SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) else N = 1; - toAsm << endl; + toAsm << "\n"; } void @@ -393,7 +394,7 @@ SparcAsmPrinter::emitMethod(const Method *M) // Output a .size directive so the debugger knows the extents of the function toAsm << ".EndOf_" << methName << ":\n\t.size " << methName << ", .EndOf_" - << methName << "-" << methName << endl; + << methName << "-" << methName << "\n"; // Put some spaces between the methods toAsm << "\n\n"; @@ -487,7 +488,6 @@ TypeToAlignment(const Type* type, const TargetMachine& target) inline unsigned int ConstantToAlignment(const Constant* CV, const TargetMachine& target) { - unsigned int constantSize; if (ConstantArray* CPA = dyn_cast<ConstantArray>(CV)) if (ArrayTypeIsString(cast<ArrayType>(CPA->getType()))) return SizeToAlignment(1 + CPA->getNumOperands(), target); @@ -515,16 +515,15 @@ SparcAsmPrinter::printSingleConstant(const Constant* CV) { if (CV->getType() == Type::FloatTy || CV->getType() == Type::DoubleTy) toAsm << "0r"; // FP constants must have this prefix - toAsm << CV->getStrValue() << endl; + toAsm << CV->getStrValue() << "\n"; } else if (ConstantPointer* CPP = dyn_cast<ConstantPointer>(CV)) { - if (! CPP->isNullValue()) - assert(0 && "Cannot yet print non-null pointer constants to assembly"); - else - toAsm << (void*) NULL << endl; + assert(CPP->isNullValue() && + "Cannot yet print non-null pointer constants to assembly"); + toAsm << "0\n"; } - else if (ConstantPointerRef* CPRef = dyn_cast<ConstantPointerRef>(CV)) + else if (isa<ConstantPointerRef>(CV)) { assert(0 && "Cannot yet initialize pointer refs in assembly"); } @@ -543,17 +542,17 @@ SparcAsmPrinter::printConstantValueOnly(const Constant* CV) if (CPA && isStringCompatible(CPA)) { // print the string alone and return - toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << endl; + toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << "\n"; } else if (CPA) { // Not a string. Print the values in successive locations - const vector<Use>& constValues = CPA->getValues(); + const std::vector<Use> &constValues = CPA->getValues(); for (unsigned i=1; i < constValues.size(); i++) this->printConstantValueOnly(cast<Constant>(constValues[i].get())); } else if (ConstantStruct *CPS = dyn_cast<ConstantStruct>(CV)) { // Print the fields in successive locations - const vector<Use>& constValues = CPS->getValues(); + const std::vector<Use>& constValues = CPS->getValues(); for (unsigned i=1; i < constValues.size(); i++) this->printConstantValueOnly(cast<Constant>(constValues[i].get())); } @@ -571,25 +570,25 @@ SparcAsmPrinter::printConstant(const Constant* CV, string valID) valID = getID(CV); toAsm << "\t.align\t" << ConstantToAlignment(CV, Target) - << endl; + << "\n"; // Print .size and .type only if it is not a string. ConstantArray *CPA = dyn_cast<ConstantArray>(CV); if (CPA && isStringCompatible(CPA)) { // print it as a string and return - toAsm << valID << ":" << endl; - toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << endl; + toAsm << valID << ":\n"; + toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << "\n"; return; } - toAsm << "\t.type" << "\t" << valID << ",#object" << endl; + toAsm << "\t.type" << "\t" << valID << ",#object\n"; unsigned int constSize = ConstantToSize(CV, Target); if (constSize) toAsm << "\t.size" << "\t" << valID << "," - << constSize << endl; + << constSize << "\n"; - toAsm << valID << ":" << endl; + toAsm << valID << ":\n"; this->printConstantValueOnly(CV); } @@ -598,29 +597,29 @@ SparcAsmPrinter::printConstant(const Constant* CV, string valID) void SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV) { - toAsm << "\t.global\t" << getID(GV) << endl; + toAsm << "\t.global\t" << getID(GV) << "\n"; if (GV->hasInitializer()) printConstant(GV->getInitializer(), getID(GV)); else { toAsm << "\t.align\t" - << TypeToAlignment(GV->getType()->getElementType(), Target) << endl; - toAsm << "\t.type\t" << getID(GV) << ",#object" << endl; + << TypeToAlignment(GV->getType()->getElementType(), Target) << "\n"; + toAsm << "\t.type\t" << getID(GV) << ",#object\n"; toAsm << "\t.reserve\t" << getID(GV) << "," << TypeToSize(GV->getType()->getElementType(), Target) - << endl; + << "\n"; } } static void FoldConstants(const Module *M, - hash_set<const Constant*>& moduleConstants) + std::hash_set<const Constant*>& moduleConstants) { for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I) if (! (*I)->isExternal()) { - const hash_set<const Constant*>& pool = + const std::hash_set<const Constant*>& pool = MachineCodeForMethod::get(*I).getConstantPoolValues(); moduleConstants.insert(pool.begin(), pool.end()); } @@ -636,7 +635,7 @@ SparcAsmPrinter::emitGlobalsAndConstants(const Module *M) // lets force these constants into the slot table so that we can get // unique names for unnamed constants also. // - hash_set<const Constant*> moduleConstants; + std::hash_set<const Constant*> moduleConstants; FoldConstants(M, moduleConstants); // Now, emit the three data sections separately; the cost of I/O should @@ -654,7 +653,8 @@ SparcAsmPrinter::emitGlobalsAndConstants(const Module *M) } } - for (hash_set<const Constant*>::const_iterator I = moduleConstants.begin(), + for (std::hash_set<const Constant*>::const_iterator + I = moduleConstants.begin(), E = moduleConstants.end(); I != E; ++I) printConstant(*I); @@ -682,7 +682,7 @@ SparcAsmPrinter::emitGlobalsAndConstants(const Module *M) } } - toAsm << endl; + toAsm << "\n"; } @@ -705,7 +705,7 @@ SparcAsmPrinter::emitModule(const Module *M) // used. // void -UltraSparc::emitAssembly(const Module *M, ostream &toAsm) const +UltraSparc::emitAssembly(const Module *M, std::ostream &toAsm) const { SparcAsmPrinter Print(toAsm, M, *this); } diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp index 99bb14d12e..e00c871545 100644 --- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp +++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp @@ -27,7 +27,7 @@ static inline MachineInstr* CreateIntSetInstruction(int64_t C, Value* dest, - vector<TmpInstruction*>& tempVec) + std::vector<TmpInstruction*>& tempVec) { MachineInstr* minstr; uint64_t absC = (C >= 0)? C : -C; @@ -55,7 +55,7 @@ CreateIntSetInstruction(int64_t C, Value* dest, static inline MachineInstr* CreateUIntSetInstruction(uint64_t C, Value* dest, - vector<TmpInstruction*>& tempVec) + std::vector<TmpInstruction*>& tempVec) { MachineInstr* minstr; if (C > (unsigned int) ~0) @@ -109,9 +109,9 @@ UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt) // void UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val, - Instruction* dest, - vector<MachineInstr*>& minstrVec, - vector<TmpInstruction*>& tempVec) const + Instruction* dest, + std::vector<MachineInstr*>& minstrVec, + std::vector<TmpInstruction*>& tempVec) const { MachineInstr* minstr; @@ -200,19 +200,17 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val, // void UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(Method* method, - Value* val, - Instruction* dest, - vector<MachineInstr*>& minstrVec, - vector<TmpInstruction*>& tempVec, - TargetMachine& target) const + Value* val, + Instruction* dest, + std::vector<MachineInstr*>& minstrVec, + std::vector<TmpInstruction*>& tempVec, + TargetMachine& target) const { assert((val->getType()->isIntegral() || val->getType()->isPointerType()) && "Source type must be integral"); assert((dest->getType() ==Type::FloatTy || dest->getType() ==Type::DoubleTy) && "Dest type must be float/double"); - const MachineFrameInfo& frameInfo = ((UltraSparc&) target).getFrameInfo(); - MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(method); int offset = mcinfo.allocateLocalVar(target, val); @@ -246,19 +244,17 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(Method* method, // void UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(Method* method, - Value* val, - Instruction* dest, - vector<MachineInstr*>& minstrVec, - vector<TmpInstruction*>& tempVec, - TargetMachine& target) const + Value* val, + Instruction* dest, + std::vector<MachineInstr*>& minstrVec, + std::vector<TmpInstruction*>& tempVec, + TargetMachine& target) const { assert((val->getType() ==Type::FloatTy || val->getType() ==Type::DoubleTy) && "Source type must be float/double"); assert((dest->getType()->isIntegral() || dest->getType()->isPointerType()) && "Dest type must be integral"); - const MachineFrameInfo& frameInfo = ((UltraSparc&) target).getFrameInfo(); - MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(method); int offset = mcinfo.allocateLocalVar(target, val); diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index c4fe735672..c20c65a5ce 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -25,7 +25,7 @@ #include "llvm/ConstantVals.h" #include "Support/MathExtras.h" #include <math.h> - +using std::vector; //************************* Forward Declarations ***************************/ @@ -34,7 +34,7 @@ static void SetMemOperands_Internal (MachineInstr* minstr, const InstructionNode* vmInstrNode, Value* ptrVal, Value* arrayOffsetVal, - const vector<Value*>& idxVec, + const std::vector<Value*>& idxVec, const TargetMachine& target); @@ -143,7 +143,7 @@ ChooseBFpccInstruction(const InstructionNode* instrNode, static TmpInstruction* GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType) { - typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache; + typedef std::hash_map<const Value*, TmpInstruction*> BoolTmpCache; static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction* static const Method* lastMethod = NULL; // Use to flush cache between methods @@ -519,7 +519,6 @@ CreateMulConstInstruction(TargetMachine &target, { MachineInstr* minstr = NULL; // return NULL if we cannot exploit constant getMinstr2 = NULL; // to create a cheaper instruction - bool needNeg = false; Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); assert(isa<Constant>(constOp)); @@ -1011,8 +1010,6 @@ GetInstructionsForProlog(BasicBlock* entryBB, TargetMachine &target, MachineInstr** mvec) { - int64_t s0=0; // used to avoid overloading ambiguity below - const MachineFrameInfo& frameInfo = target.getFrameInfo(); // The second operand is the stack size. If it does not fit in the @@ -1048,11 +1045,10 @@ GetInstructionsForEpilog(BasicBlock* anExitBB, TargetMachine &target, MachineInstr** mvec) { - int64_t s0=0; // used to avoid overloading ambiguity below - mvec[0] = new MachineInstr(RESTORE); mvec[0]->SetMachineOperand(0, target.getRegInfo().getZeroRegNum()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0); + mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, + (int64_t)0); mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum()); return 1; @@ -1118,8 +1114,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, bool checkCast = false; // initialize here to use fall-through int nextRule; int forwardOperandNum = -1; - int64_t s0=0, s8=8; // variables holding constants to avoid - uint64_t u0=0; // overloading ambiguities below for (unsigned i=0; i < MAX_INSTR_PER_VMINSTR; i++) mvec[i] = NULL; @@ -1162,7 +1156,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, mvec[0] = new MachineInstr(JMPLRET); mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, returnReg); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,s8); + mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, + (int64_t)8); mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum()); if (returnInstr->getReturnValue() != NULL) @@ -1775,7 +1770,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, int n = numInstr++; mvec[n] = new MachineInstr(SETHI); mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed, - s0); + (int64_t)0); mvec[n]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister, setCCInstr); } @@ -2021,7 +2016,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, phi->getOperand(i)); break; } -#endif NEED_PHI_MACHINE_INSTRS +#endif // NEED_PHI_MACHINE_INSTRS case 71: // reg: VReg case 72: // reg: Constant diff --git a/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h b/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h index f62457cb49..848ddddd38 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h +++ b/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h @@ -58,4 +58,4 @@ ChooseStoreInstruction(const Type *DestTy) return 0; } -#endif SPARC_INSTR_SELECTION_SUPPORT_h +#endif diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index 51609f683f..a82d122336 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -128,8 +128,8 @@ public: // virtual void CreateCodeToLoadConst(Value* val, Instruction* dest, - vector<MachineInstr*>& minstrVec, - vector<TmpInstruction*>& tempVec) const; + std::vector<MachineInstr*>& minstrVec, + std::vector<TmpInstruction*>& tmp) const; // Create an instruction sequence to copy an integer value `val' @@ -141,8 +141,8 @@ public: virtual void CreateCodeToCopyIntToFloat(Method* method, Value* val, Instruction* dest, - vector<MachineInstr*>& minstrVec, - vector<TmpInstruction*>& tempVec, + std::vector<MachineInstr*>& minstr, + std::vector<TmpInstruction*>& temp, TargetMachine& target) const; // Similarly, create an instruction sequence to copy an FP value @@ -152,8 +152,8 @@ public: virtual void CreateCodeToCopyFloatToInt(Method* method, Value* val, Instruction* dest, - vector<MachineInstr*>& minstrVec, - vector<TmpInstruction*>& tempVec, + std::vector<MachineInstr*>& minstr, + std::vector<TmpInstruction*>& temp, TargetMachine& target) const; // create copy instruction(s) @@ -161,7 +161,7 @@ public: CreateCopyInstructionsByType(const TargetMachine& target, Value* src, Instruction* dest, - vector<MachineInstr*>& minstrVec) const; + std::vector<MachineInstr*>& minstr) const; }; @@ -245,7 +245,7 @@ class UltraSparcRegInfo : public MachineRegInfo LiveRangeInfo& LRI) const; void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI, - vector<RegClass *> RCList) const; + std::vector<RegClass *> RCList) const; @@ -348,12 +348,13 @@ class UltraSparcRegInfo : public MachineRegInfo // the register allocator in association with method calling. See // SparcRegInfo.cpp for more details // - void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst, - PhyRegAlloc &PRA ) const; + void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec, + MachineInstr *UnordInst, + PhyRegAlloc &PRA) const; - void OrderAddedInstrns( vector<MachineInstr *> &UnordVec, - vector<MachineInstr *> &OrdVec, - PhyRegAlloc &PRA) const; + void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec, + std::vector<MachineInstr *> &OrdVec, + PhyRegAlloc &PRA) const; // To find whether a particular call is to a var arg method @@ -410,7 +411,7 @@ class UltraSparcRegInfo : public MachineRegInfo else if( ty <= Type::DoubleTyID) res = FloatRegClassID; // sparc float reg class else { - cerr << "TypeID: " << ty << endl; + std::cerr << "TypeID: " << ty << "\n"; assert(0 && "Cannot resolve register class for type"); return 0; } @@ -449,10 +450,11 @@ class UltraSparcRegInfo : public MachineRegInfo LiveRangeInfo& LRI) const; void suggestRegs4CallArgs(const MachineInstr *const CallMI, - LiveRangeInfo& LRI, vector<RegClass *> RCL) const; + LiveRangeInfo& LRI, + std::vector<RegClass *> RCL) const; void suggestReg4RetValue(const MachineInstr *const RetMI, - LiveRangeInfo& LRI ) const; + LiveRangeInfo& LRI) const; void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI, @@ -493,7 +495,7 @@ class UltraSparcRegInfo : public MachineRegInfo // given the unified register number, this gives the name // for generating assembly code or debugging. // - inline const string getUnifiedRegName(int reg) const { + inline const std::string getUnifiedRegName(int reg) const { if( reg < 32 ) return SparcIntRegOrder::getRegName(reg); else if ( reg < (64 + 32) ) @@ -513,7 +515,7 @@ class UltraSparcRegInfo : public MachineRegInfo // The fllowing methods are used by instruction selection // - inline unsigned int getRegNumInCallersWindow(int reg) { + inline unsigned getRegNumInCallersWindow(int reg) { if (reg == InvalidRegNum || reg >= 32) return reg; return SparcIntRegOrder::getRegNumInCallersWindow(reg); @@ -1433,7 +1435,7 @@ public: // module. The specified module must have been compiled before this may be // used. // - virtual void emitAssembly(const Module *M, ostream &OutStr) const; + virtual void emitAssembly(const Module *M, std::ostream &OutStr) const; }; diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp index 6b39d61f5e..709a8f4c7f 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp @@ -1,7 +1,8 @@ -#include "llvm/CodeGen/IGNode.h" #include "SparcInternals.h" - +#include "llvm/CodeGen/IGNode.h" #include "llvm/Target/Sparc.h" +#include <iostream> +using std::cerr; //----------------------------------------------------------------------------- // Int Register Class - method for coloring a node in the interference graph. @@ -37,7 +38,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const } if( DEBUG_RA ) { - cout << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"; + cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"; LR->printSet(); } @@ -53,18 +54,18 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const // there are no call interferences. Otherwise, it will get spilled. if (DEBUG_RA) - cout << "\n -Coloring with sug color: " << SugCol; + cerr << "\n -Coloring with sug color: " << SugCol; LR->setColor( LR->getSuggestedColor() ); return; } else if(DEBUG_RA) - cout << "\n Couldn't alloc Sug col - LR voloatile & calls interf"; + cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf"; } else if ( DEBUG_RA ) { // can't allocate the suggested col cerr << " \n Could NOT allocate the suggested color (already used) "; - LR->printSet(); cerr << endl; + LR->printSet(); cerr << "\n"; } } @@ -91,7 +92,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const if( ColorFound) { LR->setColor(c); // first color found in preffered order - if (DEBUG_RA) cout << "\n Colored after first search with col " << c ; + if (DEBUG_RA) cerr << "\n Colored after first search with col " << c ; } // if color is not found because of call interference @@ -113,7 +114,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const // since LR span across calls, must save across calls // LR->markForSaveAcrossCalls(); - if(DEBUG_RA) cout << "\n Colored after SECOND search with col " << c ; + if(DEBUG_RA) cerr << "\n Colored after SECOND search with col " << c ; } } @@ -193,7 +194,7 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const } else if (DEBUG_RA) { // can't allocate the suggested col cerr << " Could NOT allocate the suggested color for LR "; - LR->printSet(); cerr << endl; + LR->printSet(); cerr << "\n"; } } diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.h b/lib/Target/SparcV9/SparcV9RegClassInfo.h index 0a5f5169d1..9127ffdaf6 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.h +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.h @@ -17,7 +17,7 @@ // Int register names in same order as enum in class SparcIntRegOrder -static string const IntRegNames[] = +static const std::string IntRegNames[] = { "o0", "o1", "o2", "o3", "o4", "o5", "o7", "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", @@ -75,7 +75,7 @@ class SparcIntRegOrder{ static unsigned int const NumOfAllRegs = o6 + 1; - static const string getRegName(const unsigned reg) { + static const std::string getRegName(const unsigned reg) { assert( reg < NumOfAllRegs ); return IntRegNames[reg]; } @@ -119,7 +119,7 @@ class SparcIntRegClass : public MachineRegClassInfo // Float Register Class //----------------------------------------------------------------------------- -static string const FloatRegNames[] = +static const std::string FloatRegNames[] = { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", @@ -157,7 +157,7 @@ class SparcFloatRegOrder{ static unsigned int const StartOfAllRegs = f0; - static const string getRegName(const unsigned reg) { + static const std::string getRegName(const unsigned reg) { assert( reg < NumOfAllRegs ); return FloatRegNames[reg]; } @@ -203,7 +203,7 @@ class SparcFloatRegClass : public MachineRegClassInfo //----------------------------------------------------------------------------- -static string const IntCCRegNames[] = +static const std::string IntCCRegNames[] = { "xcc", "ccr" }; @@ -218,7 +218,7 @@ class SparcIntCCRegOrder{ xcc, ccr // only one is available - see the note above }; - static const string getRegName(const unsigned reg) { + static const std::string getRegName(const unsigned reg) { assert( reg < 2 ); return IntCCRegNames[reg]; } @@ -253,7 +253,7 @@ public: //----------------------------------------------------------------------------- -static string const FloatCCRegNames[] = +static const std::string FloatCCRegNames[] = { "fcc0", "fcc1", "fcc2", "fcc3" }; @@ -268,7 +268,7 @@ class SparcFloatCCRegOrder{ fcc0, fcc1, fcc2, fcc3 }; - static const string getRegName(const unsigned reg) { + static const std::string getRegName(const unsigned reg) { assert( reg < 4 ); return FloatCCRegNames[reg]; } diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index 6543397957..dcfc5fa378 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -8,6 +8,8 @@ #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/DerivedTypes.h" +#include <iostream> +using std::cerr; //--------------------------------------------------------------------------- // Purpose: @@ -21,11 +23,10 @@ //--------------------------------------------------------------------------- const Value * UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const { - unsigned OpCode = CallMI->getOpCode(); - unsigned NumOfImpRefs = CallMI->getNumImplicitRefs(); + unsigned NumOfImpRefs = CallMI->getNumImplicitRefs(); - if( OpCode == CALL ) { + if (OpCode == CALL) { // The one before the last implicit operand is the return value of // a CALL instr @@ -34,14 +35,13 @@ UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const { if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) ) return CallMI->getImplicitRef(NumOfImpRefs-2); - } - else if( OpCode == JMPLCALL) { + } else if (OpCode == JMPLCALL) { // The last implicit operand is the return value of a JMPL // - if( NumOfImpRefs > 0 ) - if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) ) - return CallMI->getImplicitRef(NumOfImpRefs-1); + if(NumOfImpRefs > 0) + if (CallMI->implicitRefIsDefined(NumOfImpRefs-1)) + return CallMI->getImplicitRef(NumOfImpRefs-1); } else assert(0 && "OpCode must be CALL/JMPL for a call instr"); @@ -189,7 +189,7 @@ void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr * RetMI, //--------------------------------------------------------------------------- void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI, - vector<RegClass *> RCList) const { + std::vector<RegClass *> RCList) const { const Value *RetAddrVal = getCallInstRetAddr( CallMI ); @@ -361,10 +361,8 @@ void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth, // that on to the stack pos of LR if( isArgInReg ) { - - MachineInstr *AdIBef = - cpReg2MemMI(UniArgReg, getFramePointer(), - LR->getSpillOffFromFP(), RegType ); + cpReg2MemMI(UniArgReg, getFramePointer(), + LR->getSpillOffFromFP(), RegType ); FirstAI->InstrnsBefore.push_back( AdMI ); } @@ -404,7 +402,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth, //--------------------------------------------------------------------------- void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI, - vector<RegClass *> RCList) const { + std::vector<RegClass *> RCList) const { assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); @@ -469,7 +467,7 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI, if( !LR ) { if( DEBUG_RA) { cerr << " ERROR: In call instr, no LR for arg: " ; - printValue(CallArg); cerr << endl; + printValue(CallArg); cerr << "\n"; } assert(0 && "NO LR for call arg"); // continue; @@ -485,7 +483,7 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI, else if (DEBUG_RA) // Do NOTHING as this will be colored as a normal value. - cerr << " Regr not suggested for int call arg" << endl; + cerr << " Regr not suggested for int call arg\n"; } else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs) @@ -535,7 +533,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI, if( !RetValLR ) { cerr << "\nNo LR for:"; printValue( RetVal ); - cerr << endl; + cerr << "\n"; assert( RetValLR && "ERR:No LR for non-void return value"); //return; } @@ -601,7 +599,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI, // Now color all args of the call instruction //------------------------------------------- - vector <MachineInstr *> AddedInstrnsBefore; + std::vector<MachineInstr *> AddedInstrnsBefore; unsigned NumOfCallArgs = getCallInstNumArgs( CallMI ); @@ -662,7 +660,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI, if( !LR ) { if( DEBUG_RA) { cerr << " ERROR: In call instr, no LR for arg: " ; - printValue(CallArg); cerr << endl; + printValue(CallArg); cerr << "\n"; } assert(0 && "NO LR for call arg"); // continue; @@ -812,7 +810,7 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI, cerr << *(AddedInstrnsBefore[i]); } - vector <MachineInstr *> TmpVec; + std::vector<MachineInstr *> TmpVec; OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA); if( DEBUG_RA ) { @@ -855,13 +853,12 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI, // The first implicit operand is the return value of a return instr const Value *RetVal = RetMI->getImplicitRef(0); - MachineInstr *AdMI; LiveRange *const LR = LRI.getLiveRangeForValue( RetVal ); if( !LR ) { cerr << "\nNo LR for:"; printValue( RetVal ); - cerr << endl; + cerr << "\n"; assert( LR && "No LR for return value of non-void method"); //return; } @@ -898,13 +895,12 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI, // The first implicit operand is the return value of a return instr const Value *RetVal = RetMI->getImplicitRef(0); - MachineInstr *AdMI; LiveRange *const LR = LRI.getLiveRangeForValue( RetVal ); if( ! LR ) { cerr << "\nNo LR for:"; printValue( RetVal ); - cerr << endl; + cerr << "\n"; // assert( LR && "No LR for return value of non-void method"); return; } @@ -941,16 +937,14 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI, // the LR received UniLRReg but must be colored with UniRetReg // to pass as the return value - - AdMI = cpReg2RegMI( UniLRReg, UniRetReg, RegType); - RetAI->InstrnsBefore.push_back( AdMI ); + RetAI->InstrnsBefore.push_back(cpReg2RegMI(UniLRReg, UniRetReg, RegType)); } else { // if the LR is spilled - - AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), - UniRetReg, RegType); - RetAI->InstrnsBefore.push_back( AdMI ); - cout << "\nCopied the return value from stack"; + MachineInstr *AdMI = cpMem2RegMI(getFramePointer(), + LR->getSpillOffFromFP(), + UniRetReg, RegType); + RetAI->InstrnsBefore.push_back(AdMI); + cerr << "\nCopied the return value from stack\n"; } } // if there is a return value @@ -1179,9 +1173,7 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst, // has set to record which registers were saved/restored // - hash_set<unsigned> PushedRegSet; - - + std::hash_set<unsigned> PushedRegSet; // Now find the LR of the return value of the call // The last *implicit operand* is the return value of a call @@ -1394,7 +1386,7 @@ void UltraSparcRegInfo::printReg(const LiveRange *const LR) { cerr << " *Node " << (LR->getUserIGNode())->getIndex(); if( ! LR->hasColor() ) { - cerr << " - could not find a color" << endl; + cerr << " - could not find a color\n"; return; } @@ -1403,15 +1395,13 @@ void UltraSparcRegInfo::printReg(const LiveRange *const LR) { cerr << " colored with color "<< LR->getColor(); if( RegClassID == IntRegClassID ) { + cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n"; - cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ; - cerr << "]" << endl; - } - else if ( RegClassID == FloatRegClassID) { + } else if ( RegClassID == FloatRegClassID) { cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor()); if( LR->getTypeID() == Type::DoubleTyID ) cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1); - cerr << "]" << endl; + cerr << "]\n"; } } @@ -1436,9 +1426,9 @@ void UltraSparcRegInfo::printReg(const LiveRange *const LR) { //--------------------------------------------------------------------------- -void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec, - vector<MachineInstr *> &OrdVec, - PhyRegAlloc &PRA) const{ +void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec, + std::vector<MachineInstr *> &OrdVec, + PhyRegAlloc &PRA) const{ /* Problem: We can have instructions inserted by RegAlloc like @@ -1476,7 +1466,7 @@ void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec, CouldMoveAll = true; - vector<MachineInstr *>::iterator DefIt = UnordVec.begin(); + std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin(); for( ; DefIt != UnordVec.end(); ++DefIt ) { @@ -1498,7 +1488,7 @@ void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec, bool DefEqUse = false; - vector<MachineInstr *>::iterator UseIt = DefIt; + std::vector<MachineInstr *>::iterator UseIt = DefIt; UseIt++; for( ; UseIt != UnordVec.end(); ++UseIt ) { @@ -1572,7 +1562,7 @@ void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec, -void UltraSparcRegInfo::moveInst2OrdVec(vector<MachineInstr *> &OrdVec, +void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst, PhyRegAlloc &PRA ) const { @@ -1585,7 +1575,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(vector<MachineInstr *> &OrdVec, // before in the OrdVec bool DefEqUse = false; - vector<MachineInstr *>::iterator OrdIt = OrdVec.begin(); + std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin(); for( ; OrdIt != OrdVec.end(); ++OrdIt ) { diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp index 9524e80515..dd9e330474 100644 --- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp +++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp @@ -17,7 +17,8 @@ #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" #include "llvm/Method.h" - +#include <iostream> +using std::cerr; // Build the MachineInstruction Description Array... const MachineInstrDescriptor SparcMachineInstrDesc[] = { @@ -47,10 +48,9 @@ void AllocateRegisters(Method *M, TargetMachine &target) if ( (M)->isExternal() ) // don't process prototypes return; - if( DEBUG_RA ) { - cerr << endl << "******************** Method "<< (M)->getName(); - cerr << " ********************" <<endl; - } + if( DEBUG_RA ) + cerr << "\n******************** Method "<< M->getName() + << " ********************\n"; MethodLiveVarInfo LVI(M ); // Analyze live varaibles LVI.analyze(); @@ -60,7 +60,7 @@ void AllocateRegisters(Method *M, TargetMachine &target) PRA.allocateRegisters(); - if( DEBUG_RA ) cerr << endl << "Register allocation complete!" << endl; + if( DEBUG_RA ) cerr << "\nRegister allocation complete!\n"; } diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp index b290f29b85..0df60fde67 100644 --- a/lib/Target/TargetData.cpp +++ b/lib/Target/TargetData.cpp @@ -40,7 +40,7 @@ StructLayout::StructLayout(const StructType *ST, const TargetData &TD) StructSize = (StructSize/TyAlign + 1) * TyAlign; // Add padding... // Keep track of maximum alignment constraint - StructAlignment = max(TyAlign, StructAlignment); + StructAlignment = std::max(TyAlign, StructAlignment); MemberOffsets.push_back(StructSize); StructSize += TySize; // Consume space for this data item... @@ -71,7 +71,7 @@ Annotation *TargetData::TypeAnFactory(AnnotationID AID, const Annotable *T, // TargetData Class Implementation //===----------------------------------------------------------------------===// -TargetData::TargetData(const string &TargetName, unsigned char PtrSize = 8, +TargetData::TargetData(const std::string &TargetName, unsigned char PtrSize = 8, unsigned char PtrAl = 8, unsigned char DoubleAl = 8, unsigned char FloatAl = 4, unsigned char LongAl = 8, unsigned char IntAl = 4, unsigned char ShortAl = 2, @@ -146,7 +146,7 @@ unsigned char TargetData::getTypeAlignment(const Type *Ty) const { } unsigned TargetData::getIndexedOffset(const Type *ptrTy, - const vector<Value*> &Idx) const { + const std::vector<Value*> &Idx) const { const PointerType *PtrTy = cast<const PointerType>(ptrTy); unsigned Result = 0; diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp index f9dca290b0..c02654f03b 100644 --- a/lib/Target/TargetSchedInfo.cpp +++ b/lib/Target/TargetSchedInfo.cpp @@ -21,8 +21,8 @@ resourceId_t MachineResource::nextId = 0; // (stl_algo.h). // inline static bool -RUConflict(const vector<resourceId_t>& fromRVec, - const vector<resourceId_t>& toRVec) +RUConflict(const std::vector<resourceId_t>& fromRVec, + const std::vector<resourceId_t>& toRVec) { unsigned fN = fromRVec.size(), tN = toRVec.size(); @@ -57,7 +57,7 @@ ComputeMinGap(const InstrRUsage &fromRU, { // check if instr. #2 can start executing `gap' cycles after #1 // by checking for resource conflicts in each overlapping cycle - cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles); + cycles_t numOverlap =std::min(fromRU.numCycles - gap, toRU.numCycles); for (cycles_t c = 0; c <= numOverlap-1; c++) if (RUConflict(fromRU.resourcesByCycle[gap + c], toRU.resourcesByCycle[c])) @@ -102,7 +102,7 @@ MachineSchedInfo::initializeResources() // most instructions will probably behave the same as their class. // Cannot allocate a vector of InstrRUsage so new each one. // - vector<InstrRUsage> instrRUForClasses; + std::vector<InstrRUsage> instrRUForClasses; instrRUForClasses.resize(numSchedClasses); for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) { // instrRUForClasses.push_back(new InstrRUsage); @@ -116,7 +116,7 @@ MachineSchedInfo::initializeResources() void -MachineSchedInfo::computeInstrResources(const vector<InstrRUsage>& +MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses) { int numOpCodes = mii->getNumRealOpCodes(); @@ -146,7 +146,7 @@ MachineSchedInfo::computeInstrResources(const vector<InstrRUsage>& void -MachineSchedInfo::computeIssueGaps(const vector<InstrRUsage>& +MachineSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses) { int numOpCodes = mii->getNumRealOpCodes(); @@ -186,7 +186,7 @@ MachineSchedInfo::computeIssueGaps(const vector<InstrRUsage>& { issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap; conflictLists[fromOp].push_back(toOp); - longestIssueConflict = max(longestIssueConflict, instrPairGap); + longestIssueConflict = std::max(longestIssueConflict, instrPairGap); } } } |