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-rw-r--r--lib/Target/ARM/ARMBaseRegisterInfo.cpp7
-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp34
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp15
-rw-r--r--lib/Target/ARM/ARMJITInfo.cpp12
-rw-r--r--lib/Target/ARM/ARMLoadStoreOptimizer.cpp7
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.cpp4
-rw-r--r--lib/Target/ARM/Thumb1RegisterInfo.cpp4
-rw-r--r--lib/Target/ARM/Thumb2RegisterInfo.cpp4
8 files changed, 41 insertions, 46 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index c266d1aa94..3cefe43712 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@@ -69,8 +70,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
case S30: return 30;
case S31: return 31;
default:
- assert(0 && "Unknown ARM register!");
- abort();
+ LLVM_UNREACHABLE("Unknown ARM register!");
}
}
@@ -81,8 +81,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
using namespace ARM;
switch (RegEnum) {
default:
- assert(0 && "Unknown ARM register!");
- abort();
+ LLVM_UNREACHABLE("Unknown ARM register!");
case R0: case D0: return 0;
case R1: case D1: return 1;
case R2: case D2: return 2;
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index da7e85e5d0..f436e97bcc 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -35,6 +35,8 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#ifndef NDEBUG
#include <iomanip>
#endif
@@ -221,7 +223,7 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
template<class CodeEmitter>
unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
switch (ARM_AM::getAM2ShiftOpc(Imm)) {
- default: assert(0 && "Unknown shift opc!");
+ default: LLVM_UNREACHABLE("Unknown shift opc!");
case ARM_AM::asr: return 2;
case ARM_AM::lsl: return 0;
case ARM_AM::lsr: return 1;
@@ -255,8 +257,10 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
else if (MO.isMBB())
emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
else {
- cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
- abort();
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "ERROR: Unknown type of MachineOperand: " << MO;
+ llvm_report_error(Msg.str());
}
return 0;
}
@@ -336,7 +340,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
NumEmitted++; // Keep track of the # of mi's emitted
switch (MI.getDesc().TSFlags & ARMII::FormMask) {
default: {
- assert(0 && "Unhandled instruction encoding format!");
+ LLVM_UNREACHABLE("Unhandled instruction encoding format!");
break;
}
case ARMII::Pseudo:
@@ -454,12 +458,10 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
else if (CFP->getType() == Type::DoubleTy)
emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
else {
- assert(0 && "Unable to handle this constantpool entry!");
- abort();
+ LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
}
} else {
- assert(0 && "Unable to handle this constantpool entry!");
- abort();
+ LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
}
}
}
@@ -586,13 +588,12 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
- abort(); // FIXME:
+ llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
if (MI.getOperand(0).getSymbolName()[0]) {
- assert(0 && "JIT does not support inline asm!\n");
- abort();
+ llvm_report_error("JIT does not support inline asm!\n");
}
break;
}
@@ -674,7 +675,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
// ROR - 0111
// RRX - 0110 and bit[11:8] clear.
switch (SOpc) {
- default: assert(0 && "Unknown shift opc!");
+ default: LLVM_UNREACHABLE("Unknown shift opc!");
case ARM_AM::lsl: SBits = 0x1; break;
case ARM_AM::lsr: SBits = 0x3; break;
case ARM_AM::asr: SBits = 0x5; break;
@@ -688,7 +689,7 @@ unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
// ASR - 100
// ROR - 110
switch (SOpc) {
- default: assert(0 && "Unknown shift opc!");
+ default: LLVM_UNREACHABLE("Unknown shift opc!");
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x2; break;
case ARM_AM::asr: SBits = 0x4; break;
@@ -741,8 +742,7 @@ void Emitter<CodeEmitter>::emitDataProcessingInstruction(
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::BFC) {
- cerr << "ERROR: ARMv6t2 JIT is not yet supported.\n";
- abort();
+ llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
}
// Part of binary is determined by TableGn.
@@ -956,7 +956,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) {
// DA - Decrement after - bit U = 0 and bit P = 0
// DB - Decrement before - bit U = 0 and bit P = 1
switch (Mode) {
- default: assert(0 && "Unknown addressing sub-mode!");
+ default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
case ARM_AM::da: break;
case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
@@ -1120,7 +1120,7 @@ void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::TPsoft)
- abort(); // FIXME
+ llvm_report_error("ARM::TPsoft FIXME"); // FIXME
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index b207bcc356..2d29142e38 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/VectorExtras.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
@@ -2258,7 +2259,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op) {
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: assert(0 && "Don't know how to custom lower this!"); abort();
+ default: LLVM_UNREACHABLE("Don't know how to custom lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress:
return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
@@ -2593,8 +2594,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
case Intrinsic::arm_neon_vshiftlu:
if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
break;
- assert(0 && "invalid shift count for vshll intrinsic");
- abort();
+ LLVM_UNREACHABLE("invalid shift count for vshll intrinsic");
case Intrinsic::arm_neon_vrshifts:
case Intrinsic::arm_neon_vrshiftu:
@@ -2611,8 +2611,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
case Intrinsic::arm_neon_vqshiftsu:
if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
break;
- assert(0 && "invalid shift count for vqshlu intrinsic");
- abort();
+ LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic");
case Intrinsic::arm_neon_vshiftn:
case Intrinsic::arm_neon_vrshiftn:
@@ -2625,8 +2624,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
// Narrowing shifts require an immediate right shift.
if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
break;
- assert(0 && "invalid shift count for narrowing vector shift intrinsic");
- abort();
+ LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic");
default:
assert(0 && "unhandled vector shift");
@@ -2687,8 +2685,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
VShiftOpc = ARMISD::VSRI;
else {
- assert(0 && "invalid shift count for vsli/vsri intrinsic");
- abort();
+ LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic");
}
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp
index e551c41936..bc28919817 100644
--- a/lib/Target/ARM/ARMJITInfo.cpp
+++ b/lib/Target/ARM/ARMJITInfo.cpp
@@ -21,13 +21,14 @@
#include "llvm/CodeGen/JITCodeEmitter.h"
#include "llvm/Config/alloca.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Streams.h"
#include "llvm/System/Memory.h"
#include <cstdlib>
using namespace llvm;
void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
- abort();
+ llvm_report_error("ARMJITInfo::replaceMachineCodeForFunction");
}
/// JITCompilerFunction - This contains the address of the JIT function used to
@@ -103,8 +104,7 @@ extern "C" {
);
#else // Not an ARM host
void ARMCompilationCallback() {
- assert(0 && "Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
- abort();
+ LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
}
#endif
}
@@ -123,14 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) {
// ldr pc, [pc,#-4]
// <addr>
if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
- cerr << "ERROR: Unable to mark stub writable\n";
- abort();
+ llvm_report_error("ERROR: Unable to mark stub writable");
}
*(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
*(intptr_t *)(StubAddr+4) = NewVal;
if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
- cerr << "ERROR: Unable to mark stub executable\n";
- abort();
+ llvm_report_error("ERROR: Unable to mark stub executable");
}
}
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 59cf125a9b..d9e21b8e07 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -29,6 +29,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -119,7 +120,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
case ARM::FSTD:
NumFSTMGened++;
return ARM::FSTMD;
- default: abort();
+ default: llvm_report_error("Unhandled opcode!");
}
return 0;
}
@@ -441,7 +442,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
case ARM::FLDD: return ARM::FLDMD;
case ARM::FSTS: return ARM::FSTMS;
case ARM::FSTD: return ARM::FSTMD;
- default: abort();
+ default: llvm_report_error("Unhandled opcode!");
}
return 0;
}
@@ -454,7 +455,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
case ARM::FLDD: return ARM::FLDMD;
case ARM::FSTS: return ARM::FSTMS;
case ARM::FSTD: return ARM::FSTMD;
- default: abort();
+ default: llvm_report_error("Unhandled opcode!");
}
return 0;
}
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 6b70abe3f9..c6ac5b53ba 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@@ -290,8 +291,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
break;
}
default:
- assert(0 && "Unsupported addressing mode!");
- abort();
+ LLVM_UNREACHABLE("Unsupported addressing mode!");
break;
}
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 92f01d1006..7417e58b89 100644
--- a/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -30,6 +30,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
static cl::opt<bool>
@@ -452,8 +453,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
break;
}
default:
- assert(0 && "Unsupported addressing mode!");
- abort();
+ LLVM_UNREACHABLE("Unsupported addressing mode!");
break;
}
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp
index 0f0c0e41fc..42d39a6f69 100644
--- a/lib/Target/ARM/Thumb2RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp
@@ -30,6 +30,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
static cl::opt<bool>
@@ -452,8 +453,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
break;
}
default:
- assert(0 && "Unsupported addressing mode!");
- abort();
+ llvm_report_error("Unsupported addressing mode!");
break;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-21 18:17:01 +0000