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-rw-r--r--lib/Target/ARM/ARMRegisterInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index d393e8d7e3..e4b18088ad 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -123,7 +123,7 @@ def FPSCR : ARMReg<1, "fpscr">;
// r10 == Stack Limit
//
def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
- R7, R8, R9, R10, R12, R11,
+ R7, R8, R9, R10, R11, R12,
LR, SP, PC]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;