3 files changed, 7 insertions, 7 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 40ab4c2dd9..49b7ef2682 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -541,7 +541,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
   const TargetInstrDescriptor *TID = getDesc();
   if (TID->isPredicable()) {
     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+      if (TID->OpInfo[i].isPredicate())
         return i;
   }
 
@@ -591,7 +591,7 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) {
   const TargetInstrDescriptor *TID = MI->getDesc();
   if (TID->isPredicable()) {
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+      if (TID->OpInfo[i].isPredicate()) {
         // Predicated operands must be last operands.
         addOperand(MI->getOperand(i));
       }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3ef907ee1a..e3e54c50a9 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -296,9 +296,9 @@ static const TargetRegisterClass *getInstrOperandRegClass(
     assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
     return NULL;
   }
-  const TargetOperandInfo &toi = II->OpInfo[Op];
-  return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
-         ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+  if (II->OpInfo[Op].isLookupPtrRegClass())
+    return TII->getPointerRegClass();
+  return MRI->getRegClass(II->OpInfo[Op].RegClass);
 }
 
 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
@@ -435,7 +435,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
     unsigned VReg = getVR(Op, VRBaseMap);
     const TargetInstrDescriptor *TID = MI->getDesc();
     bool isOptDef = (IIOpNum < TID->numOperands)
-      ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
+      ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
     MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
     
     // Verify that it is right.
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 207f371b09..4498c984e2 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -38,7 +38,7 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
   const TargetInstrDescriptor *TID = MI->getDesc();
   if (TID->isPredicable()) {
     for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+      if (TID->OpInfo[i].isPredicate()) {
         MachineOperand &MO = MI->getOperand(i);
         if (MO.isReg()) {
           MO.setReg(Pred[j].getReg());