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-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h1
-rw-r--r--include/llvm/Target/TargetLowering.h6
2 files changed, 2 insertions, 5 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 38175808ab..f22ac902de 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -292,7 +292,6 @@ private:
MachineBasicBlock *CodeGenAndEmitDAG(MachineBasicBlock *BB);
void LowerArguments(const BasicBlock *BB);
- void ShrinkDemandedOps();
void ComputeLiveOutVRegInfo();
/// Create the scheduler. If a specific scheduler was specified
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 5efebe637e..d2646fd09d 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -766,14 +766,12 @@ public:
SelectionDAG &DAG;
bool LegalTys;
bool LegalOps;
- bool ShrinkOps;
SDValue Old;
SDValue New;
explicit TargetLoweringOpt(SelectionDAG &InDAG,
- bool LT, bool LO,
- bool Shrink = false) :
- DAG(InDAG), LegalTys(LT), LegalOps(LO), ShrinkOps(Shrink) {}
+ bool LT, bool LO) :
+ DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
bool LegalTypes() const { return LegalTys; }
bool LegalOperations() const { return LegalOps; }