diff options
Diffstat (limited to 'include/llvm/CodeGen')
20 files changed, 191 insertions, 191 deletions
diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index 512cae7927..f28c00faee 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -1,10 +1,10 @@ //===-- llvm/CodeGen/AsmPrinter.h - AsmPrinter Framework --------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This class is intended to be used as a base class for target-specific @@ -78,7 +78,7 @@ namespace llvm { /// AsciiDirective - This directive allows emission of an ascii string with /// the standard C escape characters embedded into it. const char *AsciiDirective; - + /// DataDirectives - These directives are used to output some unit of /// integer data to the current section. If a data directive is set to /// null, smaller data directives will be used to emit the large sizes. diff --git a/include/llvm/CodeGen/InstrScheduling.h b/include/llvm/CodeGen/InstrScheduling.h index 816aa7e806..c9aee2244a 100644 --- a/include/llvm/CodeGen/InstrScheduling.h +++ b/include/llvm/CodeGen/InstrScheduling.h @@ -1,10 +1,10 @@ //===-- InstrScheduling.h - Interface To Instruction Scheduling -*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines a minimal, but complete, interface to instruction @@ -22,7 +22,7 @@ class TargetMachine; //--------------------------------------------------------------------------- // Function: createScheduleInstructionsWithSSAPass(..) -// +// // Purpose: // Entry point for instruction scheduling on SSA form. // Schedules the machine instructions generated by instruction selection. diff --git a/include/llvm/CodeGen/IntrinsicLowering.h b/include/llvm/CodeGen/IntrinsicLowering.h index b15d505308..12b9624860 100644 --- a/include/llvm/CodeGen/IntrinsicLowering.h +++ b/include/llvm/CodeGen/IntrinsicLowering.h @@ -1,12 +1,12 @@ //===-- IntrinsicLowering.h - Intrinsic Function Lowering -------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // This file defines the IntrinsicLowering interface. This interface allows // addition of domain-specific or front-end specific intrinsics to LLVM without // having to modify all of the code generators to support the new intrinsic. @@ -38,7 +38,7 @@ namespace llvm { class CallInst; class Module; - + class IntrinsicLowering { public: virtual ~IntrinsicLowering() {} @@ -67,7 +67,7 @@ namespace llvm { /// implementation to allow for future extensibility. struct DefaultIntrinsicLowering : public IntrinsicLowering { virtual void AddPrototypes(Module &M); - virtual void LowerIntrinsicCall(CallInst *CI); + virtual void LowerIntrinsicCall(CallInst *CI); }; } diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h index 17c1e2a770..5cb9b98661 100644 --- a/include/llvm/CodeGen/LiveVariables.h +++ b/include/llvm/CodeGen/LiveVariables.h @@ -1,12 +1,12 @@ //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // This file implements the LiveVariable analysis pass. For each machine // instruction in the function, this pass calculates the set of registers that // are immediately dead after the instruction (i.e., the instruction calculates @@ -23,7 +23,7 @@ // to resolve physical register lifetimes in each basic block). If a physical // register is not register allocatable, it is not tracked. This is useful for // things like the stack pointer and condition codes. -// +// //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_LIVEVARIABLES_H @@ -111,7 +111,7 @@ public: /// killed_iterator - Iterate over registers killed by a machine instruction /// typedef std::multimap<MachineInstr*, unsigned>::iterator killed_iterator; - + /// killed_begin/end - Get access to the range of registers killed by a /// machine instruction. killed_iterator killed_begin(MachineInstr *MI) { diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index 3f781222c9..b354f71f4e 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -1,12 +1,12 @@ //===-- llvm/CodeGen/MachineBasicBlock.h ------------------------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // Collect the sequence of machine instructions for a basic block. // //===----------------------------------------------------------------------===// @@ -75,7 +75,7 @@ public: } ~MachineBasicBlock(); - + /// getBasicBlock - Return the LLVM basic block that this instance /// corresponded to originally. /// @@ -111,7 +111,7 @@ public: typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_iterator; typedef std::vector<MachineBasicBlock *>::iterator succ_iterator; typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_iterator; - + pred_iterator pred_begin() { return Predecessors.begin (); } const_pred_iterator pred_begin() const { return Predecessors.begin (); } pred_iterator pred_end() { return Predecessors.end (); } @@ -162,7 +162,7 @@ public: iterator erase(iterator I, iterator E) { return Insts.erase(I, E); } MachineInstr *remove(MachineInstr *I) { return Insts.remove(I); } void clear() { Insts.clear(); } - + /// splice - Take a block of instructions from MBB 'Other' in the range [From, /// To), and insert them into this MBB right before 'where'. void splice(iterator where, MachineBasicBlock *Other, iterator From, @@ -219,10 +219,10 @@ template <> struct GraphTraits<MachineBasicBlock *> { typedef MachineBasicBlock::succ_iterator ChildIteratorType; static NodeType *getEntryNode(MachineBasicBlock *BB) { return BB; } - static inline ChildIteratorType child_begin(NodeType *N) { + static inline ChildIteratorType child_begin(NodeType *N) { return N->succ_begin(); } - static inline ChildIteratorType child_end(NodeType *N) { + static inline ChildIteratorType child_end(NodeType *N) { return N->succ_end(); } }; @@ -232,10 +232,10 @@ template <> struct GraphTraits<const MachineBasicBlock *> { typedef MachineBasicBlock::const_succ_iterator ChildIteratorType; static NodeType *getEntryNode(const MachineBasicBlock *BB) { return BB; } - static inline ChildIteratorType child_begin(NodeType *N) { + static inline ChildIteratorType child_begin(NodeType *N) { return N->succ_begin(); } - static inline ChildIteratorType child_end(NodeType *N) { + static inline ChildIteratorType child_end(NodeType *N) { return N->succ_end(); } }; @@ -252,10 +252,10 @@ template <> struct GraphTraits<Inverse<MachineBasicBlock*> > { static NodeType *getEntryNode(Inverse<MachineBasicBlock *> G) { return G.Graph; } - static inline ChildIteratorType child_begin(NodeType *N) { + static inline ChildIteratorType child_begin(NodeType *N) { return N->pred_begin(); } - static inline ChildIteratorType child_end(NodeType *N) { + static inline ChildIteratorType child_end(NodeType *N) { return N->pred_end(); } }; @@ -264,12 +264,12 @@ template <> struct GraphTraits<Inverse<const MachineBasicBlock*> > { typedef const MachineBasicBlock NodeType; typedef MachineBasicBlock::const_pred_iterator ChildIteratorType; static NodeType *getEntryNode(Inverse<const MachineBasicBlock*> G) { - return G.Graph; + return G.Graph; } - static inline ChildIteratorType child_begin(NodeType *N) { + static inline ChildIteratorType child_begin(NodeType *N) { return N->pred_begin(); } - static inline ChildIteratorType child_end(NodeType *N) { + static inline ChildIteratorType child_end(NodeType *N) { return N->pred_end(); } }; diff --git a/include/llvm/CodeGen/MachineCodeEmitter.h b/include/llvm/CodeGen/MachineCodeEmitter.h index 562d4c695e..f3155ba7f7 100644 --- a/include/llvm/CodeGen/MachineCodeEmitter.h +++ b/include/llvm/CodeGen/MachineCodeEmitter.h @@ -1,10 +1,10 @@ //===-- llvm/CodeGen/MachineCodeEmitter.h - Code emission -------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines an abstract interface that is used by the machine code @@ -37,7 +37,7 @@ public: /// about to be code generated. /// virtual void startFunction(MachineFunction &F) {} - + /// finishFunction - This callback is invoked when the specified function has /// finished code generation. /// @@ -88,7 +88,7 @@ public: /// addRelocation - Whenever a relocatable address is needed, it should be /// noted with this interface. virtual void addRelocation(const MachineRelocation &MR) = 0; - + // getConstantPoolEntryAddress - Return the address of the 'Index' entry in // the constant pool that was last emitted with the 'emitConstantPool' method. // diff --git a/include/llvm/CodeGen/MachineConstantPool.h b/include/llvm/CodeGen/MachineConstantPool.h index edfd601faa..0e6c642e8e 100644 --- a/include/llvm/CodeGen/MachineConstantPool.h +++ b/include/llvm/CodeGen/MachineConstantPool.h @@ -1,12 +1,12 @@ //===-- CodeGen/MachineConstantPool.h - Abstract Constant Pool --*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // The MachineConstantPool class keeps track of constants referenced by a // function which must be spilled to memory. This is used for constants which // are unable to be used directly as operands to instructions, which typically diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h index 7ac582c75d..8f8a852480 100644 --- a/include/llvm/CodeGen/MachineFrameInfo.h +++ b/include/llvm/CodeGen/MachineFrameInfo.h @@ -1,12 +1,12 @@ //===-- CodeGen/MachineFrameInfo.h - Abstract Stack Frame Rep. --*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // The MachineFrameInfo class represents an abstract stack frame until // prolog/epilog code is inserted. This class is key to allowing stack frame // representation optimizations, such as frame pointer elimination. It also @@ -168,7 +168,7 @@ public: /// bool hasCalls() const { return HasCalls; } void setHasCalls(bool V) { HasCalls = V; } - + /// getMaxCallFrameSize - Return the maximum size of a call frame that must be /// allocated for an outgoing function call. This is only available if /// CallFrameSetup/Destroy pseudo instructions are used by the target, and @@ -186,7 +186,7 @@ public: Objects.insert(Objects.begin(), StackObject(Size, 1, SPOffset)); return -++NumFixedObjects; } - + /// CreateStackObject - Create a new statically sized stack object, returning /// a postive identifier to represent it. /// diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h index 1121fd0480..bc4c4c4f92 100644 --- a/include/llvm/CodeGen/MachineFunction.h +++ b/include/llvm/CodeGen/MachineFunction.h @@ -1,18 +1,18 @@ //===-- llvm/CodeGen/MachineFunction.h --------------------------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // Collect native machine code for a function. This class contains a list of // MachineBasicBlock instances that make up the current compiled function. // // This class also contains pointers to various classes which hold // target-specific information about the generated code. -// +// //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H @@ -35,19 +35,19 @@ struct ilist_traits<MachineBasicBlock> { // this is only set by the MachineFunction owning the ilist friend class MachineFunction; MachineFunction* Parent; - + public: ilist_traits<MachineBasicBlock>() : Parent(0) { } - + static MachineBasicBlock* getPrev(MachineBasicBlock* N) { return N->Prev; } static MachineBasicBlock* getNext(MachineBasicBlock* N) { return N->Next; } - + static const MachineBasicBlock* getPrev(const MachineBasicBlock* N) { return N->Prev; } - + static const MachineBasicBlock* getNext(const MachineBasicBlock* N) { return N->Next; } - + static void setPrev(MachineBasicBlock* N, MachineBasicBlock* prev) { N->Prev = prev; } @@ -179,7 +179,7 @@ public: /// is an error to add the same register to the same set more than once. void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } - + // Iteration support for live in/out sets. These sets are kept in sorted // order by their register number. typedef std::vector<unsigned>::const_iterator liveinout_iterator; @@ -219,7 +219,7 @@ public: /// in your path. /// void viewCFG() const; - + /// viewCFGOnly - This function is meant for use from the debugger. It works /// just like viewCFG, but it does not include the contents of basic blocks /// into the nodes, just the label. If you are only interested in the CFG @@ -256,7 +256,7 @@ public: // Provide accessors for basic blocks... const BasicBlockListType &getBasicBlockList() const { return BasicBlocks; } BasicBlockListType &getBasicBlockList() { return BasicBlocks; } - + //===--------------------------------------------------------------------===// // BasicBlock iterator forwarding functions // @@ -331,7 +331,7 @@ template <> struct GraphTraits<const MachineFunction*> : }; -// Provide specializations of GraphTraits to be able to treat a function as a +// Provide specializations of GraphTraits to be able to treat a function as a // graph of basic blocks... and to walk it in inverse order. Inverse order for // a function is considered to be when traversing the predecessor edges of a BB // instead of the successor edges. diff --git a/include/llvm/CodeGen/MachineFunctionPass.h b/include/llvm/CodeGen/MachineFunctionPass.h index 390dcb8562..973babd702 100644 --- a/include/llvm/CodeGen/MachineFunctionPass.h +++ b/include/llvm/CodeGen/MachineFunctionPass.h @@ -1,10 +1,10 @@ //===-- MachineFunctionPass.h - Pass for MachineFunctions --------*-C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the MachineFunctionPass class. MachineFunctionPass's are diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 6a6d380fef..ea2233f8d2 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -1,10 +1,10 @@ //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file contains the declaration of the MachineInstr class, which is the @@ -35,8 +35,8 @@ template <typename T> struct ilist; typedef short MachineOpCode; //===----------------------------------------------------------------------===// -// class MachineOperand -// +// class MachineOperand +// // Purpose: // Representation of each machine instruction operand. // This class is designed so that you can allocate a vector of operands @@ -45,10 +45,10 @@ typedef short MachineOpCode; // E.g, for this VM instruction: // ptr = alloca type, numElements // we generate 2 machine instructions on the SPARC: -// +// // mul Constant, Numelements -> Reg // add %sp, Reg -> Ptr -// +// // Each instruction has 3 operands, listed above. Of those: // - Reg, NumElements, and Ptr are of operand type MO_Register. // - Constant is of operand type MO_SignExtendedImmed on the SPARC. @@ -57,16 +57,16 @@ typedef short MachineOpCode; // // - Reg will be of virtual register type MO_MInstrVirtualReg. The field // MachineInstr* minstr will point to the instruction that computes reg. -// +// // - %sp will be of virtual register type MO_MachineReg. // The field regNum identifies the machine register. -// +// // - NumElements will be of virtual register type MO_VirtualReg. // The field Value* value identifies the value. -// +// // - Ptr will also be of virtual register type MO_VirtualReg. // Again, the field Value* value identifies the value. -// +// //===----------------------------------------------------------------------===// struct MachineOperand { @@ -108,14 +108,14 @@ public: MO_ExternalSymbol, // Name of external global symbol MO_GlobalAddress, // Address of a global value }; - + private: union { Value* value; // BasicBlockVal for a label operand. // ConstantVal for a non-address immediate. // Virtual register for an SSA operand, // including hidden operands required for - // the generated machine code. + // the generated machine code. // LLVM global for MO_GlobalAddress. int64_t immedVal; // Constant value for an explicit constant @@ -134,7 +134,7 @@ private: // valid for MO_GlobalAddress and MO_ExternalSym } extra; - void zeroContents () { + void zeroContents () { memset (&contents, 0, sizeof (contents)); memset (&extra, 0, sizeof (extra)); } @@ -193,9 +193,9 @@ public: extra = M.extra; } - + ~MachineOperand() {} - + const MachineOperand &operator=(const MachineOperand &MO) { contents = MO.contents; flags = MO.flags; @@ -205,7 +205,7 @@ public: } /// getType - Returns the MachineOperandType for this operand. - /// + /// MachineOperandType getType() const { return opType; } /// getUseType - Returns the MachineOperandUseType of this operand. @@ -245,7 +245,7 @@ public: /// has one. This is deprecated and only used by the SPARC v9 backend. /// Value* getVRegValueOrNull() const { - return (opType == MO_VirtualRegister || opType == MO_CCRegister || + return (opType == MO_VirtualRegister || opType == MO_CCRegister || isPCRelativeDisp()) ? contents.value : NULL; } @@ -312,7 +312,7 @@ public: /// bool hasAllocatedReg() const { return (extra.regNum >= 0 && - (opType == MO_VirtualRegister || opType == MO_CCRegister || + (opType == MO_VirtualRegister || opType == MO_CCRegister || opType == MO_MachineRegister)); } @@ -331,13 +331,13 @@ public: // code.' It's not clear where the duplication is. assert(hasAllocatedReg() && "This operand cannot have a register number!"); extra.regNum = Reg; - } + } void setValueReg(Value *val) { assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*"); contents.value = val; } - + void setImmedValue(int immVal) { assert(isImmediate() && "Wrong MachineOperand mutator"); contents.immedVal = immVal; @@ -358,35 +358,35 @@ public: void markLo32() { flags |= LOFLAG32; } void markHi64() { flags |= HIFLAG64; } void markLo64() { flags |= LOFLAG64; } - + private: /// setRegForValue - Replaces the Value with its corresponding physical /// register after register allocation is complete. This is deprecated /// and only used by the SPARC v9 back-end. /// void setRegForValue(int reg) { - assert(opType == MO_VirtualRegister || opType == MO_CCRegister || + assert(opType == MO_VirtualRegister || opType == MO_CCRegister || opType == MO_MachineRegister); extra.regNum = reg; } - + friend class MachineInstr; }; //===----------------------------------------------------------------------===// -// class MachineInstr -// +// class MachineInstr +// // Purpose: // Representation of each machine instruction. -// +// // MachineOpCode must be an enum, defined separately for each target. // E.g., It is defined in SparcInstructionSelection.h for the SPARC. -// +// // There are 2 kinds of operands: -// -// (1) Explicit operands of the machine instruction in vector operands[] -// +// +// (1) Explicit operands of the machine instruction in vector operands[] +// // (2) "Implicit operands" are values implicitly used or defined by the // machine instruction, such as arguments to a CALL, return value of // a CALL (if any), and return value of a RETURN. @@ -426,7 +426,7 @@ public: /// block. /// MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps); - + ~MachineInstr(); const MachineBasicBlock* getParent() const { return parent; } @@ -439,7 +439,7 @@ public: /// Access to explicit operands of the instruction. /// unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } - + const MachineOperand& getOperand(unsigned i) const { assert(i < getNumOperands() && "getOperand() out of range!"); return operands[i]; @@ -454,7 +454,7 @@ public: // This returns the i'th entry in the operand vector. // That represents the i'th explicit operand or the (i-N)'th implicit operand, // depending on whether i < N or i >= N. - // + // const MachineOperand& getExplOrImplOperand(unsigned i) const { assert(i < operands.size() && "getExplOrImplOperand() out of range!"); return (i < getNumOperands()? getOperand(i) @@ -463,9 +463,9 @@ public: // // Access to implicit operands of the instruction - // + // unsigned getNumImplicitRefs() const{ return numImplicitRefs; } - + MachineOperand& getImplicitOp(unsigned i) { assert(i < numImplicitRefs && "implicit ref# out of range!"); return operands[i + operands.size() - numImplicitRefs]; @@ -672,7 +672,7 @@ public: /// replace - Support to rewrite a machine instruction in place: for now, /// simply replace() and then set new operands with Set.*Operand methods /// below. - /// + /// void replace(short Opcode, unsigned numOperands); /// setOpcode - Replace the opcode of the current instruction with a new one. @@ -687,7 +687,7 @@ public: } // Access to set the operands when building the machine instruction - // + // void SetMachineOperandVal(unsigned i, MachineOperand::MachineOperandType operandType, Value* V); @@ -702,22 +702,22 @@ public: unsigned substituteValue(const Value* oldVal, Value* newVal, bool defsOnly, bool notDefsAndUses, bool& someArgsWereIgnored); - + // SetRegForOperand - // SetRegForImplicitRef - // Mark an explicit or implicit operand with its allocated physical register. - // + // void SetRegForOperand(unsigned i, int regNum); void SetRegForImplicitRef(unsigned i, int regNum); // // Iterator to enumerate machine operands. - // + // template<class MITy, class VTy> class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { unsigned i; MITy MI; - + void skipToNextVal() { while (i < MI->getNumOperands() && !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || @@ -725,14 +725,14 @@ public: && MI->getOperand(i).getVRegValue() != 0)) ++i; } - + inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { skipToNextVal(); } - + public: typedef ValOpIterator<MITy, VTy> _Self; - + inline VTy operator*() const { return MI->getOperand(i).getVRegValue(); } @@ -742,16 +742,16 @@ public: inline VTy operator->() const { return operator*(); } - inline bool isUse() const { return MI->getOperand(i).isUse(); } - inline bool isDef() const { return MI->getOperand(i).isDef(); } + inline bool isUse() const { return MI->getOperand(i).isUse(); } + inline bool isDef() const { return MI->getOperand(i).isDef(); } inline _Self& operator++() { i++; skipToNextVal(); return *this; } inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } - inline bool operator==(const _Self &y) const { + inline bool operator==(const _Self &y) const { return i == y.i; } - inline bool operator!=(const _Self &y) const { + inline bool operator!=(const _Self &y) const { return !operator==(y); } diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 060f90c53f..2aee02ee6c 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -1,10 +1,10 @@ //===-- CodeGen/MachineInstBuilder.h - Simplify creation of MIs -*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file exposes a function named BuildMI, which is useful for dramatically @@ -86,7 +86,7 @@ public: MI->addMachineRegOperand(Reg, Ty); return *this; } - + /// addImm - Add a new immediate operand. /// const MachineInstrBuilder &addImm(int Val) const { diff --git a/include/llvm/CodeGen/MachineRelocation.h b/include/llvm/CodeGen/MachineRelocation.h index a72f29dd0f..93d2527ab6 100644 --- a/include/llvm/CodeGen/MachineRelocation.h +++ b/include/llvm/CodeGen/MachineRelocation.h @@ -1,10 +1,10 @@ //===-- llvm/CodeGen/MachineRelocation.h - Target Relocation ----*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the MachineRelocation class. diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 866d07ff43..a053dd95a6 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -1,10 +1,10 @@ //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines interfaces to access the target independent code generation @@ -31,7 +31,7 @@ namespace llvm { /// last LLVM modifying pass to clean up blocks that are not reachable from /// the entry block. FunctionPass *createUnreachableBlockEliminationPass(); - + /// MachineFunctionPrinter pass - This pass prints out the machine function to /// standard error, as a debugging tool. FunctionPass *createMachineFunctionPrinterPass(std::ostream *OS, @@ -62,9 +62,9 @@ namespace llvm { /// LocalRegisterAllocation Pass - This pass register allocates the input code /// a basic block at a time, yielding code better than the simple register /// allocator, but not as good as a global allocator. - /// + /// FunctionPass *createLocalRegisterAllocator(); - + /// LinearScanRegisterAllocation Pass - This pass implements the linear scan /// register allocation algorithm, a global register allocator. /// @@ -90,7 +90,7 @@ namespace llvm { /// the current function, which should happen after the function has been /// emitted to a .s file or to memory. FunctionPass *createMachineCodeDeleter(); - + /// getRegisterAllocator - This creates an instance of the register allocator /// for the Sparc. FunctionPass *getRegisterAllocator(TargetMachine &T); diff --git a/include/llvm/CodeGen/SchedGraphCommon.h b/include/llvm/CodeGen/SchedGraphCommon.h index 167bfb0f2d..7560690230 100644 --- a/include/llvm/CodeGen/SchedGraphCommon.h +++ b/include/llvm/CodeGen/SchedGraphCommon.h @@ -1,10 +1,10 @@ //===-- SchedGraphCommon.h - Scheduling Base Graph --------------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // A common graph class that is based on the SSA graph. It includes @@ -47,7 +47,7 @@ public: typedef std::vector<SchedGraphEdge*>::const_iterator const_iterator; typedef std::vector<SchedGraphEdge*>::reverse_iterator reverse_iterator; typedef std::vector<SchedGraphEdge*>::const_reverse_iterator const_reverse_iterator; - + // Accessor methods unsigned getNodeId() const { return ID; } int getLatency() const { return latency; } @@ -60,7 +60,7 @@ public: iterator endInEdges() { return inEdges.end(); } iterator beginOutEdges() { return outEdges.begin(); } iterator endOutEdges() { return outEdges.end(); } - + const_iterator beginInEdges() const { return inEdges.begin(); } const_iterator endInEdges() const { return inEdges.end(); } const_iterator beginOutEdges() const { return outEdges.begin(); } @@ -70,29 +70,29 @@ public: // Debugging support virtual void print(std::ostream &os) const = 0; - + protected: friend class SchedGraphCommon; friend class SchedGraphEdge; // give access for adding edges - - + + // disable default constructor and provide a ctor for single-block graphs SchedGraphNodeCommon(); // DO NOT IMPLEMENT - + inline SchedGraphNodeCommon(unsigned Id, int index, int late=0) : ID(Id), latency(late), origIndexInBB(index) {} - + virtual ~SchedGraphNodeCommon(); - + //Functions to add and remove edges inline void addInEdge(SchedGraphEdge* edge) { inEdges.push_back(edge); } inline void addOutEdge(SchedGraphEdge* edge) { outEdges.push_back(edge); } void removeInEdge(const SchedGraphEdge* edge); void removeOutEdge(const SchedGraphEdge* edge); - + }; // ostream << operator for SchedGraphNode class -inline std::ostream &operator<<(std::ostream &os, +inline std::ostream &operator<<(std::ostream &os, const SchedGraphNodeCommon &node) { node.print(os); return os; @@ -112,7 +112,7 @@ public: enum DataDepOrderType { TrueDep = 0x1, AntiDep=0x2, OutputDep=0x4, NonDataDep=0x8 }; - + protected: SchedGraphNodeCommon* src; SchedGraphNodeCommon* sink; @@ -120,7 +120,7 @@ protected: unsigned int depOrderType; int minDelay; // cached latency (assumes fixed target arch) int iteDiff; - + union { const Value* val; int machineRegNum; @@ -130,30 +130,30 @@ protected: public: // For all constructors, if minDelay is unspecified, minDelay is // set to _src->getLatency(). - + // constructor for CtrlDep or MemoryDep edges, selected by 3rd argument SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink, SchedGraphEdgeDepType _depType, unsigned int _depOrderType, int _minDelay = -1); - + // constructor for explicit value dependence (may be true/anti/output) SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink, const Value* _val, unsigned int _depOrderType, int _minDelay = -1); - + // constructor for machine register dependence SchedGraphEdge(SchedGraphNodeCommon* _src,SchedGraphNodeCommon* _sink, unsigned int _regNum, unsigned int _depOrderType, int _minDelay = -1); - + // constructor for any other machine resource dependences. // DataDepOrderType is always NonDataDep. It it not an argument to // avoid overloading ambiguity with previous constructor. SchedGraphEdge(SchedGraphNodeCommon* _src, SchedGraphNodeCommon* _sink, ResourceId _resourceId, int _minDelay = -1); - + ~SchedGraphEdge() {} - + SchedGraphNodeCommon* getSrc() const { return src; } SchedGraphNodeCommon* getSink() const { return sink; } int getMinDelay() const { return minDelay; } @@ -179,12 +179,12 @@ public: int getIteDiff() { return iteDiff; } - + public: // Debugging support void print(std::ostream &os) const; void dump(int indent=0) const; - + private: // disable default ctor SchedGraphEdge(); // DO NOT IMPLEMENT @@ -197,7 +197,7 @@ inline std::ostream &operator<<(std::ostream &os, const SchedGraphEdge &edge) { } class SchedGraphCommon { - + protected: SchedGraphNodeCommon* graphRoot; // the root and leaf are not inserted SchedGraphNodeCommon* graphLeaf; // in the hash_map (see getNumNodes()) @@ -207,16 +207,16 @@ public: // Accessor methods // SchedGraphNodeCommon* getRoot() const { return graphRoot; } - SchedGraphNodeCommon* getLeaf() const { return graphLeaf; } - + SchedGraphNodeCommon* getLeaf() const { return graphLeaf; } + // // Delete nodes or edges from the graph. - // + // void eraseNode(SchedGraphNodeCommon* node); void eraseIncomingEdges(SchedGraphNodeCommon* node, bool addDummyEdges = true); void eraseOutgoingEdges(SchedGraphNodeCommon* node, bool addDummyEdges = true); void eraseIncidentEdges(SchedGraphNodeCommon* node, bool addDummyEdges = true); - + SchedGraphCommon() {} ~SchedGraphCommon(); }; @@ -227,30 +227,30 @@ public: // Ok to make it a template because it shd get instantiated at most twice: // for <SchedGraphNode, SchedGraphNode::iterator> and // for <const SchedGraphNode, SchedGraphNode::const_iterator>. -// +// template <class _NodeType, class _EdgeType, class _EdgeIter> class SGPredIterator: public bidirectional_iterator<_NodeType, ptrdiff_t> { protected: _EdgeIter oi; public: typedef SGPredIterator<_NodeType, _EdgeType, _EdgeIter> _Self; - + inline SGPredIterator(_EdgeIter startEdge) : oi(startEdge) {} - + inline bool operator==(const _Self& x) const { return oi == x.oi; } inline bool operator!=(const _Self& x) const { return !operator==(x); } - + // operator*() differs for pred or succ iterator inline _NodeType* operator*() const { return (_NodeType*)(*oi)->getSrc(); } inline _NodeType* operator->() const { return operator*(); } - + inline _EdgeType* getEdge() const { return *(oi); } - + inline _Self &operator++() { ++oi; return *this; } // Preincrement inline _Self operator++(int) { // Postincrement - _Self tmp(*this); ++*this; return tmp; + _Self tmp(*this); ++*this; return tmp; } - + inline _Self &operator--() { --oi; return *this; } // Predecrement inline _Self operator--(int) { // Postdecrement _Self tmp = *this; --*this; return tmp; @@ -263,22 +263,22 @@ protected: _EdgeIter oi; public: typedef SGSuccIterator<_NodeType, _EdgeType, _EdgeIter> _Self; - + inline SGSuccIterator(_EdgeIter startEdge) : oi(startEdge) {} - + inline bool operator==(const _Self& x) const { return oi == x.oi; } inline bool operator!=(const _Self& x) const { return !operator==(x); } - + inline _NodeType* operator*() const { return (_NodeType*)(*oi)->getSink(); } inline _NodeType* operator->() const { return operator*(); } - + inline _EdgeType* getEdge() const { return *(oi); } - + inline _Self &operator++() { ++oi; return *this; } // Preincrement inline _Self operator++(int) { // Postincrement - _Self tmp(*this); ++*this; return tmp; + _Self tmp(*this); ++*this; return tmp; } - + inline _Self &operator--() { --oi; return *this; } // Predecrement inline _Self operator--(int) { // Postdecrement _Self tmp = *this; --*this; return tmp; diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 9ae69c256b..39d4ef4ffc 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -1,15 +1,15 @@ //===-- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ---------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // This file declares the SelectionDAG class, and transitively defines the // SDNode class and subclasses. -// +// //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_SELECTIONDAG_H @@ -62,7 +62,7 @@ public: typedef std::vector<SDNode*>::const_iterator allnodes_iterator; allnodes_iterator allnodes_begin() const { return AllNodes.begin(); } allnodes_iterator allnodes_end() const { return AllNodes.end(); } - + /// getRoot - Return the root tag of the SelectionDAG. /// const SDOperand &getRoot() const { return Root; } diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 93672f97db..ee028a6876 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -1,10 +1,10 @@ //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file implements the SelectionDAGISel class, which is used as the common @@ -49,13 +49,13 @@ public: unsigned MakeReg(MVT::ValueType VT); virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0; - + private: SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg); void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF, FunctionLoweringInfo &FuncInfo); - + void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, FunctionLoweringInfo &FuncInfo); diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index d605961bb4..35993d986a 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1,12 +1,12 @@ //===-- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ---*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// -// +// // This file declares the SDNode class and derived classes, which are used to // represent the nodes and operations present in a SelectionDAG. These nodes // and operations are machine code level operations, with some similarities to @@ -51,7 +51,7 @@ namespace ISD { // single token result. This is used to represent the fact that the operand // operators are independent of each other. TokenFactor, - + // Various leaf nodes. Constant, ConstantFP, GlobalAddress, FrameIndex, ConstantPool, BasicBlock, ExternalSymbol, @@ -185,7 +185,7 @@ namespace ISD { // integer result type. // ZEXTLOAD loads the integer operand and zero extends it to a larger // integer result type. - // EXTLOAD is used for two things: floating point extending loads, and + // EXTLOAD is used for two things: floating point extending loads, and // integer extending loads where it doesn't matter what the high // bits are set to. The code generator is allowed to codegen this // into whichever operation is more efficient. @@ -205,7 +205,7 @@ namespace ISD { DYNAMIC_STACKALLOC, // Control flow instructions. These all have token chains. - + // BR - Unconditional branch. The first operand is the chain // operand, the second is the MBB to branch to. BR, @@ -240,7 +240,7 @@ namespace ISD { MEMSET, MEMMOVE, MEMCPY, - + // ADJCALLSTACKDOWN/ADJCALLSTACKUP - These operators mark the beginning and // end of a call sequence and indicate how much the stack pointer needs to // be adjusted for that particular call. The first operand is a chain, the @@ -284,7 +284,7 @@ namespace ISD { SETUGT, // 1 0 1 0 True if unordered or greater than SETUGE, // 1 0 1 1 True if unordered, greater than, or equal SETULT, // 1 1 0 0 True if unordered or less than - SETULE, // 1 1 0 1 True if unordered, less than, or equal + SETULE, // 1 1 0 1 True if unordered, less than, or equal SETUNE, // 1 1 1 0 True if unordered or not equal SETTRUE, // 1 1 1 1 Always true (always folded) // Don't care operations: undefined if the input is a nan. @@ -293,7 +293,7 @@ namespace ISD { SETGT, // 1 X 0 1 0 True if greater than SETGE, // 1 X 0 1 1 True if greater than or equal SETLT, // 1 X 1 0 0 True if less than - SETLE, // 1 X 1 0 1 True if less than or equal + SETLE, // 1 X 1 0 1 True if less than or equal SETNE, // 1 X 1 1 0 True if not equal SETTRUE2, // 1 X 1 1 1 Always true (always folded) @@ -385,7 +385,7 @@ public: /// getValueType - Return the ValueType of the referenced return value. /// inline MVT::ValueType getValueType() const; - + // Forwarding methods - These forward to the corresponding methods in SDNode. inline unsigned getOpcode() const; inline unsigned getNodeDepth() const; @@ -806,11 +806,11 @@ public: static bool classof(const MVTSDNode *) { return true; } static bool classof(const SDNode *N) { - return + return N->getOpcode() == ISD::SIGN_EXTEND_INREG || N->getOpcode() == ISD::FP_ROUND_INREG || N->getOpcode() == ISD::EXTLOAD || - N->getOpcode() == ISD::SEXTLOAD || + N->getOpcode() == ISD::SEXTLOAD || N->getOpcode() == ISD::ZEXTLOAD || N->getOpcode() == ISD::TRUNCSTORE; } @@ -819,7 +819,7 @@ public: class SDNodeIterator : public forward_iterator<SDNode, ptrdiff_t> { SDNode *Node; unsigned Operand; - + SDNodeIterator(SDNode *N, unsigned Op) : Node(N), Operand(Op) {} public: bool operator==(const SDNodeIterator& x) const { @@ -832,18 +832,18 @@ public: Operand = I.Operand; return *this; } - + pointer operator*() const { return Node->getOperand(Operand).Val; } pointer operator->() const { return operator*(); } - + SDNodeIterator& operator++() { // Preincrement ++Operand; return *this; } SDNodeIterator operator++(int) { // Postincrement - SDNodeIterator tmp = *this; ++*this; return tmp; + SDNodeIterator tmp = *this; ++*this; return tmp; } static SDNodeIterator begin(SDNode *N) { return SDNodeIterator(N, 0); } @@ -859,10 +859,10 @@ template <> struct GraphTraits<SDNode*> { typedef SDNode NodeType; typedef SDNodeIterator ChildIteratorType; static inline NodeType *getEntryNode(SDNode *N) { return N; } - static inline ChildIteratorType child_begin(NodeType *N) { + static inline ChildIteratorType child_begin(NodeType *N) { return SDNodeIterator::begin(N); } - static inline ChildIteratorType child_end(NodeType *N) { + static inline ChildIteratorType child_end(NodeType *N) { return SDNodeIterator::end(N); } }; diff --git a/include/llvm/CodeGen/ValueSet.h b/include/llvm/CodeGen/ValueSet.h index f4bc6e80d4..558e7489d1 100644 --- a/include/llvm/CodeGen/ValueSet.h +++ b/include/llvm/CodeGen/ValueSet.h @@ -1,10 +1,10 @@ //===-- llvm/CodeGen/ValueSet.h ---------------------------------*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This header is OBSOLETE, do not use it for new code. @@ -22,7 +22,7 @@ namespace llvm { class Value; -// RAV - Used to print values in a form used by the register allocator. +// RAV - Used to print values in a form used by the register allocator. // struct RAV { // Register Allocator Value const Value &V; diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index ce6cb0764f..7efad1103c 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -1,10 +1,10 @@ //===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the set of low-level target independent types which various |