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author | Dmitri Gribenko <gribozavr@gmail.com> | 2012-09-12 16:59:47 +0000 |
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committer | Dmitri Gribenko <gribozavr@gmail.com> | 2012-09-12 16:59:47 +0000 |
commit | 67c8978617c3bce9d07210f93f6c64c715f77695 (patch) | |
tree | 474ba0af41beb3d595bc350bec57754103e3661f /lib | |
parent | ba9d069d797fbe204470c18a5f15e7f3cf763e0b (diff) | |
download | external_llvm-67c8978617c3bce9d07210f93f6c64c715f77695.tar.gz external_llvm-67c8978617c3bce9d07210f93f6c64c715f77695.tar.bz2 external_llvm-67c8978617c3bce9d07210f93f6c64c715f77695.zip |
Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 2 | ||||
-rw-r--r-- | lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index c021a937b6..20ba804446 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -508,7 +508,7 @@ bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, /// /// @param VirtReg Live range that is about to be assigned. /// @param PhysReg Desired register for assignment. -/// @prarm IsHint True when PhysReg is VirtReg's preferred register. +/// @param IsHint True when PhysReg is VirtReg's preferred register. /// @param MaxCost Only look for cheaper candidates and update with new cost /// when returning true. /// @returns True when interference can be evicted cheaper than MaxCost. diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 18961fdd78..ab80e45754 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -217,7 +217,7 @@ public: /// /// \param Inst - The instruction to relax, which may be the same /// as the output. - /// \parm Res [output] - On return, the relaxed instruction. + /// \param [out] Res On return, the relaxed instruction. void relaxInstruction(const MCInst &Inst, MCInst &Res) const { } |