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| author | JF Bastien <jfb@google.com> | 2013-05-29 15:45:47 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-05-29 15:45:47 +0000 |
| commit | a9a8a128f807d46ce46971abf65578996c50cf2e (patch) | |
| tree | e495c401c8d2f6d7d7ca6f498c3f217dbd3e19fa /lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | |
| parent | d1c180e0305c5bedb2b4259c1d841e944d043880 (diff) | |
| download | external_llvm-a9a8a128f807d46ce46971abf65578996c50cf2e.tar.gz external_llvm-a9a8a128f807d46ce46971abf65578996c50cf2e.tar.bz2 external_llvm-a9a8a128f807d46ce46971abf65578996c50cf2e.zip | |
Tidy some register classes for ARM and Thumb
Tidy up three places where the register class for ARM and Thumb wasn't
restrictive enough:
- No PC dest for reg-reg add/orr/sub.
- No PC dest for shifts.
- No PC or SP for Thumb2 reg-imm add.
I encountered this while combining FastISel with
-verify-machineinstrs. These instructions defined registers whose
classes weren't restrictive enough, and the uses failed
verification. They're also undefined in the ISA, or would produce code
that FastISel wouldn't want. This doesn't fix the register class
narrowing issue (where uses should restrict definitions), and isn't
thorough, but it's a small step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182863 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp')
0 files changed, 0 insertions, 0 deletions