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32-bit virtual register can be in 64-bit solo register.
So we should not compute the size of virtual register
basing on size of phyical register.
Change-Id: I4e11be13df8469be63808d0ce9d1ca6f80bef483
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
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This patch fixes to always increment the index for a wide argument,
and fixes the index upper bound.
Otherwise, the mapping may be incorrect.
Change-Id: I0116d8fd0a0a5c1270a23129c73a9e3651132977
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
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This patch shows our efforts on resolving the ART limitations:
- passing "float"/"double" arguments via FPR
- passing "long" arguments via single GPR, not pair
- passing more than 3 agruments via GPR.
Work done:
- Extended SpecialTargetRegister enum with kARG4, kARG5, fARG4..fARG7.
- Created initial LoadArgRegs/GenDalvikX/FlushIns version in X86Mir2Lir.
- Unlimited number of long/double/float arguments support
- Refactored (v2)
Change-Id: I5deadd320b4341d5b2f50ba6fa4a98031abc3902
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
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