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* ART: Implement X86 hard float (Quick/JNI/Baseline)Mark Mendell2015-01-231-3/+8
| | | | | | | | | | | | | | | | | Use XMM0-XMM3 as parameter registers for float/double on X86. X86_64 already uses XMM0-XMM7 for parameters. Change the 'hidden' argument register from XMM0 to XMM7 to avoid a conflict. Add support for FPR save/restore in runtime/arch/x86. Minimal support for Optimizing baseline compiler. Bump the version in runtime/oat.h because this is an ABI change. Change-Id: Ia6fe150e8488b9e582b0178c0dda65fc81d5a8ba Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Support callee save floating point registers on x64.Nicolas Geoffray2015-01-231-2/+0
| | | | | | | | | - Share the computation of core_spill_mask and fpu_spill_mask between backends. - Remove explicit stack overflow check support: we need to adjust them and since they are not tested, they will easily bitrot. Change-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a
* Enable core callee-save on x64.Nicolas Geoffray2015-01-211-1/+1
| | | | | | Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
* [optimizing compiler] Implement inline x86 FP '%'Mark Mendell2015-01-211-0/+3
| | | | | | | | | | | | | | Replace the calls to fmod/fmodf by inline code as is done in the Quick compiler. Remove the quick fmod/fmodf runtime entries, as they are no longer in use. 64 bit code generator Move() routine needed to be enhanced to handle constants, as Location::Any() allows them to be generated. Change-Id: I6b6a42f6faeed4b0b3c940453e487daf5b25d184 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Add implicit null checks for the optimizing compilerCalin Juravle2015-01-161-1/+5
| | | | | | | | | - for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
* [optimizing compiler] Compute live spill sizeMark Mendell2015-01-151-0/+5
| | | | | | | | | | | | | | | | | The current stack frame calculation assumes that each live register to be saved/restored has the word size of the machine. This fails for X86, where a double in an XMM register takes up 8 bytes. Change the calculation to keep track of the number of core registers and number of fp registers to handle this distinction. This is slightly pessimal, as the registers may not be active at the same time, but the only way to handle this would be to allocate both classes of registers simultaneously, or remember all the active intervals, matching them up and compute the size of each safepoint interval. Change-Id: If7860aa319b625c214775347728cdf49a56946eb Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Implement double and float support for arm in register allocator.Nicolas Geoffray2015-01-081-0/+4
| | | | | | | | | | | | The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
* [optimizing compiler] Add support for volatileCalin Juravle2014-12-191-0/+6
| | | | | | | | | | | | - for backends: arm, x86, x86_64 - added necessary instructions to assemblies - clean up code gen for field set/get - fixed InstructionDataEquals for some instructions - fixed comments in compiler_enums * 003-opcode test verifies basic volatile functionality Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
* [optimizing compiler] Add shiftsCalin Juravle2014-11-241-0/+5
| | | | | | Added SHL, SHR, USHR for arm, x86, x86_64. Change-Id: I971f594e270179457e6958acf1401ff7630df07e
* Consistently use k{InstructionSet}WordSize.Nicolas Geoffray2014-11-191-1/+2
| | | | | | | | These constants were defined prior to k{InstructionSet}PointerSize. So use them consistently in optimizing as a first step. We can discuss whether we should remove them in a second step. Change-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6
* [optimizing compiler] Add REM_INT, REM_LONGCalin Juravle2014-11-171-0/+1
| | | | | | | - for arm, x86, x86_64 - minor cleanup/fix in div tests Change-Id: I240874010206a5a9b3aaffbc81a885b94c248f93
* Merge "Do a parallel move in BoundsCheckSlowPath."Nicolas Geoffray2014-11-131-1/+1
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| * Do a parallel move in BoundsCheckSlowPath.Nicolas Geoffray2014-11-121-1/+1
| | | | | | | | | | | | | | | | The two locations of the index and length could overlap, so we need a parallel move. Also factorize the code for doing a parallel move based on two locations. Change-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4
* | Implement and/or/xor in optimizing.Nicolas Geoffray2014-11-121-1/+3
|/ | | | Change-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec
* Implement try/catch/throw in optimizing.Nicolas Geoffray2014-11-061-24/+28
| | | | | | | | - We currently don't run optimizations in the presence of a try/catch. - We therefore implement Quick's mapping table. - Also fix a missing null check on array-length. Change-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f
* Implement CONST_CLASS in optimizing compiler.Nicolas Geoffray2014-11-041-0/+2
| | | | Change-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd
* Add support for static fields in optimizing compiler.Nicolas Geoffray2014-10-291-2/+2
| | | | Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
* Implement register allocator for floating point registers.Nicolas Geoffray2014-10-211-2/+2
| | | | | | | | Also: - Fix misuses of emitting the rex prefix in the x86_64 assembler. - Fix movaps code generation in the x86_64 assembler. Change-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe
* Add multiplication for integral typesCalin Juravle2014-10-171-0/+4
| | | | | | | This also fixes an issue where we could allocate a pair register even if one of its parts was already blocked. Change-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01
* Don't use assembler classes in code_generator.h.Nicolas Geoffray2014-10-161-1/+11
| | | | | | | | | The arm64 backend uses its own assembler and does not share the same classes as the other backends. To avoid conflicts or unnecessary mappings, just don't use those classes in the shared part of the code generator. Change-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d
* Cleanup baseline register allocator.Nicolas Geoffray2014-10-101-12/+2
| | | | | | | | - Use three arrays for blocking regsters instead of one and computing offsets in that array.] - Don't pass blocked_registers_ to methods, just use the field. Change-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6
* Fix code generation of materialized conditions.Nicolas Geoffray2014-10-091-2/+2
| | | | | | | | | | | | | Move the logic for knowing if a condition needs to be materialized in an optimization pass (so that the information does not change as a side effect of another optimization). Also clean-up arm and x86_64 codegen: - arm: ldr and str are for power-users when a constant is in play. We should use LoadFromOffset and StoreToOffset. - x86_64: fix misuses of movq instead of movl. Change-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3
* Stop converting from Location to ManagedRegister.Nicolas Geoffray2014-10-091-1/+1
| | | | | | | Now the source of truth is the Location object that knows which register (core, pair, fpu) it needs to refer to. Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
* Add support for floats and doubles.Nicolas Geoffray2014-10-071-3/+8
| | | | | | | - Follows Quick conventions. - Currently only works with baseline register allocator. Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
* Optimize suspend checks in optimizing compiler.Nicolas Geoffray2014-09-251-0/+5
| | | | | | | | | | - Remove the ones added during graph build (they were added for the baseline code generator). - Emit them at loop back edges after phi moves, so that the test can directly jump to the loop header. - Fix x86 and x86_64 suspend check by using cmpw instead of cmpl. Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
* Support for saving and restoring live registers in a slow path.Nicolas Geoffray2014-09-231-0/+2
| | | | | | And use it in suspend check slow paths. Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
* Implement invoke virtual in optimizing compiler.Nicolas Geoffray2014-09-171-0/+2
| | | | | | | Also refactor 004 tests to make them work with both Quick and Optimizing. Change-Id: I87e275cb0ae0258fc3bb32b612140000b1d2adf8
* Implement array get and array put in optimizing.Nicolas Geoffray2014-07-281-1/+4
| | | | | | Also fix a couple of assembler/disassembler issues. Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
* Stack overflow checks and NPE checks for optimizing.Nicolas Geoffray2014-07-221-1/+1
| | | | Change-Id: I59e97448bf29778769b79b51ee4ea43f43493d96
* Add assembly operations with constants in optimizing compiler.Nicolas Geoffray2014-07-211-2/+2
| | | | Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
* Fix a braino in the stack layout.Nicolas Geoffray2014-07-151-3/+2
| | | | | | Also do some refactoring to have this code be just in CodeGenerator. Change-Id: I88de109889138af8d60027973c12a64bee813cb7
* Support fields in optimizing compiler.Nicolas Geoffray2014-07-141-0/+1
| | | | | | | | - Required support for temporaries, to be only used by baseline compiler. - Also fixed a few invalid assumptions around locations and instructions that don't need materialization. These instructions should not have an Out. Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
* Support longs in the register allocator for x86_64.Nicolas Geoffray2014-07-021-0/+4
| | | | Change-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867
* Final CL to enable register allocation on x86.Nicolas Geoffray2014-06-121-0/+29
| | | | | | | | | | | | This CL implements: 1) Resolution after allocation: connecting the locations allocated to an interval within a block and between blocks. 2) Handling of fixed registers: some instructions require inputs/output to be at a specific location, and the allocator needs to deal with them in a special way. 3) ParallelMoveResolver::EmitNativeCode for x86. Change-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858
* Add a linear scan register allocator to the optimizing compiler.Nicolas Geoffray2014-05-261-0/+11
| | | | | | | | | | | | This is a "by-the-book" implementation. It currently only deals with allocating registers, with no hint optimizations. The changes remaining to make it functional are: - Allocate spill slots. - Resolution and placements of Move instructions. - Connect it to the code generator. Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
* Setup policies for register allocation.Nicolas Geoffray2014-04-291-4/+7
| | | | Change-Id: I857e77530fca3e2fb872fc142a916af1b48400dc
* Code cleanup in preparation for x64 backend.Nicolas Geoffray2014-04-171-0/+32
| | | | | | | | | - Use InvokeDexCallingConventionVisitor for setting up HParameterValues - Use kVregSize instead of kX86WordSize when dealing with virtual registers. Change-Id: Ia520223010194c70a3ff0ed659077f55cec4e7d8
* Long support in optimizing compiler.Nicolas Geoffray2014-04-161-4/+12
| | | | | | | | | - Add stack locations to the Location class. - Change logic of parameter passing/setup by setting the location of such instructions the ones for the calling convention. Change-Id: I4730ad58732813dcb9c238f44f55dfc0baa18799
* Use target-specific word instead of runtime word.Nicolas Geoffray2014-04-041-1/+6
| | | | Change-Id: Ia11dc3cc520a1a5c7bd017013e5699af9570ce91
* Support passing arguments to invoke-static* instructions.Nicolas Geoffray2014-04-031-13/+9
| | | | | | | | | - Stop using the frame pointer for accessing locals. - Stop emulating a stack when doing code generation. Instead, rely on dex register model, where instructions only reference registers. Change-Id: Id51bd7d33ac430cb87a53c9f4b0c864eeb1006f9
* Add support for invoke-static in optimizing compiler.Nicolas Geoffray2014-03-311-0/+2
| | | | | | | Support is limited to calls without parameters and returning void. For simplicity, we currently follow the Quick ABI. Change-Id: I54805161141b7eac5959f1cae0dc138dd0b2e8a5
* Plug new optimizing compiler in compilation pipeline.Nicolas Geoffray2014-03-181-3/+33
| | | | | | Also rename accessors to ART's conventions. Change-Id: I344807055b98aa4b27215704ec362191464acecc
* More code generation for the optimizing compiler.Nicolas Geoffray2014-03-131-5/+28
| | | | | | | | | - Add HReturn instruction - Generate code for locals/if/return - Setup infrastructure for register allocation. Currently emulate a stack. Change-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb
* Add codegen support to the optimizing compiler.Nicolas Geoffray2014-03-041-0/+54
Change-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28
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