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| author | buzbee <buzbee@google.com> | 2014-08-28 13:48:56 -0700 |
|---|---|---|
| committer | buzbee <buzbee@google.com> | 2014-08-28 13:48:56 -0700 |
| commit | 3a658077af2a931e5d7f6cd22b777c57112c19df (patch) | |
| tree | 7b9baf7793c6b8fbe11d3d9f8d1a1405f7f65c43 /compiler | |
| parent | 70644461909a68eb5cd032027ae0eb528143d99c (diff) | |
| download | art-3a658077af2a931e5d7f6cd22b777c57112c19df.tar.gz art-3a658077af2a931e5d7f6cd22b777c57112c19df.tar.bz2 art-3a658077af2a931e5d7f6cd22b777c57112c19df.zip | |
Quick compiler: Fix MIPS build
In debug builds, the Quick compiler frequently runs a sanity checker
over the register pool. Among other things, it attempts to verify
consistent representation of register pairs. However, a register's
"wide" flag is meaningful only when the register pair is associated
with a Dalvik wide value (sreg != INVALID_SREG) rather than a temp
wide value.
The MIPS build was tripping over this bad assertion. Fixed here.
Note related cl/105461
Change-Id: Id726ff1ea0f5cbcc8dba6fa3aacb3fd4fc043a63
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/dex/quick/ralloc_util.cc | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc index 0a737a9315..195da0dad2 100644 --- a/compiler/dex/quick/ralloc_util.cc +++ b/compiler/dex/quick/ralloc_util.cc @@ -934,9 +934,9 @@ void Mir2Lir::MarkInUse(RegStorage reg) { bool Mir2Lir::CheckCorePoolSanity() { GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_); for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { - if (info->IsTemp() && info->IsLive() && info->IsWide()) { + int my_sreg = info->SReg(); + if (info->IsTemp() && info->IsLive() && info->IsWide() && my_sreg != INVALID_SREG) { RegStorage my_reg = info->GetReg(); - int my_sreg = info->SReg(); RegStorage partner_reg = info->Partner(); RegisterInfo* partner = GetRegInfo(partner_reg); DCHECK(partner != NULL); @@ -944,12 +944,8 @@ bool Mir2Lir::CheckCorePoolSanity() { DCHECK_EQ(my_reg.GetReg(), partner->Partner().GetReg()); DCHECK(partner->IsLive()); int partner_sreg = partner->SReg(); - if (my_sreg == INVALID_SREG) { - DCHECK_EQ(partner_sreg, INVALID_SREG); - } else { - int diff = my_sreg - partner_sreg; - DCHECK((diff == 0) || (diff == -1) || (diff == 1)); - } + int diff = my_sreg - partner_sreg; + DCHECK((diff == 0) || (diff == -1) || (diff == 1)); } if (info->Master() != info) { // Aliased. |