art/test/456-baseline-array-set, branch cm-13.0Unnamed repository; edit this file 'description' to name the repository.
[optimizing] Use callee-save registers for x862015-03-05T11:08:33+00:00Mark Mendellmark.p.mendell@intel.com2015-03-04T20:42:45+00:005f8741860d465410bfed495dbb5f794590d338da
Add ESI, EDI, EBP to available registers for non-baseline mode. Ensure
that they aren't used when byte addressible registers are needed.
Change-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Add ESI, EDI, EBP to available registers for non-baseline mode. Ensure
that they aren't used when byte addressible registers are needed.
Change-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>