From 651ef18db973f8543faf8a7450484502f916a936 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 23 Apr 2012 15:42:54 +0000 Subject: ARM: bcmring: move cfg_global header to mach/ Platforms should not have header files outside of include/mach, and bcmring is the only one that has one just under include/, so move that away. Signed-off-by: Arnd Bergmann --- drivers/mtd/nand/nand_bcm_umi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h index 198b304d6f72..a158d5dd9a02 100644 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ b/drivers/mtd/nand/nand_bcm_umi.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include #include -#include +#include /* ---- Constants and Types ---------------------------------------------- */ #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) -- cgit v1.2.3 From 878040ef831a12855af26a42cc25c817f4fb3f2d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 25 Apr 2012 16:44:23 +0000 Subject: ARM: bcmring: use proper MMIO accessors A lot of code in bcmring just dereferences pointers to MMIO locations, which is not safe. This annotates the pointers correctly using __iomem and uses readl/write to access them. Signed-off-by: Arnd Bergmann --- drivers/mtd/nand/bcm_umi_nand.c | 12 +++---- drivers/mtd/nand/nand_bcm_umi.h | 71 ++++++++++++++++++++--------------------- 2 files changed, 41 insertions(+), 42 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c index 6908cdde3065..55e7799f4bf3 100644 --- a/drivers/mtd/nand/bcm_umi_nand.c +++ b/drivers/mtd/nand/bcm_umi_nand.c @@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd) int bcm_umi_nand_inithw(void) { /* Configure nand timing parameters */ - REG_UMI_NAND_TCR &= ~0x7ffff; - REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; + writel(readl(®_UMI_NAND_TCR) & ~0x7ffff, ®_UMI_NAND_TCR); + writel(readl(®_UMI_NAND_TCR) | HW_CFG_NAND_TCR, ®_UMI_NAND_TCR); #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) /* enable software control of CS */ - REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; + writel(readl(®_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, ®_UMI_NAND_TCR); #endif /* keep NAND chip select asserted */ - REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; + writel(readl(®_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, ®_UMI_NAND_RCSR); - REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; + writel(readl(®_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, ®_UMI_NAND_TCR); /* enable writes to flash */ - REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; + writel(readl(®_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, ®_UMI_MMD_ICR); writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); nand_bcm_umi_wait_till_ready(); diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h index a158d5dd9a02..d90186684db8 100644 --- a/drivers/mtd/nand/nand_bcm_umi.h +++ b/drivers/mtd/nand/nand_bcm_umi.h @@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData, /* Check in device is ready */ static inline int nand_bcm_umi_dev_ready(void) { - return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; + return readl(®_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY; } /* Wait until device is ready */ @@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void) static inline void nand_bcm_umi_hamming_enable_hwecc(void) { /* disable and reset ECC, 512 byte page */ - REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | - REG_UMI_NAND_ECC_CSR_256BYTE); + writel(readl(®_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | + REG_UMI_NAND_ECC_CSR_256BYTE), ®_UMI_NAND_ECC_CSR); /* enable ECC */ - REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; + writel(readl(®_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE, + ®_UMI_NAND_ECC_CSR); } #if NAND_ECC_BCH @@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void) static inline void nand_bcm_umi_bch_enable_read_hwecc(void) { /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); } /* Enable BCH Write ECC */ static inline void nand_bcm_umi_bch_enable_write_hwecc(void) { /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, ®_UMI_BCH_CTRL_STATUS); /* Turn on ECC */ - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, ®_UMI_BCH_CTRL_STATUS); } /* Config number of BCH ECC bytes */ @@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) uint32_t numBits = numEccBytes * 8; /* disable and reset ECC */ - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | - REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; + writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | + REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, + ®_UMI_BCH_CTRL_STATUS); /* Every correctible bit requires 13 ECC bits */ tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); @@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes) kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); /* Write the settings */ - REG_UMI_BCH_N = nValue; - REG_UMI_BCH_T = tValue; - REG_UMI_BCH_K = kValue; + writel(nValue, ®_UMI_BCH_N); + writel(tValue, ®_UMI_BCH_T); + writel(kValue, ®_UMI_BCH_K); } /* Pause during ECC read calculation to skip bytes in OOB */ static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) { - REG_UMI_BCH_CTRL_STATUS = - REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | - REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, ®_UMI_BCH_CTRL_STATUS); } /* Resume during ECC read calculation after skipping bytes in OOB */ static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) { - REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; + writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS); } /* Poll read ECC calc to check when hardware completes */ @@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) do { /* wait for ECC to be valid */ - regVal = REG_UMI_BCH_CTRL_STATUS; + regVal = readl(®_UMI_BCH_CTRL_STATUS); } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); return regVal; @@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void) static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) { /* wait for ECC to be valid */ - while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) + while ((readl(®_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) == 0) ; } @@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, if (pageSize != NAND_DATA_ACCESS_SIZE) { /* skip BI */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, while (numToRead > numEccBytes) { /* skip free oob region */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, while (numToRead > 11) { #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; + *oobp = readb(®_NAND_DATA8); eccCalc[eccPos++] = *oobp; oobp++; #else - eccCalc[eccPos++] = REG_NAND_DATA8; + eccCalc[eccPos++] = readb(®_NAND_DATA8); #endif numToRead--; } @@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, if (numToRead == 11) { /* read BI */ #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp++ = REG_NAND_DATA8; + *oobp++ = readb(®_NAND_DATA8); #else - REG_NAND_DATA8; + readb(®_NAND_DATA8); #endif numToRead--; } @@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize, nand_bcm_umi_bch_resume_read_ecc_calc(); while (numToRead) { #if defined(__KERNEL__) && !defined(STANDALONE) - *oobp = REG_NAND_DATA8; + *oobp = readb(®_NAND_DATA8); eccCalc[eccPos++] = *oobp; oobp++; #else - eccCalc[eccPos++] = REG_NAND_DATA8; + eccCalc[eccPos++] = readb(®_NAND_DATA8); #endif numToRead--; } @@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, if (pageSize == NAND_DATA_ACCESS_SIZE) { /* Now fill in the ECC bytes */ if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; + eccVal = readl(®_UMI_BCH_WR_ECC_3); /* Usually we skip CM in oob[0,1] */ NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], @@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC 12 */ if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; + eccVal = readl(®_UMI_BCH_WR_ECC_2); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], (eccVal >> 24) & 0xff); /* ECC11 */ @@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, /* Now fill in the ECC bytes */ if (numEccBytes >= 13) - eccVal = REG_UMI_BCH_WR_ECC_3; + eccVal = readl(®_UMI_BCH_WR_ECC_3); /* Usually skip CM in oob[1,2] */ NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], @@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC12 */ if (numEccBytes >= 9) - eccVal = REG_UMI_BCH_WR_ECC_2; + eccVal = readl(®_UMI_BCH_WR_ECC_2); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], (eccVal >> 24) & 0xff); /* ECC11 */ @@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC8 */ if (numEccBytes >= 5) - eccVal = REG_UMI_BCH_WR_ECC_1; + eccVal = readl(®_UMI_BCH_WR_ECC_1); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], (eccVal >> 24) & 0xff); /* ECC7 */ @@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize, eccVal & 0xff); /* ECC4 */ if (numEccBytes >= 1) - eccVal = REG_UMI_BCH_WR_ECC_0; + eccVal = readl(®_UMI_BCH_WR_ECC_0); NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], (eccVal >> 24) & 0xff); /* ECC3 */ -- cgit v1.2.3 From b4084bcf5ae833e049b0c428868de7e4efae2e4f Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Fri, 22 Jun 2012 15:29:28 +0200 Subject: ARM: at91/defconfig: Remove unaffected config option The commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c removed the use of CONFIG_MTD_NAND_ATMEL_ECC_NONE and CONFIG_MTD_NAND_ATMEL_ECC_HW but the Kconfig file was forgotten. This patch remove those inoperative options. Signed-off-by: Richard Genoud Signed-off-by: Nicolas Ferre --- drivers/mtd/nand/Kconfig | 40 ---------------------------------------- 1 file changed, 40 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 31bb7e5b504a..0d9340798954 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -406,46 +406,6 @@ config MTD_NAND_ATMEL help Enables support for NAND Flash / Smart Media Card interface on Atmel AT91 and AVR32 processors. -choice - prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32" - depends on MTD_NAND_ATMEL - -config MTD_NAND_ATMEL_ECC_HW - bool "Hardware ECC" - depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32 - help - Use hardware ECC instead of software ECC when the chip - supports it. - - The hardware ECC controller is capable of single bit error - correction and 2-bit random detection per page. - - NB : hardware and software ECC schemes are incompatible. - If you switch from one to another, you'll have to erase your - mtd partition. - - If unsure, say Y - -config MTD_NAND_ATMEL_ECC_SOFT - bool "Software ECC" - help - Use software ECC. - - NB : hardware and software ECC schemes are incompatible. - If you switch from one to another, you'll have to erase your - mtd partition. - -config MTD_NAND_ATMEL_ECC_NONE - bool "No ECC (testing only, DANGEROUS)" - depends on DEBUG_KERNEL - help - No ECC will be used. - It's not a good idea and it should be reserved for testing - purpose only. - - If unsure, say N - -endchoice config MTD_NAND_PXA3xx tristate "Support for NAND flash devices on PXA3xx" -- cgit v1.2.3 From 1e7ba630d4aeabef8e022a4099b20ab9f660d37d Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sun, 22 Jul 2012 19:51:02 +0200 Subject: MTD: pxa3xx-nand: add devicetree bindings This patch contains a hack to get the DMA resources of the device when probed from a devicetree node. This can be removed once a generic DMA controller framework lands. A mtd_part_parser_data is passed mtd_device_parse_register which contains a reference to the device node, so MTD partitions can be added as children. Signed-off-by: Daniel Mack Cc: David Woodhouse Acked-by: Arnd Bergmann Signed-off-by: Haojian Zhuang --- drivers/mtd/nand/pxa3xx_nand.c | 85 +++++++++++++++++++++++++++++++++++------- 1 file changed, 71 insertions(+), 14 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 252aaefcacfa..b0319d8934ad 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include #include @@ -1081,21 +1083,31 @@ static int alloc_nand_resource(struct platform_device *pdev) } clk_enable(info->clk); - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no resource defined for data DMA\n"); - ret = -ENXIO; - goto fail_put_clk; - } - info->drcmr_dat = r->start; + /* + * This is a dirty hack to make this driver work from devicetree + * bindings. It can be removed once we have a prober DMA controller + * framework for DT. + */ + if (pdev->dev.of_node && cpu_is_pxa3xx()) { + info->drcmr_dat = 97; + info->drcmr_cmd = 99; + } else { + r = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (r == NULL) { + dev_err(&pdev->dev, "no resource defined for data DMA\n"); + ret = -ENXIO; + goto fail_put_clk; + } + info->drcmr_dat = r->start; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r == NULL) { - dev_err(&pdev->dev, "no resource defined for command DMA\n"); - ret = -ENXIO; - goto fail_put_clk; + r = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (r == NULL) { + dev_err(&pdev->dev, "no resource defined for command DMA\n"); + ret = -ENXIO; + goto fail_put_clk; + } + info->drcmr_cmd = r->start; } - info->drcmr_cmd = r->start; irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -1200,12 +1212,55 @@ static int pxa3xx_nand_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_OF +static struct of_device_id pxa3xx_nand_dt_ids[] = { + { .compatible = "marvell,pxa3xx-nand" }, + {} +}; +MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); + +static int pxa3xx_nand_probe_dt(struct platform_device *pdev) +{ + struct pxa3xx_nand_platform_data *pdata; + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *of_id = + of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); + + if (!of_id) + return 0; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + if (of_get_property(np, "marvell,nand-enable-arbiter", NULL)) + pdata->enable_arbiter = 1; + if (of_get_property(np, "marvell,nand-keep-config", NULL)) + pdata->keep_config = 1; + of_property_read_u32(np, "num-cs", &pdata->num_cs); + + pdev->dev.platform_data = pdata; + + return 0; +} +#else +static inline int pxa3xx_nand_probe_dt(struct platform_device *) +{ + return 0; +} +#endif + static int pxa3xx_nand_probe(struct platform_device *pdev) { struct pxa3xx_nand_platform_data *pdata; + struct mtd_part_parser_data ppdata = {}; struct pxa3xx_nand_info *info; int ret, cs, probe_success; + ret = pxa3xx_nand_probe_dt(pdev); + if (ret) + return ret; + pdata = pdev->dev.platform_data; if (!pdata) { dev_err(&pdev->dev, "no platform data defined\n"); @@ -1229,8 +1284,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) continue; } + ppdata.of_node = pdev->dev.of_node; ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, - NULL, pdata->parts[cs], + &ppdata, pdata->parts[cs], pdata->nr_parts[cs]); if (!ret) probe_success = 1; @@ -1306,6 +1362,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev) static struct platform_driver pxa3xx_nand_driver = { .driver = { .name = "pxa3xx-nand", + .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids), }, .probe = pxa3xx_nand_probe, .remove = pxa3xx_nand_remove, -- cgit v1.2.3 From 6e308f87c821e5b9316d9eb69e96d8a33910412a Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 20 Aug 2012 13:40:31 +0800 Subject: mtd: nand: append missing parameter and value Signed-off-by: Haojian Zhuang --- drivers/mtd/nand/pxa3xx_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index b0319d8934ad..d944d6ef7da8 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1034,7 +1034,7 @@ static int alloc_nand_resource(struct platform_device *pdev) struct pxa3xx_nand_platform_data *pdata; struct pxa3xx_nand_info *info; struct pxa3xx_nand_host *host; - struct nand_chip *chip; + struct nand_chip *chip = NULL; struct mtd_info *mtd; struct resource *r; int ret, irq, cs; @@ -1244,7 +1244,7 @@ static int pxa3xx_nand_probe_dt(struct platform_device *pdev) return 0; } #else -static inline int pxa3xx_nand_probe_dt(struct platform_device *) +static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev) { return 0; } -- cgit v1.2.3 From 65b97cf6b8deca3ad7a3e00e8316bb89617190fb Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Thu, 30 Aug 2012 12:53:22 -0700 Subject: mtd: nand: omap2: handle nand on gpmc GPMC platform initialization has been modified to fill NAND platform data with GPMC NAND register details. As these registers are accessible in NAND driver itself, configure NAND in GPMC by itself. Modified prefetch and ecc functions are logically same as the corresponding exported symbols from GPMC code. Note: Verfying that other CS have not yet enabled for prefetch & ecc has to be incorporated. Currently this causes no issues as there are no boards that use NAND on multiple CS. With ongoing GPMC driver migration, perhaps it would be better to consider NAND connected on multiple CS as a single peripheral using multiple CS. This would make handling multiple CS issues easier. Signed-off-by: Afzal Mohammed Acked-by: Artem Bityutskiy Signed-off-by: Tony Lindgren --- drivers/mtd/nand/omap2.c | 206 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 161 insertions(+), 45 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index ac4fd756eda3..52fc089d5bcb 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -101,6 +101,16 @@ #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) +#define PREFETCH_CONFIG1_CS_SHIFT 24 +#define ECC_CONFIG_CS_SHIFT 1 +#define CS_MASK 0x7 +#define ENABLE_PREFETCH (0x1 << 7) +#define DMA_MPU_MODE_SHIFT 2 +#define ECCSIZE1_SHIFT 22 +#define ECC1RESULTSIZE 0x1 +#define ECCCLEAR 0x100 +#define ECC1 0x1 + /* oob info generated runtime depending on ecc algorithm and layout selected */ static struct nand_ecclayout omap_oobinfo; /* Define some generic bad / good block scan pattern which are used @@ -133,6 +143,7 @@ struct omap_nand_info { } iomode; u_char *buf; int buf_len; + struct gpmc_nand_regs reg; #ifdef CONFIG_MTD_NAND_OMAP_BCH struct bch_control *bch; @@ -140,6 +151,63 @@ struct omap_nand_info { #endif }; +/** + * omap_prefetch_enable - configures and starts prefetch transfer + * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write + * @dma_mode: dma mode enable (1) or disable (0) + * @u32_count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + */ +static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, + unsigned int u32_count, int is_write, struct omap_nand_info *info) +{ + u32 val; + + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) + return -1; + + if (readl(info->reg.gpmc_prefetch_control)) + return -EBUSY; + + /* Set the amount of bytes to be prefetched */ + writel(u32_count, info->reg.gpmc_prefetch_config2); + + /* Set dma/mpu mode, the prefetch read / post write and + * enable the engine. Set which cs is has requested for. + */ + val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | + PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | + (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); + writel(val, info->reg.gpmc_prefetch_config1); + + /* Start the prefetch engine */ + writel(0x1, info->reg.gpmc_prefetch_control); + + return 0; +} + +/** + * omap_prefetch_reset - disables and stops the prefetch engine + */ +static int omap_prefetch_reset(int cs, struct omap_nand_info *info) +{ + u32 config1; + + /* check if the same module/cs is trying to reset */ + config1 = readl(info->reg.gpmc_prefetch_config1); + if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) + return -EINVAL; + + /* Stop the PFPW engine */ + writel(0x0, info->reg.gpmc_prefetch_control); + + /* Reset/disable the PFPW engine */ + writel(0x0, info->reg.gpmc_prefetch_config1); + + return 0; +} + /** * omap_hwcontrol - hardware specific access to control-lines * @mtd: MTD device structure @@ -158,13 +226,13 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) if (cmd != NAND_CMD_NONE) { if (ctrl & NAND_CLE) - gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd); + writeb(cmd, info->reg.gpmc_nand_command); else if (ctrl & NAND_ALE) - gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd); + writeb(cmd, info->reg.gpmc_nand_address); else /* NAND_NCE */ - gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd); + writeb(cmd, info->reg.gpmc_nand_data); } } @@ -198,7 +266,8 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) iowrite8(*p++, info->nand.IO_ADDR_W); /* wait until buffer is available for write */ do { - status = gpmc_read_status(GPMC_STATUS_BUFFER); + status = readl(info->reg.gpmc_status) & + GPMC_STATUS_BUFF_EMPTY; } while (!status); } } @@ -235,7 +304,8 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) iowrite16(*p++, info->nand.IO_ADDR_W); /* wait until buffer is available for write */ do { - status = gpmc_read_status(GPMC_STATUS_BUFFER); + status = readl(info->reg.gpmc_status) & + GPMC_STATUS_BUFF_EMPTY; } while (!status); } } @@ -265,8 +335,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, - PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); + ret = omap_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -275,14 +345,15 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) omap_read_buf8(mtd, (u_char *)p, len); } else { do { - r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); + r_count = readl(info->reg.gpmc_prefetch_status); + r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count); r_count = r_count >> 2; ioread32_rep(info->nand.IO_ADDR_R, p, r_count); p += r_count; len -= r_count << 2; } while (len); /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); + omap_prefetch_reset(info->gpmc_cs, info); } } @@ -301,6 +372,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd, int i = 0, ret = 0; u16 *p = (u16 *)buf; unsigned long tim, limit; + u32 val; /* take care of subpage writes */ if (len % 2 != 0) { @@ -310,8 +382,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd, } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, - PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); + ret = omap_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -320,7 +392,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd, omap_write_buf8(mtd, (u_char *)p, len); } else { while (len) { - w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); + w_count = readl(info->reg.gpmc_prefetch_status); + w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count); w_count = w_count >> 1; for (i = 0; (i < w_count) && len; i++, len -= 2) iowrite16(*p++, info->nand.IO_ADDR_W); @@ -329,11 +402,14 @@ static void omap_write_buf_pref(struct mtd_info *mtd, tim = 0; limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); - while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + do { cpu_relax(); + val = readl(info->reg.gpmc_prefetch_status); + val = GPMC_PREFETCH_STATUS_COUNT(val); + } while (val && (tim++ < limit)); /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); + omap_prefetch_reset(info->gpmc_cs, info); } } @@ -365,6 +441,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, unsigned long tim, limit; unsigned n; int ret; + u32 val; if (addr >= high_memory) { struct page *p1; @@ -396,9 +473,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, tx->callback_param = &info->comp; dmaengine_submit(tx); - /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, - PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); + /* configure and start prefetch transfer */ + ret = omap_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy_unmap; @@ -410,11 +487,15 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, wait_for_completion(&info->comp); tim = 0; limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); - while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + + do { cpu_relax(); + val = readl(info->reg.gpmc_prefetch_status); + val = GPMC_PREFETCH_STATUS_COUNT(val); + } while (val && (tim++ < limit)); /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); + omap_prefetch_reset(info->gpmc_cs, info); dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); return 0; @@ -474,7 +555,8 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev) u32 irq_stat; irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); - bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); + bytes = readl(info->reg.gpmc_prefetch_status); + bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes); bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ if (irq_stat & 0x2) @@ -534,8 +616,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) init_completion(&info->comp); /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, - PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); + ret = omap_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; @@ -549,7 +631,7 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) wait_for_completion(&info->comp); /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); + omap_prefetch_reset(info->gpmc_cs, info); return; out_copy: @@ -572,6 +654,7 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, struct omap_nand_info, mtd); int ret = 0; unsigned long tim, limit; + u32 val; if (len <= mtd->oobsize) { omap_write_buf_pref(mtd, buf, len); @@ -583,8 +666,8 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, init_completion(&info->comp); /* configure and start prefetch transfer : size=24 */ - ret = gpmc_prefetch_enable(info->gpmc_cs, - (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); + ret = omap_prefetch_enable(info->gpmc_cs, + (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; @@ -599,11 +682,14 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, /* wait for data to flushed-out before reset the prefetch */ tim = 0; limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); - while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + do { + val = readl(info->reg.gpmc_prefetch_status); + val = GPMC_PREFETCH_STATUS_COUNT(val); cpu_relax(); + } while (val && (tim++ < limit)); /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); + omap_prefetch_reset(info->gpmc_cs, info); return; out_copy: @@ -843,7 +929,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code); + u32 val; + + val = readl(info->reg.gpmc_ecc_config); + if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) + return -EINVAL; + + /* read ecc result */ + val = readl(info->reg.gpmc_ecc1_result); + *ecc_code++ = val; /* P128e, ..., P1e */ + *ecc_code++ = val >> 16; /* P128o, ..., P1o */ + /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ + *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); + + return 0; } /** @@ -857,8 +956,34 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) mtd); struct nand_chip *chip = mtd->priv; unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; + u32 val; - gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); + /* clear ecc and enable bits */ + val = ECCCLEAR | ECC1; + writel(val, info->reg.gpmc_ecc_control); + + /* program ecc and result sizes */ + val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | + ECC1RESULTSIZE); + writel(val, info->reg.gpmc_ecc_size_config); + + switch (mode) { + case NAND_ECC_READ: + case NAND_ECC_WRITE: + writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); + break; + case NAND_ECC_READSYN: + writel(ECCCLEAR, info->reg.gpmc_ecc_control); + break; + default: + dev_info(&info->pdev->dev, + "error: unrecognized Mode[%d]!\n", mode); + break; + } + + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); + writel(val, info->reg.gpmc_ecc_config); } /** @@ -886,10 +1011,9 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) else timeo += (HZ * 20) / 1000; - gpmc_nand_write(info->gpmc_cs, - GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF)); + writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); while (time_before(jiffies, timeo)) { - status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA); + status = readb(info->reg.gpmc_nand_data); if (status & NAND_STATUS_READY) break; cond_resched(); @@ -909,22 +1033,13 @@ static int omap_dev_ready(struct mtd_info *mtd) struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - val = gpmc_read_status(GPMC_GET_IRQ_STATUS); + val = readl(info->reg.gpmc_status); + if ((val & 0x100) == 0x100) { - /* Clear IRQ Interrupt */ - val |= 0x100; - val &= ~(0x0); - gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val); + return 1; } else { - unsigned int cnt = 0; - while (cnt++ < 0x1FF) { - if ((val & 0x100) == 0x100) - return 0; - val = gpmc_read_status(GPMC_GET_IRQ_STATUS); - } + return 0; } - - return 1; } #ifdef CONFIG_MTD_NAND_OMAP_BCH @@ -1175,6 +1290,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->gpmc_cs = pdata->cs; info->phys_base = pdata->phys_base; + info->reg = pdata->reg; info->mtd.priv = &info->nand; info->mtd.name = dev_name(&pdev->dev); -- cgit v1.2.3 From 9c4c2f8b91a8bcc431d1c033e4d4455479b8183b Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Thu, 30 Aug 2012 12:53:23 -0700 Subject: mtd: nand: omap2: obtain memory from resource gpmc initialization done by platform code now updates struct resource with the address space alloted for nand. Use this interface to obtain memory rather than relying on platform data field - phys_base. Signed-off-by: Afzal Mohammed Acked-by: Artem Bityutskiy Signed-off-by: Tony Lindgren --- drivers/mtd/nand/omap2.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 52fc089d5bcb..3578c633e97e 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -134,6 +134,7 @@ struct omap_nand_info { int gpmc_cs; unsigned long phys_base; + unsigned long mem_size; struct completion comp; struct dma_chan *dma; int gpmc_irq; @@ -1270,6 +1271,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) int i, offset; dma_cap_mask_t mask; unsigned sig; + struct resource *res; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1289,7 +1291,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->pdev = pdev; info->gpmc_cs = pdata->cs; - info->phys_base = pdata->phys_base; info->reg = pdata->reg; info->mtd.priv = &info->nand; @@ -1302,13 +1303,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) /* NAND write protect off */ gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0); - if (!request_mem_region(info->phys_base, NAND_IO_SIZE, + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + err = -EINVAL; + dev_err(&pdev->dev, "error getting memory resource\n"); + goto out_free_info; + } + + info->phys_base = res->start; + info->mem_size = resource_size(res); + + if (!request_mem_region(info->phys_base, info->mem_size, pdev->dev.driver->name)) { err = -EBUSY; goto out_free_info; } - info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); + info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size); if (!info->nand.IO_ADDR_R) { err = -ENOMEM; goto out_release_mem_region; @@ -1479,7 +1490,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) out_release_mem_region: if (info->dma) dma_release_channel(info->dma); - release_mem_region(info->phys_base, NAND_IO_SIZE); + release_mem_region(info->phys_base, info->mem_size); out_free_info: kfree(info); -- cgit v1.2.3 From 5c4684557b7e37afd42fa35f420f2f28bfb75442 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Thu, 30 Aug 2012 12:53:24 -0700 Subject: mtd: nand: omap2: use gpmc provided irqs GPMC platform initialization provides it's clients with interrupts that can be used through struct resource. Make use of it for irq mode functionality. Also now write protect disable is done by GPMC, hence remove it. Signed-off-by: Afzal Mohammed Acked-by: Artem Bityutskiy [tony@atomide.com: updated to fix new warnings introduced] Signed-off-by: Tony Lindgren --- drivers/mtd/nand/omap2.c | 78 +++++++++++++++++++++++++++++++----------------- 1 file changed, 50 insertions(+), 28 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 3578c633e97e..27293e328517 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -137,7 +137,8 @@ struct omap_nand_info { unsigned long mem_size; struct completion comp; struct dma_chan *dma; - int gpmc_irq; + int gpmc_irq_fifo; + int gpmc_irq_count; enum { OMAP_NAND_IO_READ = 0, /* read */ OMAP_NAND_IO_WRITE, /* write */ @@ -553,14 +554,12 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev) { struct omap_nand_info *info = (struct omap_nand_info *) dev; u32 bytes; - u32 irq_stat; - irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); bytes = readl(info->reg.gpmc_prefetch_status); bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes); bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ - if (irq_stat & 0x2) + if (this_irq == info->gpmc_irq_count) goto done; if (info->buf_len && (info->buf_len < bytes)) @@ -577,20 +576,17 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev) (u32 *)info->buf, bytes >> 2); info->buf = info->buf + bytes; - if (irq_stat & 0x2) + if (this_irq == info->gpmc_irq_count) goto done; } - gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); return IRQ_HANDLED; done: complete(&info->comp); - /* disable irq */ - gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); - /* clear status */ - gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + disable_irq_nosync(info->gpmc_irq_fifo); + disable_irq_nosync(info->gpmc_irq_count); return IRQ_HANDLED; } @@ -624,9 +620,9 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) goto out_copy; info->buf_len = len; - /* enable irq */ - gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, - (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + enable_irq(info->gpmc_irq_count); + enable_irq(info->gpmc_irq_fifo); /* waiting for read to complete */ wait_for_completion(&info->comp); @@ -674,12 +670,13 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, goto out_copy; info->buf_len = len; - /* enable irq */ - gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, - (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + enable_irq(info->gpmc_irq_count); + enable_irq(info->gpmc_irq_fifo); /* waiting for write to complete */ wait_for_completion(&info->comp); + /* wait for data to flushed-out before reset the prefetch */ tim = 0; limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); @@ -1300,9 +1297,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.options = pdata->devsize; info->nand.options |= NAND_SKIP_BBTSCAN; - /* NAND write protect off */ - gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { err = -EINVAL; @@ -1392,17 +1386,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) break; case NAND_OMAP_PREFETCH_IRQ: - err = request_irq(pdata->gpmc_irq, - omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); + info->gpmc_irq_fifo = platform_get_irq(pdev, 0); + if (info->gpmc_irq_fifo <= 0) { + dev_err(&pdev->dev, "error getting fifo irq\n"); + err = -ENODEV; + goto out_release_mem_region; + } + err = request_irq(info->gpmc_irq_fifo, omap_nand_irq, + IRQF_SHARED, "gpmc-nand-fifo", info); if (err) { dev_err(&pdev->dev, "requesting irq(%d) error:%d", - pdata->gpmc_irq, err); + info->gpmc_irq_fifo, err); + info->gpmc_irq_fifo = 0; + goto out_release_mem_region; + } + + info->gpmc_irq_count = platform_get_irq(pdev, 1); + if (info->gpmc_irq_count <= 0) { + dev_err(&pdev->dev, "error getting count irq\n"); + err = -ENODEV; + goto out_release_mem_region; + } + err = request_irq(info->gpmc_irq_count, omap_nand_irq, + IRQF_SHARED, "gpmc-nand-count", info); + if (err) { + dev_err(&pdev->dev, "requesting irq(%d) error:%d", + info->gpmc_irq_count, err); + info->gpmc_irq_count = 0; goto out_release_mem_region; - } else { - info->gpmc_irq = pdata->gpmc_irq; - info->nand.read_buf = omap_read_buf_irq_pref; - info->nand.write_buf = omap_write_buf_irq_pref; } + + info->nand.read_buf = omap_read_buf_irq_pref; + info->nand.write_buf = omap_write_buf_irq_pref; + break; default: @@ -1490,6 +1506,10 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) out_release_mem_region: if (info->dma) dma_release_channel(info->dma); + if (info->gpmc_irq_count > 0) + free_irq(info->gpmc_irq_count, info); + if (info->gpmc_irq_fifo > 0) + free_irq(info->gpmc_irq_fifo, info); release_mem_region(info->phys_base, info->mem_size); out_free_info: kfree(info); @@ -1508,8 +1528,10 @@ static int omap_nand_remove(struct platform_device *pdev) if (info->dma) dma_release_channel(info->dma); - if (info->gpmc_irq) - free_irq(info->gpmc_irq, info); + if (info->gpmc_irq_count > 0) + free_irq(info->gpmc_irq_count, info); + if (info->gpmc_irq_fifo > 0) + free_irq(info->gpmc_irq_fifo, info); /* Release NAND device, its internal structures and partitions */ nand_release(&info->mtd); -- cgit v1.2.3 From 4b25408f1f61c35b70a19a41053b5e5e3224e97f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 30 Aug 2012 15:37:24 -0700 Subject: ARM: OMAP: Move gpio.h to include/linux/platform_data This way we can remove includes of plat/gpio.h which won't work with the single zImage support. Note that we also remove the cpu_class_is_omap2() check in gpio-omap.c as the drivers should not call it as we need to make it local to arch/arm/mach-omap2 for single zImage support. While at it, arrange the related includes in the standard way. Cc: Grant Likely Cc: linux-mtd@lists.infradead.org Cc: alsa-devel@alsa-project.org Acked-by: Linus Walleij Signed-off-by: Tony Lindgren --- drivers/mtd/nand/ams-delta.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c index 861ca8f7e47d..78a524b49357 100644 --- a/drivers/mtd/nand/ams-delta.c +++ b/drivers/mtd/nand/ams-delta.c @@ -23,12 +23,16 @@ #include #include #include +#include +#include + #include -#include #include -#include + #include +#include + /* * MTD structure for E3 (Delta) */ -- cgit v1.2.3 From ec2a0833e5157fab6cac5f57a49b2f31eb418a39 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:11:34 +0200 Subject: ARM: davinci: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the davinci include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Mauro Carvalho Chehab Acked-by: Felipe Balbi Cc: Sekhar Nori Cc: Kevin Hilman Cc: "Ben Dooks" Cc: "Wolfram Sang" Cc: Dmitry Torokhov Cc: Chris Ball Cc: David Woodhouse Cc: Grant Likely Cc: Alan Stern Cc: Liam Girdwood Cc: davinci-linux-open-source@linux.davincidsp.com --- drivers/mtd/nand/davinci_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d94b03c207af..f1deb1ee2c95 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -34,8 +34,8 @@ #include #include -#include -#include +#include +#include /* * This is a device driver for the NAND flash controller found on the -- cgit v1.2.3 From 82906b13a6f4f42edec92f0a3e480e1bdd9b3f91 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:14:29 +0200 Subject: ARM: imx: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the imx include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Mauro Carvalho Chehab Acked-by: Sascha Hauer Acked-by: Vinod Koul Cc: Russell King Cc: Dan Williams Cc: "Ben Dooks (embedded platforms)" Cc: "Wolfram Sang (embedded platforms)" Cc: Chris Ball Cc: David Woodhouse Cc: Grant Likely Cc: Alan Cox Cc: Felipe Balbi Cc: Alan Stern Cc: Florian Tobias Schandinat Cc: Liam Girdwood Cc: Javier Martin Cc: Shawn Guo Cc: Guennadi Liakhovetski --- drivers/mtd/nand/mxc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 6acc790c2fbb..5683604967d7 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -36,7 +36,7 @@ #include #include -#include +#include #include #define DRIVER_NAME "mxc_nand" -- cgit v1.2.3 From 293b2da1b61136813fc2764f43304c66ff8040e9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:16:48 +0200 Subject: ARM: pxa: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the pxa include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Mauro Carvalho Chehab Acked-by: Igor Grinberg Acked-by: Jeff Garzik Acked-by: Marek Vasut Acked-by: Robert Jarzmik Acked-by: Paul Parsons Acked-by: Vinod Koul Acked-By: Stefan Schmidt Cc: Eric Miao Cc: Haojian Zhuang Cc: Daniel Ribeiro Cc: Harald Welte Cc: Philipp Zabel Cc: Tomas Cech Cc: Sergey Lapin Cc: Jonathan Cameron Cc: Dan Williams Cc: Dmitry Torokhov Cc: Chris Ball Cc: David Woodhouse Cc: Samuel Ortiz Cc: Alan Stern Cc: Florian Tobias Schandinat Cc: Liam Girdwood Cc: Jaroslav Kysela Cc: Takashi Iwai Cc: Guennadi Liakhovetski Cc: Artem Bityutskiy Cc: openezx-devel@lists.openezx.org --- drivers/mtd/nand/pxa3xx_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 252aaefcacfa..c53502f3eb6c 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -24,7 +24,7 @@ #include #include -#include +#include #define CHIP_DELAY_TIMEOUT (2 * HZ/10) #define NAND_STOP_DELAY (2 * HZ/50) -- cgit v1.2.3 From db298da2c31e1dcf7c9b7c9cef6217ad3449ebb7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:19:33 +0200 Subject: ARM: nomadik: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the nomadik include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Felipe Balbi Acked-by: Alessandro Rubini Acked-by: Linus Walleij Cc: STEricsson Cc: Srinidhi Kasagar Cc: Herbert Xu Cc: "David S. Miller" Cc: Dmitry Torokhov Cc: David Woodhouse Cc: Andreas Westin --- drivers/mtd/nand/nomadik_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nomadik_nand.c b/drivers/mtd/nand/nomadik_nand.c index a86aa812ca13..9ee0c4edfacf 100644 --- a/drivers/mtd/nand/nomadik_nand.c +++ b/drivers/mtd/nand/nomadik_nand.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include -- cgit v1.2.3 From 2203747c97712975accc5e69bdaf1ad38a691635 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:21:06 +0200 Subject: ARM: omap: move platform_data definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the omap include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Tony Lindgren Cc: Kevin Hilman Cc: "Benoît Cousson" Cc: Dmitry Torokhov Cc: David Woodhouse Cc: Kyungmin Park Cc: Ohad Ben-Cohen Cc: Grant Likely Cc: Omar Ramirez Luna Cc: Tomi Valkeinen Cc: Florian Tobias Schandinat Cc: Peter Ujfalusi Cc: Jarkko Nikula Cc: Liam Girdwood Cc: Artem Bityutskiy Cc: Jean Pihet Cc: J Keerthy Cc: linux-omap@vger.kernel.org --- drivers/mtd/nand/omap2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 27293e328517..fc8111278d12 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -29,7 +29,7 @@ #include #include -#include +#include #define DRIVER_NAME "omap2-nand" #define OMAP_NAND_TIMEOUT_MS 5000 -- cgit v1.2.3 From c02cecb92ed49f36196ee9e29d29c4cfcbad05ae Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:21:54 +0200 Subject: ARM: orion: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the orion include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Mauro Carvalho Chehab Cc: Jason Cooper Cc: Andrew Lunn Cc: Vinod Koul Cc: Dan Williams Cc: Bryan Wu Cc: Richard Purdie Cc: Chris Ball Cc: David Woodhouse Cc: Alan Stern Cc: Liam Girdwood Cc: Jaroslav Kysela Cc: Takashi Iwai --- drivers/mtd/nand/orion_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index fc5a868c436e..131b58a133f1 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { -- cgit v1.2.3 From 436d42c61c3eef1d02256174c8615046c61a28ad Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Aug 2012 15:22:12 +0200 Subject: ARM: samsung: move platform_data definitions Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the samsung include directories Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Nicolas Pitre Acked-by: Mauro Carvalho Chehab Cc: Kukjin Kim Cc: Kyungmin Park Cc: Ben Dooks Cc: Jeff Garzik Cc: Guenter Roeck Cc: "Wolfram Sang (embedded platforms)" Cc: Dmitry Torokhov Cc: Bryan Wu Cc: Richard Purdie Cc: Sylwester Nawrocki Cc: Chris Ball Cc: David Woodhouse Cc: Grant Likely Cc: Felipe Balbi Cc: Alan Stern Cc: Sangbeom Kim Cc: Liam Girdwood Cc: linux-samsung-soc@vger.kernel.org --- drivers/mtd/nand/s3c2410.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 91121f33f743..d8040619ad8d 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -46,7 +46,7 @@ #include #include -#include +#include #ifdef CONFIG_MTD_NAND_S3C2410_HWECC static int hardware_ecc = 1; -- cgit v1.2.3 From e27e35ec735fa78c976d30304f852cd2e02c5d1f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 19 Sep 2012 10:33:43 -0700 Subject: ARM: OMAP1: Move board-ams-delta.h from plat to mach This is only used by omap1. And to fix things properly, this should not be included from the drivers at all. Acked-by: Janusz Krzysztofik Cc: Tomi Valkeinen Cc: linux-fbdev@vger.kernel.org Cc: Artem Bityutskiy Cc: linux-mtd@lists.infradead.org Cc: Dmitry Torokhov Cc: linux-input@vger.kernel.org Cc: Peter Ujfalusi Cc: Liam Girdwood Acked-by: Mark Brown Cc: alsa-devel@alsa-project.org Signed-off-by: Tony Lindgren --- drivers/mtd/nand/ams-delta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c index 78a524b49357..a7040af08536 100644 --- a/drivers/mtd/nand/ams-delta.c +++ b/drivers/mtd/nand/ams-delta.c @@ -29,7 +29,7 @@ #include #include -#include +#include #include -- cgit v1.2.3 From 10bfa766efa19c23f72f50727952a26cb1512256 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 13 Sep 2012 14:24:49 +0530 Subject: driver/mtd:IFC NAND:Initialise internal SRAM before any write IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for SRAM i.e. "byte select" is not supported. Hence Read Modify Write is implemented in IFC for any "system side write" into sram buffer. Reading an uninitialized memory results in ECC Error from sram wrapper. Hence we must initialize/prefill SRAM buffer by any data before writing anything in SRAM from system side. To initialize SRAM user can use "READID" NAND command with read bytes equal to SRAM size. It will be a one time activity post boot. Signed-off-by: Prabhakar Kushwaha Acked-by: Artem Bityutskiy Signed-off-by: Kumar Gala --- drivers/mtd/nand/fsl_ifc_nand.c | 56 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 9602c1b7e27e..01e2f2e87d8c 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -31,6 +31,7 @@ #include #include +#define FSL_IFC_V1_1_0 0x01010000 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait @@ -773,13 +774,62 @@ static int fsl_ifc_chip_init_tail(struct mtd_info *mtd) return 0; } +static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) +{ + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + struct fsl_ifc_regs __iomem *ifc = ctrl->regs; + uint32_t csor = 0, csor_8k = 0, csor_ext = 0; + uint32_t cs = priv->bank; + + /* Save CSOR and CSOR_ext */ + csor = in_be32(&ifc->csor_cs[cs].csor); + csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext); + + /* chage PageSize 8K and SpareSize 1K*/ + csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; + out_be32(&ifc->csor_cs[cs].csor, csor_8k); + out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400); + + /* READID */ + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + out_be32(&ifc->ifc_nand.row3, 0x0); + + out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + + /* Program ROW0/COL0 */ + out_be32(&ifc->ifc_nand.row0, 0x0); + out_be32(&ifc->ifc_nand.col0, 0x0); + + /* set the chip select for NAND Transaction */ + out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT); + + /* start read seq */ + out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + + /* wait for command complete flag or timeout */ + wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, + IFC_TIMEOUT_MSECS * HZ/1000); + + if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) + printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); + + /* Restore CSOR and CSOR_ext */ + out_be32(&ifc->csor_cs[cs].csor, csor); + out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext); +} + static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) { struct fsl_ifc_ctrl *ctrl = priv->ctrl; struct fsl_ifc_regs __iomem *ifc = ctrl->regs; struct nand_chip *chip = &priv->chip; struct nand_ecclayout *layout; - u32 csor; + u32 csor, ver; /* Fill in fsl_ifc_mtd structure */ priv->mtd.priv = chip; @@ -874,6 +924,10 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) chip->ecc.mode = NAND_ECC_SOFT; } + ver = in_be32(&ifc->ifc_rev); + if (ver == FSL_IFC_V1_1_0) + fsl_ifc_sram_init(priv); + return 0; } -- cgit v1.2.3