From cede2f899d8f85baea32ff2e8a89a97aaac339b9 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Wed, 27 Feb 2019 18:14:22 +0200 Subject: iio: imu: adis16480: Add support for configurable drdy indicator The FNCTIO_CTRL register provides configuration control for each I/O pin (DIO1, DIO2, DIO3 and DIO4). This patch adds the option to configure each DIOx pin as data ready indicator with positive or negative polarity by reading the 'interrupts' and 'interrupt-names' properties from the devicetree. The 'interrupt-names' property is optional, if it is not specified, then the DIO1 pin is used as default data ready signal. Although the factory default assigns DIO2 as data ready signal, in the versions previous this patch, DIO1 pin was used. We should leave this configuration as is, since some devices might be expecting the interrupt on the wrong physical pin. Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 97 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 2 deletions(-) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index a27fe208f3ae..98a23ac50266 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -9,6 +9,8 @@ * */ +#include +#include #include #include #include @@ -107,6 +109,14 @@ #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) +/* ADIS16480_REG_FNCTIO_CTRL */ +#define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) +#define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) +#define ADIS16480_DRDY_POL_MSK BIT(2) +#define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) +#define ADIS16480_DRDY_EN_MSK BIT(3) +#define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) + struct adis16480_chip_info { unsigned int num_channels; const struct iio_chan_spec *channels; @@ -116,12 +126,26 @@ struct adis16480_chip_info { unsigned int accel_max_scale; }; +enum adis16480_int_pin { + ADIS16480_PIN_DIO1, + ADIS16480_PIN_DIO2, + ADIS16480_PIN_DIO3, + ADIS16480_PIN_DIO4 +}; + struct adis16480 { const struct adis16480_chip_info *chip_info; struct adis adis; }; +static const char * const adis16480_int_pin_names[4] = { + [ADIS16480_PIN_DIO1] = "DIO1", + [ADIS16480_PIN_DIO2] = "DIO2", + [ADIS16480_PIN_DIO3] = "DIO3", + [ADIS16480_PIN_DIO4] = "DIO4", +}; + #ifdef CONFIG_DEBUG_FS static ssize_t adis16480_show_firmware_revision(struct file *file, @@ -741,8 +765,17 @@ static int adis16480_stop_device(struct iio_dev *indio_dev) static int adis16480_enable_irq(struct adis *adis, bool enable) { - return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, - enable ? BIT(3) : 0); + uint16_t val; + int ret; + + ret = adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); + if (ret < 0) + return ret; + + val &= ~ADIS16480_DRDY_EN_MSK; + val |= ADIS16480_DRDY_EN(enable); + + return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); } static int adis16480_initial_setup(struct iio_dev *indio_dev) @@ -826,6 +859,62 @@ static const struct adis_data adis16480_data = { .enable_irq = adis16480_enable_irq, }; +static int adis16480_config_irq_pin(struct device_node *of_node, + struct adis16480 *st) +{ + struct irq_data *desc; + enum adis16480_int_pin pin; + unsigned int irq_type; + uint16_t val; + int i, irq = 0; + + desc = irq_get_irq_data(st->adis.spi->irq); + if (!desc) { + dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); + return -EINVAL; + } + + /* Disable data ready since the default after reset is on */ + val = ADIS16480_DRDY_EN(0); + + /* + * Get the interrupt from the devicetre by reading the interrupt-names + * property. If it is not specified, use DIO1 pin as default. + * According to the datasheet, the factory default assigns DIO2 as data + * ready signal. However, in the previous versions of the driver, DIO1 + * pin was used. So, we should leave it as is since some devices might + * be expecting the interrupt on the wrong physical pin. + */ + pin = ADIS16480_PIN_DIO1; + for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { + irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); + if (irq > 0) { + pin = i; + break; + } + } + + val |= ADIS16480_DRDY_SEL(pin); + + /* + * Get the interrupt line behaviour. The data ready polarity can be + * configured as positive or negative, corresponding to + * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively. + */ + irq_type = irqd_get_trigger_type(desc); + if (irq_type == IRQF_TRIGGER_RISING) { /* Default */ + val |= ADIS16480_DRDY_POL(1); + } else if (irq_type == IRQF_TRIGGER_FALLING) { + val |= ADIS16480_DRDY_POL(0); + } else { + dev_err(&st->adis.spi->dev, + "Invalid interrupt type 0x%x specified\n", irq_type); + return -EINVAL; + } + /* Write the data ready configuration to the FNCTIO_CTRL register */ + return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); +} + static int adis16480_probe(struct spi_device *spi) { const struct spi_device_id *id = spi_get_device_id(spi); @@ -853,6 +942,10 @@ static int adis16480_probe(struct spi_device *spi) if (ret) return ret; + ret = adis16480_config_irq_pin(spi->dev.of_node, st); + if (ret) + return ret; + ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); if (ret) return ret; -- cgit v1.2.3 From 304840c476ee84ef21f57f284922040ab0d0ce41 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Wed, 27 Feb 2019 18:14:23 +0200 Subject: iio: imu: adis16480: Add OF device ID table The driver does not have a struct of_device_id table, but supported devices are registered via Device Trees. This patch adds OF device ID table. Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index 98a23ac50266..150d814aee29 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -991,9 +991,19 @@ static const struct spi_device_id adis16480_ids[] = { }; MODULE_DEVICE_TABLE(spi, adis16480_ids); +static const struct of_device_id adis16480_of_match[] = { + { .compatible = "adi,adis16375" }, + { .compatible = "adi,adis16480" }, + { .compatible = "adi,adis16485" }, + { .compatible = "adi,adis16488" }, + { }, +}; +MODULE_DEVICE_TABLE(of, adis16480_of_match); + static struct spi_driver adis16480_driver = { .driver = { .name = "adis16480", + .of_match_table = adis16480_of_match, }, .id_table = adis16480_ids, .probe = adis16480_probe, -- cgit v1.2.3 From 6cf7b866bdd5cfbeb401cb65b928ebd46440490d Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Wed, 27 Feb 2019 18:14:24 +0200 Subject: iio: imu: adis16480: Treat temperature scale in a generic way All supported devices provide internal temperature measurement from -40 C to +85 C, with +25 C representing value 0x00. This patch treats the temperature scale in a generic way, similar to the accelerometer and gyroscope scales. So far, there are no temperature max scale differences between the supported devices. However, devices that will make use of this feature will be added in the future. Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index 150d814aee29..5a2864abfc3d 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -124,6 +124,7 @@ struct adis16480_chip_info { unsigned int gyro_max_scale; unsigned int accel_max_val; unsigned int accel_max_scale; + unsigned int temp_scale; }; enum adis16480_int_pin { @@ -530,6 +531,7 @@ static int adis16480_read_raw(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, int *val, int *val2, long info) { struct adis16480 *st = iio_priv(indio_dev); + unsigned int temp; switch (info) { case IIO_CHAN_INFO_RAW: @@ -549,8 +551,13 @@ static int adis16480_read_raw(struct iio_dev *indio_dev, *val2 = 100; /* 0.0001 gauss */ return IIO_VAL_INT_PLUS_MICRO; case IIO_TEMP: - *val = 5; - *val2 = 650000; /* 5.65 milli degree Celsius */ + /* + * +85 degrees Celsius = temp_max_scale + * +25 degrees Celsius = 0 + * LSB, 25 degrees Celsius = 60 / temp_max_scale + */ + *val = st->chip_info->temp_scale / 1000; + *val2 = (st->chip_info->temp_scale % 1000) * 1000; return IIO_VAL_INT_PLUS_MICRO; case IIO_PRESSURE: *val = 0; @@ -561,7 +568,8 @@ static int adis16480_read_raw(struct iio_dev *indio_dev, } case IIO_CHAN_INFO_OFFSET: /* Only the temperature channel has a offset */ - *val = 4425; /* 25 degree Celsius = 0x0000 */ + temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ + *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); return IIO_VAL_INT; case IIO_CHAN_INFO_CALIBBIAS: return adis16480_get_calibbias(indio_dev, chan, val); @@ -717,6 +725,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .gyro_max_scale = 300, .accel_max_val = IIO_M_S_2_TO_G(21973), .accel_max_scale = 18, + .temp_scale = 5650, /* 5.65 milli degree Celsius */ }, [ADIS16480] = { .channels = adis16480_channels, @@ -725,6 +734,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .gyro_max_scale = 450, .accel_max_val = IIO_M_S_2_TO_G(12500), .accel_max_scale = 10, + .temp_scale = 5650, /* 5.65 milli degree Celsius */ }, [ADIS16485] = { .channels = adis16485_channels, @@ -733,6 +743,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .gyro_max_scale = 450, .accel_max_val = IIO_M_S_2_TO_G(20000), .accel_max_scale = 5, + .temp_scale = 5650, /* 5.65 milli degree Celsius */ }, [ADIS16488] = { .channels = adis16480_channels, @@ -741,6 +752,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .gyro_max_scale = 450, .accel_max_val = IIO_M_S_2_TO_G(22500), .accel_max_scale = 18, + .temp_scale = 5650, /* 5.65 milli degree Celsius */ }, }; -- cgit v1.2.3 From e0e6398e1e4e27b06307457be8a85a7a5c0f9ef0 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Wed, 27 Feb 2019 18:14:25 +0200 Subject: iio: imu: adis16480: Calculate the sampling frequency in a generic way The adis1648x devices have an internal clock of 2.46 kSPS. The sampling frequency is calculated by applying a decimation rate which can take the maximum value of 2047. Although all adis1648x devices are similar in this regard, devices that will use this feature will be added in the future. Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index 5a2864abfc3d..92abc95d31dc 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -125,6 +125,8 @@ struct adis16480_chip_info { unsigned int accel_max_val; unsigned int accel_max_scale; unsigned int temp_scale; + unsigned int int_clk; + unsigned int max_dec_rate; }; enum adis16480_int_pin { @@ -299,9 +301,9 @@ static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) if (t <= 0) return -EINVAL; - t = 2460000 / t; - if (t > 2048) - t = 2048; + t = st->chip_info->int_clk / t; + if (t > st->chip_info->max_dec_rate) + t = st->chip_info->max_dec_rate; if (t != 0) t--; @@ -320,7 +322,7 @@ static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) if (ret < 0) return ret; - freq = 2460000 / (t + 1); + freq = st->chip_info->int_clk / (t + 1); *val = freq / 1000; *val2 = (freq % 1000) * 1000; @@ -726,6 +728,8 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .accel_max_val = IIO_M_S_2_TO_G(21973), .accel_max_scale = 18, .temp_scale = 5650, /* 5.65 milli degree Celsius */ + .int_clk = 2460000, + .max_dec_rate = 2048, }, [ADIS16480] = { .channels = adis16480_channels, @@ -735,6 +739,8 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .accel_max_val = IIO_M_S_2_TO_G(12500), .accel_max_scale = 10, .temp_scale = 5650, /* 5.65 milli degree Celsius */ + .int_clk = 2460000, + .max_dec_rate = 2048, }, [ADIS16485] = { .channels = adis16485_channels, @@ -744,6 +750,8 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .accel_max_val = IIO_M_S_2_TO_G(20000), .accel_max_scale = 5, .temp_scale = 5650, /* 5.65 milli degree Celsius */ + .int_clk = 2460000, + .max_dec_rate = 2048, }, [ADIS16488] = { .channels = adis16480_channels, @@ -753,6 +761,8 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .accel_max_val = IIO_M_S_2_TO_G(22500), .accel_max_scale = 18, .temp_scale = 5650, /* 5.65 milli degree Celsius */ + .int_clk = 2460000, + .max_dec_rate = 2048, }, }; -- cgit v1.2.3 From 83ec2d5404bfdf3aa67abfc594d0e6118d16ac06 Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Wed, 27 Feb 2019 18:14:26 +0200 Subject: iio: imu: adis16480: Deal with filter freq in a generic way When setting the filter frequency, the driver looks into the adis16480_def_filter_freqs table for the best match. Pass this table to the chip_info struct since future devices will need to use a different table. Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index 92abc95d31dc..c90375da8129 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -127,6 +127,7 @@ struct adis16480_chip_info { unsigned int temp_scale; unsigned int int_clk; unsigned int max_dec_rate; + const unsigned int *filter_freqs; }; enum adis16480_int_pin { @@ -483,7 +484,7 @@ static int adis16480_get_filter_freq(struct iio_dev *indio_dev, if (!(val & enable_mask)) *freq = 0; else - *freq = adis16480_def_filter_freqs[(val >> offset) & 0x3]; + *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; return IIO_VAL_INT; } @@ -510,10 +511,10 @@ static int adis16480_set_filter_freq(struct iio_dev *indio_dev, val &= ~enable_mask; } else { best_freq = 0; - best_diff = 310; + best_diff = st->chip_info->filter_freqs[0]; for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { - if (adis16480_def_filter_freqs[i] >= freq) { - diff = adis16480_def_filter_freqs[i] - freq; + if (st->chip_info->filter_freqs[i] >= freq) { + diff = st->chip_info->filter_freqs[i] - freq; if (diff < best_diff) { best_diff = diff; best_freq = i; @@ -730,6 +731,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .temp_scale = 5650, /* 5.65 milli degree Celsius */ .int_clk = 2460000, .max_dec_rate = 2048, + .filter_freqs = adis16480_def_filter_freqs, }, [ADIS16480] = { .channels = adis16480_channels, @@ -741,6 +743,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .temp_scale = 5650, /* 5.65 milli degree Celsius */ .int_clk = 2460000, .max_dec_rate = 2048, + .filter_freqs = adis16480_def_filter_freqs, }, [ADIS16485] = { .channels = adis16485_channels, @@ -752,6 +755,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .temp_scale = 5650, /* 5.65 milli degree Celsius */ .int_clk = 2460000, .max_dec_rate = 2048, + .filter_freqs = adis16480_def_filter_freqs, }, [ADIS16488] = { .channels = adis16480_channels, @@ -763,6 +767,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .temp_scale = 5650, /* 5.65 milli degree Celsius */ .int_clk = 2460000, .max_dec_rate = 2048, + .filter_freqs = adis16480_def_filter_freqs, }, }; -- cgit v1.2.3 From 82e7a1b2501709cce9294b744224e70cc3be96cd Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Wed, 27 Feb 2019 18:14:27 +0200 Subject: iio: imu: adis16480: Add support for ADIS1649x family of devices The ADIS16495 and ADIS16497 are inertial systems that include a triaxis gyroscope and a triaxis accelerometer. The serial peripheral interface (SPI) provide a simple interface for data collection and configuration control. The devices are similar to ADIS16475, ADIS16480, ADIS16485 and ADIS16488, the main differences are highlighted below: * The temperature data scale is 0.00565 C/LSB for ADIS16475 and ADIS1648x devices, while for ADIS1649x 0.0125 C/LSB. * ADIS1649x devices support different gyroscope measurement ranges which are dependent on the dash number (-1, -2, -3), see Table 24 in the ADIS16495 datasheet. However, the ADIS16497 gyroscopes have the same scale as ADIS16495. * ADIS16495 devices support the acceleration maximum range of 8g, while ADIS16497 devices go up to 40g. * The internal clock for ADIS1649x devices is 4.25 kSPS. The sampling frequency is calculated by applying a decimation rate which can take a maximum value of 4250. * ADIS1649x devices support different default filter frequencies. Datasheets: Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adis16495.pdf Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adis16497.pdf Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 97 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index c90375da8129..28cece3cc868 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -453,6 +453,13 @@ static const unsigned int adis16480_def_filter_freqs[] = { 63, }; +static const unsigned int adis16495_def_filter_freqs[] = { + 300, + 100, + 300, + 100, +}; + static const unsigned int ad16480_filter_data[][2] = { [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, @@ -713,6 +720,12 @@ enum adis16480_variant { ADIS16480, ADIS16485, ADIS16488, + ADIS16495_1, + ADIS16495_2, + ADIS16495_3, + ADIS16497_1, + ADIS16497_2, + ADIS16497_3, }; static const struct adis16480_chip_info adis16480_chip_info[] = { @@ -769,6 +782,78 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .max_dec_rate = 2048, .filter_freqs = adis16480_def_filter_freqs, }, + [ADIS16495_1] = { + .channels = adis16485_channels, + .num_channels = ARRAY_SIZE(adis16485_channels), + .gyro_max_val = IIO_RAD_TO_DEGREE(20000), + .gyro_max_scale = 125, + .accel_max_val = IIO_M_S_2_TO_G(32000), + .accel_max_scale = 8, + .temp_scale = 12500, /* 12.5 milli degree Celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + }, + [ADIS16495_2] = { + .channels = adis16485_channels, + .num_channels = ARRAY_SIZE(adis16485_channels), + .gyro_max_val = IIO_RAD_TO_DEGREE(18000), + .gyro_max_scale = 450, + .accel_max_val = IIO_M_S_2_TO_G(32000), + .accel_max_scale = 8, + .temp_scale = 12500, /* 12.5 milli degree Celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + }, + [ADIS16495_3] = { + .channels = adis16485_channels, + .num_channels = ARRAY_SIZE(adis16485_channels), + .gyro_max_val = IIO_RAD_TO_DEGREE(20000), + .gyro_max_scale = 2000, + .accel_max_val = IIO_M_S_2_TO_G(32000), + .accel_max_scale = 8, + .temp_scale = 12500, /* 12.5 milli degree Celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + }, + [ADIS16497_1] = { + .channels = adis16485_channels, + .num_channels = ARRAY_SIZE(adis16485_channels), + .gyro_max_val = IIO_RAD_TO_DEGREE(20000), + .gyro_max_scale = 125, + .accel_max_val = IIO_M_S_2_TO_G(32000), + .accel_max_scale = 40, + .temp_scale = 12500, /* 12.5 milli degree Celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + }, + [ADIS16497_2] = { + .channels = adis16485_channels, + .num_channels = ARRAY_SIZE(adis16485_channels), + .gyro_max_val = IIO_RAD_TO_DEGREE(18000), + .gyro_max_scale = 450, + .accel_max_val = IIO_M_S_2_TO_G(32000), + .accel_max_scale = 40, + .temp_scale = 12500, /* 12.5 milli degree Celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + }, + [ADIS16497_3] = { + .channels = adis16485_channels, + .num_channels = ARRAY_SIZE(adis16485_channels), + .gyro_max_val = IIO_RAD_TO_DEGREE(20000), + .gyro_max_scale = 2000, + .accel_max_val = IIO_M_S_2_TO_G(32000), + .accel_max_scale = 40, + .temp_scale = 12500, /* 12.5 milli degree Celsius */ + .int_clk = 4250000, + .max_dec_rate = 4250, + .filter_freqs = adis16495_def_filter_freqs, + }, }; static const struct iio_info adis16480_info = { @@ -1014,6 +1099,12 @@ static const struct spi_device_id adis16480_ids[] = { { "adis16480", ADIS16480 }, { "adis16485", ADIS16485 }, { "adis16488", ADIS16488 }, + { "adis16495-1", ADIS16495_1 }, + { "adis16495-2", ADIS16495_2 }, + { "adis16495-3", ADIS16495_3 }, + { "adis16497-1", ADIS16497_1 }, + { "adis16497-2", ADIS16497_2 }, + { "adis16497-3", ADIS16497_3 }, { } }; MODULE_DEVICE_TABLE(spi, adis16480_ids); @@ -1023,6 +1114,12 @@ static const struct of_device_id adis16480_of_match[] = { { .compatible = "adi,adis16480" }, { .compatible = "adi,adis16485" }, { .compatible = "adi,adis16488" }, + { .compatible = "adi,adis16495-1" }, + { .compatible = "adi,adis16495-2" }, + { .compatible = "adi,adis16495-3" }, + { .compatible = "adi,adis16497-1" }, + { .compatible = "adi,adis16497-2" }, + { .compatible = "adi,adis16497-3" }, { }, }; MODULE_DEVICE_TABLE(of, adis16480_of_match); -- cgit v1.2.3 From 326e2357553d39769aacf737fd19650f2d81671a Mon Sep 17 00:00:00 2001 From: Stefan Popa Date: Mon, 11 Mar 2019 11:45:29 +0200 Subject: iio: imu: adis16480: Add support for external clock Inertial sensor data collection and processing can be controlled by configuring one of the DIOx lines as an external clock input. This option is available for all devices supported by this driver. However, only adis1649x devices support different modes for the external clock. Sync mode is supported by all devices. In this mode, the output data rate is equal with the clock frequency divided by DEC_RATE + 1. This mode of calculation is similar with the case when the internal clock is used. Pulse Per Second (PPS) Mode, is only supported by adis1649x devices. In this mode, the output data rate is equal to the product of the external clock frequency and the scale factor in the SYNC_SCALE register. This patch uses the "clock-names" property to enable the external clock in one of the two supported modes: "sync" or "pps". This property is optional. If it is not specified, the internal clock is used. This patch also offers the option to select the DIOx line to be used as an external clock input via the custom "adi,ext-clk-pin" property. If this field is left empty, DIO2 is assigned as default external clock input pin. Each DIOx pin supports only one function at a time (data ready line selection or external clock input). Signed-off-by: Stefan Popa Signed-off-by: Jonathan Cameron --- drivers/iio/imu/adis16480.c | 186 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 179 insertions(+), 7 deletions(-) (limited to 'drivers/iio/imu/adis16480.c') diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c index 28cece3cc868..ab137c1bbe7b 100644 --- a/drivers/iio/imu/adis16480.c +++ b/drivers/iio/imu/adis16480.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include @@ -99,6 +100,12 @@ #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) +/* + * External clock scaling in PPS mode. + * Available only for ADIS1649x devices + */ +#define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) + #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) /* Each filter coefficent bank spans two pages */ @@ -116,6 +123,12 @@ #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) #define ADIS16480_DRDY_EN_MSK BIT(3) #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) +#define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) +#define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) +#define ADIS16480_SYNC_EN_MSK BIT(7) +#define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) +#define ADIS16480_SYNC_MODE_MSK BIT(8) +#define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) struct adis16480_chip_info { unsigned int num_channels; @@ -128,6 +141,7 @@ struct adis16480_chip_info { unsigned int int_clk; unsigned int max_dec_rate; const unsigned int *filter_freqs; + bool has_pps_clk_mode; }; enum adis16480_int_pin { @@ -137,10 +151,19 @@ enum adis16480_int_pin { ADIS16480_PIN_DIO4 }; +enum adis16480_clock_mode { + ADIS16480_CLK_SYNC, + ADIS16480_CLK_PPS, + ADIS16480_CLK_INT +}; + struct adis16480 { const struct adis16480_chip_info *chip_info; struct adis adis; + struct clk *ext_clk; + enum adis16480_clock_mode clk_mode; + unsigned int clk_freq; }; static const char * const adis16480_int_pin_names[4] = { @@ -296,20 +319,34 @@ static int adis16480_debugfs_init(struct iio_dev *indio_dev) static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) { struct adis16480 *st = iio_priv(indio_dev); - unsigned int t; + unsigned int t, reg; t = val * 1000 + val2 / 1000; if (t <= 0) return -EINVAL; - t = st->chip_info->int_clk / t; + /* + * When using PPS mode, the rate of data collection is equal to the + * product of the external clock frequency and the scale factor in the + * SYNC_SCALE register. + * When using sync mode, or internal clock, the output data rate is + * equal with the clock frequency divided by DEC_RATE + 1. + */ + if (st->clk_mode == ADIS16480_CLK_PPS) { + t = t / st->clk_freq; + reg = ADIS16495_REG_SYNC_SCALE; + } else { + t = st->clk_freq / t; + reg = ADIS16480_REG_DEC_RATE; + } + if (t > st->chip_info->max_dec_rate) t = st->chip_info->max_dec_rate; - if (t != 0) + if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) t--; - return adis_write_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, t); + return adis_write_reg_16(&st->adis, reg, t); } static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) @@ -318,12 +355,29 @@ static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) uint16_t t; int ret; unsigned freq; + unsigned int reg; + + if (st->clk_mode == ADIS16480_CLK_PPS) + reg = ADIS16495_REG_SYNC_SCALE; + else + reg = ADIS16480_REG_DEC_RATE; - ret = adis_read_reg_16(&st->adis, ADIS16480_REG_DEC_RATE, &t); + ret = adis_read_reg_16(&st->adis, reg, &t); if (ret < 0) return ret; - freq = st->chip_info->int_clk / (t + 1); + /* + * When using PPS mode, the rate of data collection is equal to the + * product of the external clock frequency and the scale factor in the + * SYNC_SCALE register. + * When using sync mode, or internal clock, the output data rate is + * equal with the clock frequency divided by DEC_RATE + 1. + */ + if (st->clk_mode == ADIS16480_CLK_PPS) + freq = st->clk_freq * t; + else + freq = st->clk_freq / (t + 1); + *val = freq / 1000; *val2 = (freq % 1000) * 1000; @@ -793,6 +847,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .int_clk = 4250000, .max_dec_rate = 4250, .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, }, [ADIS16495_2] = { .channels = adis16485_channels, @@ -805,6 +860,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .int_clk = 4250000, .max_dec_rate = 4250, .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, }, [ADIS16495_3] = { .channels = adis16485_channels, @@ -817,6 +873,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .int_clk = 4250000, .max_dec_rate = 4250, .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, }, [ADIS16497_1] = { .channels = adis16485_channels, @@ -829,6 +886,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .int_clk = 4250000, .max_dec_rate = 4250, .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, }, [ADIS16497_2] = { .channels = adis16485_channels, @@ -841,6 +899,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .int_clk = 4250000, .max_dec_rate = 4250, .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, }, [ADIS16497_3] = { .channels = adis16485_channels, @@ -853,6 +912,7 @@ static const struct adis16480_chip_info adis16480_chip_info[] = { .int_clk = 4250000, .max_dec_rate = 4250, .filter_freqs = adis16495_def_filter_freqs, + .has_pps_clk_mode = true, }, }; @@ -1027,6 +1087,100 @@ static int adis16480_config_irq_pin(struct device_node *of_node, return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); } +static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, + struct device_node *of_node) +{ + const char *ext_clk_pin; + enum adis16480_int_pin pin; + int i; + + pin = ADIS16480_PIN_DIO2; + if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) + goto clk_input_not_found; + + for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { + if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) + return i; + } + +clk_input_not_found: + dev_info(&st->adis.spi->dev, + "clk input line not specified, using DIO2\n"); + return pin; +} + +static int adis16480_ext_clk_config(struct adis16480 *st, + struct device_node *of_node, + bool enable) +{ + unsigned int mode, mask; + enum adis16480_int_pin pin; + uint16_t val; + int ret; + + ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); + if (ret < 0) + return ret; + + pin = adis16480_of_get_ext_clk_pin(st, of_node); + /* + * Each DIOx pin supports only one function at a time. When a single pin + * has two assignments, the enable bit for a lower priority function + * automatically resets to zero (disabling the lower priority function). + */ + if (pin == ADIS16480_DRDY_SEL(val)) + dev_warn(&st->adis.spi->dev, + "DIO%x pin supports only one function at a time\n", + pin + 1); + + mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); + mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; + /* Only ADIS1649x devices support pps ext clock mode */ + if (st->chip_info->has_pps_clk_mode) { + mode |= ADIS16480_SYNC_MODE(st->clk_mode); + mask |= ADIS16480_SYNC_MODE_MSK; + } + + val &= ~mask; + val |= mode; + + ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); + if (ret < 0) + return ret; + + return clk_prepare_enable(st->ext_clk); +} + +static int adis16480_get_ext_clocks(struct adis16480 *st) +{ + st->clk_mode = ADIS16480_CLK_INT; + st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); + if (!IS_ERR_OR_NULL(st->ext_clk)) { + st->clk_mode = ADIS16480_CLK_SYNC; + return 0; + } + + if (PTR_ERR(st->ext_clk) != -ENOENT) { + dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); + return PTR_ERR(st->ext_clk); + } + + if (st->chip_info->has_pps_clk_mode) { + st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); + if (!IS_ERR_OR_NULL(st->ext_clk)) { + st->clk_mode = ADIS16480_CLK_PPS; + return 0; + } + + if (PTR_ERR(st->ext_clk) != -ENOENT) { + dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); + return PTR_ERR(st->ext_clk); + } + } + + return 0; +} + static int adis16480_probe(struct spi_device *spi) { const struct spi_device_id *id = spi_get_device_id(spi); @@ -1058,10 +1212,25 @@ static int adis16480_probe(struct spi_device *spi) if (ret) return ret; - ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); + ret = adis16480_get_ext_clocks(st); if (ret) return ret; + if (!IS_ERR_OR_NULL(st->ext_clk)) { + ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); + if (ret) + return ret; + + st->clk_freq = clk_get_rate(st->ext_clk); + st->clk_freq *= 1000; /* micro */ + } else { + st->clk_freq = st->chip_info->int_clk; + } + + ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); + if (ret) + goto error_clk_disable_unprepare; + ret = adis16480_initial_setup(indio_dev); if (ret) goto error_cleanup_buffer; @@ -1078,6 +1247,8 @@ error_stop_device: adis16480_stop_device(indio_dev); error_cleanup_buffer: adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); +error_clk_disable_unprepare: + clk_disable_unprepare(st->ext_clk); return ret; } @@ -1090,6 +1261,7 @@ static int adis16480_remove(struct spi_device *spi) adis16480_stop_device(indio_dev); adis_cleanup_buffer_and_trigger(&st->adis, indio_dev); + clk_disable_unprepare(st->ext_clk); return 0; } -- cgit v1.2.3