From d66f3f0e10b49df8d0cc0d8eb5bf2ef9863a33cf Mon Sep 17 00:00:00 2001 From: Ganesan Ramalingam Date: Fri, 9 May 2014 16:35:49 +0530 Subject: MIPS: Add MSI support for XLP9XX In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX. Update XLP MSI/MSI-X code to handle this. Signed-off-by: Ganesan Ramalingam Signed-off-by: Jayachandran C Cc: g@linux-mips.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6912/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/netlogic/xlp-hal/xlp.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/mips/include/asm/netlogic/xlp-hal/xlp.h') diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h index 62d19871b983..a862b93223cc 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h @@ -70,8 +70,9 @@ #define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */ #define PIC_PCIE_MSIX_IRQ(i) (48 + (i)) -#define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */ -#define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */ +/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */ +#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */ +#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */ #define NLM_PIC_INDIRECT_VEC_BASE 512 #define NLM_GPIO_VEC_BASE 768 -- cgit v1.2.3