From 383af9c2586e0c51e27ed4f186a2f23f8e889054 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 3 Nov 2009 14:42:07 +0000 Subject: ARM: S3C64XX: Provide logging when CPU frequencies are eliminated due to clocks This provides symmetry with the voltage based checks done for the regulator. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/cpufreq.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c index e6e0843215df..bdc3c96971f5 100644 --- a/arch/arm/plat-s3c64xx/cpufreq.c +++ b/arch/arm/plat-s3c64xx/cpufreq.c @@ -217,8 +217,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) /* Check for frequencies we can generate */ r = clk_round_rate(armclk, freq->frequency * 1000); r /= 1000; - if (r != freq->frequency) + if (r != freq->frequency) { + pr_debug("cpufreq: %dkHz unsupported by clock\n", + freq->frequency); freq->frequency = CPUFREQ_ENTRY_INVALID; + } /* If we have no regulator then assume startup * frequency is the maximum we can support. */ -- cgit v1.2.3 From 43f1069ef9af9a0b1fa1a1d6b49b2b05e1efc998 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 3 Nov 2009 14:42:11 +0000 Subject: ARM: S3C64XX: Separate out regulator and frequency latencies Currently the transition latency reported by the S3C64xx cpufreq driver includes both the time for the CPU to reclock itself and the time for a regulator to change voltage. This means that if a regulator is not in use then the transition latency reported is excessively high. In future the regulator API will be extended to report latencies so the driver will be able to query the performance of a given regulator. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/cpufreq.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c index bdc3c96971f5..61276bf73927 100644 --- a/arch/arm/plat-s3c64xx/cpufreq.c +++ b/arch/arm/plat-s3c64xx/cpufreq.c @@ -19,6 +19,7 @@ static struct clk *armclk; static struct regulator *vddarm; +static unsigned long regulator_latency; #ifdef CONFIG_CPU_S3C6410 struct s3c64xx_dvfs { @@ -141,7 +142,7 @@ err: } #ifdef CONFIG_REGULATOR -static void __init s3c64xx_cpufreq_constrain_voltages(void) +static void __init s3c64xx_cpufreq_config_regulator(void) { int count, v, i, found; struct cpufreq_frequency_table *freq; @@ -150,11 +151,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void) count = regulator_count_voltages(vddarm); if (count < 0) { pr_err("cpufreq: Unable to check supported voltages\n"); - return; } freq = s3c64xx_freq_table; - while (freq->frequency != CPUFREQ_TABLE_END) { + while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { if (freq->frequency == CPUFREQ_ENTRY_INVALID) continue; @@ -175,6 +175,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void) freq++; } + + /* Guess based on having to do an I2C/SPI write; in future we + * will be able to query the regulator performance here. */ + regulator_latency = 1 * 1000 * 1000; } #endif @@ -206,7 +210,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) pr_err("cpufreq: Only frequency scaling available\n"); vddarm = NULL; } else { - s3c64xx_cpufreq_constrain_voltages(); + s3c64xx_cpufreq_config_regulator(); } #endif @@ -233,9 +237,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) policy->cur = clk_get_rate(armclk) / 1000; - /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI - * write plus clock reprogramming. */ - policy->cpuinfo.transition_latency = 2 * 1000 * 1000; + /* Datasheet says PLL stabalisation time (if we were to use + * the PLLs, which we don't currently) is ~300us worst case, + * but add some fudge. + */ + policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency; ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); if (ret != 0) { -- cgit v1.2.3 From e9c08f0d5737a988e735f7371bc0bffb343c485c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 3 Nov 2009 14:42:12 +0000 Subject: ARM: S3C64XX: Redo voltage ranges for cpufreq The documentation for the S3C6410 CPU voltage scaling is rather unclear, with omitted values for several speed settings. Originally the code was using only quoted values, resulting in some fairly odd settings. The S3C6410 is also unusual in that the both the maximum and minimum voltages quoted scale as the frequency rises, rather than just the minimum voltage. Clean this up a bit by always using the specified typical settings as the minimum voltage (ignoring any specified minimum voltage) in order to avoid running near the edge of the processor capabilities. Also use the next quoted maximum voltages rather than the typical voltages where no maximum voltage is quoted, allowing operation on a greater range of systems. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/cpufreq.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c index 61276bf73927..74c0e8347de5 100644 --- a/arch/arm/plat-s3c64xx/cpufreq.c +++ b/arch/arm/plat-s3c64xx/cpufreq.c @@ -28,11 +28,10 @@ struct s3c64xx_dvfs { }; static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { - [0] = { 1000000, 1000000 }, - [1] = { 1000000, 1050000 }, - [2] = { 1050000, 1100000 }, - [3] = { 1050000, 1150000 }, - [4] = { 1250000, 1350000 }, + [0] = { 1000000, 1150000 }, + [1] = { 1050000, 1150000 }, + [2] = { 1100000, 1150000 }, + [3] = { 1200000, 1350000 }, }; static struct cpufreq_frequency_table s3c64xx_freq_table[] = { @@ -42,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = { { 1, 266000 }, { 2, 333000 }, { 2, 400000 }, - { 3, 532000 }, - { 3, 533000 }, - { 4, 667000 }, + { 2, 532000 }, + { 2, 533000 }, + { 3, 667000 }, { 0, CPUFREQ_TABLE_END }, }; #endif -- cgit v1.2.3 From 23196a42a691012ac9710677f711bb6dca0a1cde Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Fri, 20 Nov 2009 13:04:08 +0100 Subject: ARM: S3C64XX: fix USB OTG compilation This adds the S3C_VA_USB_HSPHY mapping. Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index b1fdd83940a6..49796d2db86d 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -107,6 +107,11 @@ static struct map_desc s3c_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_USB_HSPHY, + .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY), + .length = SZ_1K, + .type = MT_DEVICE, }, }; -- cgit v1.2.3 From 6a88e9838fdc9ede136e3bb76a5c19413bd6cddb Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Fri, 20 Nov 2009 13:04:13 +0100 Subject: ARM: S3C64XX: add support for all group 0 external interrupts Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/gpiolib.c | 12 ++++++++++++ arch/arm/plat-s3c64xx/irq-eint.c | 19 ++++++++++++++----- 2 files changed, 26 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 92859290ea33..778560457277 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -213,6 +213,11 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { .get_pull = s3c_gpio_getpull_updown, }; +int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin) +{ + return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; +} + static struct s3c_gpio_chip gpio_4bit[] = { { .base = S3C64XX_GPA_BASE, @@ -269,10 +274,16 @@ static struct s3c_gpio_chip gpio_4bit[] = { .base = S3C64XX_GPM(0), .ngpio = S3C64XX_GPIO_M_NR, .label = "GPM", + .to_irq = s3c64xx_gpio2int_gpm, }, }, }; +int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) +{ + return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; +} + static struct s3c_gpio_chip gpio_4bit2[] = { { .base = S3C64XX_GPH_BASE + 0x4, @@ -297,6 +308,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = { .base = S3C64XX_GPL(0), .ngpio = S3C64XX_GPIO_L_NR, .label = "GPL", + .to_irq = s3c64xx_gpio2int_gpl, }, }, }; diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index f81b7b818ba0..ebdf183a0911 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -65,7 +65,7 @@ static void s3c_irq_eint_maskack(unsigned int irq) static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) { int offs = eint_offset(irq); - int pin; + int pin, pin_val; int shift; u32 ctrl, mask; u32 newvalue = 0; @@ -109,7 +109,10 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) return -1; } - shift = (offs / 2) * 4; + if (offs <= 15) + shift = (offs / 2) * 4; + else + shift = ((offs - 16) / 2) * 4; mask = 0x7 << shift; ctrl = __raw_readl(reg); @@ -119,12 +122,18 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) /* set the GPIO pin appropriately */ - if (offs < 23) + if (offs < 16) { pin = S3C64XX_GPN(offs); - else + pin_val = S3C_GPIO_SFN(2); + } else if (offs < 23) { + pin = S3C64XX_GPL(offs + 8 - 16); + pin_val = S3C_GPIO_SFN(3); + } else { pin = S3C64XX_GPM(offs - 23); + pin_val = S3C_GPIO_SFN(3); + } - s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(pin, pin_val); return 0; } -- cgit v1.2.3 From 92b118f6968ae0788ac659af47b464acd9a754a1 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Mon, 23 Nov 2009 13:34:46 +0100 Subject: ARM: S3C64XX: add HSMMC2 support This adds support for the third SDHCI controller. Signed-off-by: Maurus Cuelenaere Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/setup-sdhci-gpio.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c index 5417123b0ac1..a58c0cc7ba5e 100644 --- a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c +++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c @@ -53,3 +53,23 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); } + +void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPH(6 + width); + + /* Set all the necessary GPH pins to special-function 1 */ + for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* Set all the necessary GPC pins to special-function 1 */ + for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} -- cgit v1.2.3 From 88d27041cf4d36e499e2c54b6c44d9115ccf124a Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 27 Nov 2009 16:43:54 +0000 Subject: ARM: S3C6410: Correct names of IISv4 data output pin definitions The naming of the defines suggests that there are three IISv4 ports with one data line each when in fact there is a single IISv4 port with three data lines. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h index c47daf7e2723..e22b49f4f982 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h @@ -36,18 +36,18 @@ #define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) #define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) -#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) +#define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16) #define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) #define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) #define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) -#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) +#define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20) #define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) #define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) #define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) #define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) -#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) +#define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28) #define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) -- cgit v1.2.3