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path: root/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
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* clk: tegra: dfll: Use builtin_platform_driver to simplify the codeWei Yongjun2016-11-101-6/+1
| | | | | | | Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modularPaul Gortmaker2016-11-041-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: arch/arm/mach-tegra/Kconfig:config ARCH_TEGRA_124_SOC arch/arm/mach-tegra/Kconfig: bool "Enable support for Tegra124 family" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tags etc. since all that information is already contained at the top of the file in the comments. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: linux-clk@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: dfll: Reformat CVB frequency tableThierry Reding2016-04-281-25/+25
| | | | | | | Increase the readability of the CVB frequency table by reformatting it a little. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: dfll: Properly clean up on failure and removalThierry Reding2016-04-281-4/+27
| | | | | | | | Upon failure to probe the DFLL, the OPP table will not be cleaned up properly. Fix this and while at it make sure the OPP table will also be cleared upon driver removal. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: dfll: Make code more comprehensibleThierry Reding2016-04-281-6/+5
| | | | | | | | Rename some variables and structure fields to make the code more comprehensible. Also change the prototype of internal functions to be more in line with the OPP core functions. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding2016-04-281-14/+9
| | | | | | | | Instead of copying parts of the CVB table into a separate structure, keep track of the selected CVB table and directly reference data from it. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen2015-07-161-0/+166
Add basic platform driver support for the fast CPU cluster DFLL clocksource found on Tegra124 SoCs. This small driver selects the appropriate Tegra124-specific characterization data and integration code. It relies on the DFLL common code to do most of the work. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> [treding@nvidia.com: move setup code into ->probe()] Signed-off-by: Thierry Reding <treding@nvidia.com>