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* ARM: dts: tegra: fix PCI bus dtc warningsRob Herring2017-06-131-1/+3
| | | | | | | | | | | dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Add Tegra20 GMI supportMirza Krak2016-11-071-0/+13
| | | | | | | | | | Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak <mirza.krak@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Correct interrupt type for ARM TWDJon Hunter2016-04-121-1/+1
| | | | | | | | | | | | | The ARM TWD interrupt is a private peripheral interrupt (PPI) and per the ARM GIC documentation, whether the type for PPIs can be set is IMPLEMENTATION DEFINED. For Tegra20/30 devices the PPI type cannot be set and so when we attempt to set the type for the ARM TWD interrupt it fails. This has gone unnoticed because it fails silently and because we cannot re-configure the type it has had no impact. Nevertheless fix the type for the TWD interrupt so that it matches the hardware configuration. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Fix copy/paste typo in several DTS includesRalf Ramsauer2016-04-121-1/+1
| | | | | | | | | | | | | The comment about the 8250 vs. APB DMA-enabled UART devices that was added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts: add aliases and DMA requestor for serial controller") introduced a typo that has since spread to various other DTS include files. Fix all occurrences of this typo. Signed-off-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de> Acked-by: Stephen Warren <swarren@nvidia.com> [treding@nvidia.com: amend subject, add commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-11-101-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
| * ARM: tegra: Whitespace clean-up for Tegra20/30/124Marcel Ziswiler2015-09-151-2/+2
| | | | | | | | | | | | | | | | | | There were a few cases of eight spaces being used instead of a tab character plus one case of using two spaces after an equal sign instead of just one which this patch fixes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | ARM: tegra: Comment out gpio-ranges propertiesThierry Reding2015-10-151-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the addition of these properties is technically correct it unveils a bug with deferred probe. The problem is that the presence of the gpio- range property causes the gpio-tegra driver to defer probe (it needs the pinctrl driver to be ready). That's technically correct, but it causes a couple of issues: - The keyboard on Chromebooks stops working. The reason for that is that the gpio-tegra device has not registered an IRQ domain by the time the EC SPI device is registered, hence the interrupt number resolves to 0. This is technically a bug in the SPI core, since it should really resolve the interrupt at probe time and defer if the IRQ domain isn't available yet. This is similar to what's done for I2C and platform device already. - The gpio-tegra device deferring probe means that it is moved to the end of the dpm_list. This list defines the suspend/resume order for devices. However the core lacks a way to move all users of the gpio-tegra device to the end of the dpm_list at the same time. This in turn results in a subtle bug on Jetson TK1, where the gpio-keys device is used to expose the power key as input. The power key is a convenient way to wake the system from suspend. Interestingly, the gpio-keys device ends up getting probed at a point after gpio-tegra has been probed successfully from having been deferred earlier. As such the driver doesn't need to defer the probe itself, and hence the device isn't moved to the end of the dpm_list. This causes the gpio-tegra device to be suspended before gpio-keys, which in turn leaves gpio-keys unable to wake the system from suspend. There are patches in the works to fix both of the above issues, but they are too involved to make it into v4.3, so in the meantime let's fix the regressions by commenting out the gpio-ranges properties until the fixes have landed. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: tegra: Add gpio-ranges propertyTomeu Vizoso2015-08-211-0/+1
| | | | | | | | | Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is explicit. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114Nicolas Chauvet2015-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | Current base address is wrong by 0x04 bytes for AHB bus device as shown in dmesg: tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround To correct old DTBs, commit ce7a10b0ff3d ("ARM: 8334/1: amba: tegra-ahb: detect and correct bogus base address") checks for the low bit of the base address and removes theses 0x04 bytes at runtime. This patch fixes the original DTS, so upstream version doesn't need the workaround of the base address. As both addresses are valid, this patch doesn't break compatibility. Tested on tegra20-paz00 (aka ac100). Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Use lower-case hexadecimal digitsThierry Reding2015-05-041-1/+1
| | | | | | | For consistency with other device tree content, use lower-case hexadecimal digits in register region specifications. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DTs to expose legacy interrupt controllerMarc Zyngier2015-03-151-1/+14
| | | | | | | | | Describe the legacy interrupt controller in every tegra DTSI files, and make it the parent of most interrupts. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-5-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: tegra: Fix unit address for Cortex-A9 TWD timerThierry Reding2015-01-091-1/+1
| | | | | | | The Cortex-A9 TWD timer has registers at address 0x50040600, but the unit address was 50004600, most likely a typo. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: dts: tegra20: fix GR3D, DSI unit and reg base addressesDmitry Osipenko2015-01-071-4/+4
| | | | | | | | | | | | | Commit 58ecb23f64ee ("ARM: tegra: add missing unit addresses to DT") added unit address and changed reg base for GR3D and DSI host1x modules, but these addresses belongs to GR2D and TVO modules respectively. Fix it by changing modules unit and reg base addresses to proper ones. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Fixes: 58ecb23f64ee (ARM: tegra: add missing unit addresses to DT) Cc: <stable@vger.kernel.org> # v3.13+ Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: dts: tegra: move serial aliases to per-boardOlof Johansson2014-11-131-8/+0
| | | | | | | | | | | | | | There are general changes pending to make the /aliases/serial* entries number the serial ports on the system. On Tegra, so far the ports have been just numbered dynamically as they are configured so that makes them change. To avoid this, add specific aliases per board to keep the old numbers. This allows us to change the numbering by default on future SoCs while keeping the numbering on existing boards. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Add device tree nodes for flow controllerThierry Reding2014-08-261-0/+5
| | | | | | | | These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'cleanup-for-3.17' of ↵Linus Torvalds2014-08-081-0/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This merge window brings a good size of cleanups on various platforms. Among the bigger ones: - Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. - OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. - Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. - Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc" * tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits) drivers: CCI: Correct use of ! and & video: clcd-versatile: Depend on ARM video: fix up versatile CLCD helper move MAINTAINERS: Add sdhci-st file to ARCH/STI architecture ARM: EXYNOS: Fix build breakge with PM_SLEEP=n MAINTAINERS: Remove Kirkwood ARM: tegra: Convert PMC to a driver soc/tegra: fuse: Set up in early initcall ARM: tegra: Always lock the CPU reset vector ARM: tegra: Setup CPU hotplug in a pure initcall soc/tegra: Implement runtime check for Tegra SoCs soc/tegra: fuse: fix dummy functions soc/tegra: fuse: move APB DMA into Tegra20 fuse driver soc/tegra: Add efuse and apbmisc bindings soc/tegra: Add efuse driver for Tegra ARM: tegra: move fuse exports to soc/tegra/fuse.h ARM: tegra: export apb dma readl/writel ARM: tegra: Use a function to get the chip ID ARM: tegra: Sort includes alphabetically ARM: tegra: Move includes to include/soc/tegra ...
| * soc/tegra: Add efuse and apbmisc bindingsPeter De Schrijver2014-07-171-0/+15
| | | | | | | | | | | | | | | | | | Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | ARM: tegra: Add resets & has-utmi-pad-registers flag to all USB PHYsTuomas Tynkkynen2014-07-091-0/+7
|/ | | | | | | | | | | | | Add new properties to all of the Tegra PHYs that are now required according to the binding. In order to stay compatible with old device trees, the USB drivers will still function without these reset properties but with the old, potentially buggy behaviour. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'tegra-for-3.15-dt' of ↵Olof Johansson2014-03-201-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Merge "ARM: tegra: device tree changes for 3.15" from Stephen Warren: This enables: - host1x and eDP support on Tegra124. - LCD panel support for a few Tegra20 devices and Venice2. - Enables power down, SPI flash, and USB on Venice2. - Documents which Dalmore revision is supported. - Adds an I2C bus mux to Cardhu. Additionally, Tegra124 is converted to use #address-cells=<2> since the HW suports more than 32-bits of address space, and various cleanups are included. * tag 'tegra-for-3.15-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (21 commits) ARM: dts: tegra: add PCIe interrupt mapping properties ARM: tegra: use 2 address cells for Tegra124 DT ARM: tegra: Rename as3722 node to pmic ARM: tegra: Fix whitespace around '=' ARM: tegra: Enable USB on Venice2 ARM: tegra: Add Tegra124 USB support ARM: tegra: Enable eDP for Venice2 ARM: tegra: Add Tegra124 eDP support ARM: tegra: Add Tegra124 host1x support ARM: tegra: Hook up SDMMC3 power-supply on Venice2 ARM: tegra: Overhaul Venice2 regulators ARM: tegra: Combine VBUS enable pins into one node ARM: tegra: Use "disabled" for status property ARM: tegra: add SPI flash to Venice2 DT ARM: tegra: enable PCA9546 on Cardhu ARM: tegra: enable LCD panel on Ventana ARM: tegra: enable LCD panel on Seaboard ARM: tegra: add system-power-controller property for PMIC node ARM: tegra: document which Dalmore revisions are supported ARM: tegra: Properly sort clocks property ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: dts: tegra: add PCIe interrupt mapping propertiesLucas Stach2014-03-061-0/+4
| | | | | | | | | | | | | | | | Those are defined by the common PCI binding. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add head numbers to display controllersThierry Reding2014-02-181-0/+4
|/ | | | | | | | | | The number of the head specifies the index of the display controller unit and is required to properly configure outputs so that they receive video data from the correct source. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl definesLaxman Dewangan2013-12-161-0/+1
| | | | | | | | Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra20 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add missing unit addresses to DTStephen Warren2013-12-161-27/+27
| | | | | | | | | | DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: remove legacy DMA entries from DTStephen Warren2013-12-111-13/+0
| | | | | | | | | Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: remove legacy clock entries from DTStephen Warren2013-12-111-2/+1
| | | | | | | | | Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add DMA propertiesStephen Warren2013-12-111-0/+35
| | | | | | | | | This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add reset propertiesStephen Warren2013-12-111-0/+81
| | | | | | | | | | | | An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add missing clock documentation to DT bindingsStephen Warren2013-12-111-2/+2
| | | | | | | | | | | | | Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
* Merge tag 'dt-for-linus' of ↵Linus Torvalds2013-09-061-0/+55
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "Device tree and bindings updates for 3.12. General additions of various on-chip and on-board peripherals on various platforms as support gets added. Some of the bigger changes are: - Addition of (new) PCI-e support on Tegra. - More Tegra4 support, including PMC configuration for Dalmore. - Addition of a new board for Exynos4 (trats2) and more bindings for 4x12 IP. - Addition of Allwinner A20 and A31 SoC and board files. - Move of the ST Ericsson device tree files to now use ste-* prefix. - More move of hardware description of shmobile platforms to DT. - Two new board dts files for Freescale MXs" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (177 commits) dts: Rename DW APB timer compatible strings dts: Deprecate ALTR as a vendor prefix of: add vendor prefix for Altera Corp. ARM: at91/dt: sam9x5ek: add sound configuration ARM: at91/dt: sam9x5ek: enable SSC ARM: at91/dt: sam9x5ek: add WM8731 codec ARM: at91/dt: sam9x5: add SSC DMA parameters ARM: at91/dt: add at91rm9200 PQFP package version ARM: at91: at91rm9200: set default mmc0 pinctrl-names ARM: at91: at91sam9n12: correct pin number of gpio-key ARM: at91: at91sam9n12: add qt1070 support ARM: at91: at91sam9n12: add pinctrl of TWI ARM: at91: Add PMU support for sama5d3 ARM: at91: at91sam9260: add missing pinctrl-names on mmc ARM: tegra: configure power off for Dalmore ARM: DT: binding fixup to align with vendor-prefixes.txt (DT) ARM: dts: add sdio blocks to bcm28155-ap board ARM: dts: align sdio numbers to HW definition ARM: sun7i: Add Olimex A20-Olinuxino-Micro support ARM: sun7i: Add Allwinner A20 DTSI ...
| * ARM: dts: tegra: Increase prefetchable PCI memory spaceJay Agarwal2013-08-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of evenly splitting the 512 MiB area between prefetchable and non-prefetchable memory spaces, increase the prefetchable memory space to 384 MiB while at the same time decreasing the non-prefetchable memory space to 128 MiB. This is a more useful default as most PCIe devices require more prefetchable than non-prefetchable memory. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Add Tegra20 PCIe support to DTThierry Reding2013-08-121-0/+55
| | | | | | | | | | | | | | | | | | | | Add the top-level pcie-controller node for the Tegra20 SoC. Tegra20 has two root ports that can use different lane layouts. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren: split DT changes into a separate patch from the main driver] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | arm: dts: tegra20: Rename USB UTMI parameters according to new definitionsMikko Perttunen2013-07-291-14/+14
|/ | | | | | | | | | | | This patch changes the Tegra20 USB PHY nodes to use the UTMI configuration parameter names as specified in the device tree binding documentation after patch "ARM: tegra: finalize USB EHCI and PHY bindings". Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* ARM: tegra20: convert device tree files to use CLK definesHiroshi Doyu2013-05-281-54/+62
| | | | | | | | | | | | Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra20-car.h moved for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert device tree files to use IRQ definesStephen Warren2013-05-281-68/+70
| | | | | | Use the GIC and standard IRQ binding defines in all IRQ specifiers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert device tree files to use GPIO definesStephen Warren2013-05-281-0/+2
| | | | | | | Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties, and some interrupts properties. Use standard GPIO flag defines too. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: use #include for all device treesStephen Warren2013-05-281-1/+1
| | | | | | | | | | | | | Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as the IDs and flags in GPIO specifiers. Use of those features will increase the readability of the device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: update device trees for USB binding reworkVenu Byravarasu2013-05-171-12/+37
| | | | | | | | | | | | | This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'tegra-for-3.10-dt' of ↵Arnd Bergmann2013-04-091-26/+27
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt2 From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: device tree changes This branch contains the majority of the device tree changes for Tegra. Highlights include: * Many changes for Tegra114, and the Dalmore board, to enable pinctrl, SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators. * Adding or enabling suspend wakeup sources on many boards, and adding suspend timing parameters, to support the system suspend patches. * Adding clocks to the audio-related nodes, so that in 3.11, the audio driver can pull these clocks from device tree rather than hard-coding clock names. * Some small DT fixes/cleanup. This branch is based on the previous clk pull request. * tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits) clk: tegra: Fix cdev1 and cdev2 IDs ARM: dts: tegra: add the PM configurations of PMC ARM: tegra: add non-removable and keep-power-in-suspend property for MMC ARM: tegra: whistler: add wakeup source for KBC ARM: tegra: add power gpio keys to DT ARM: tegra: keep power on to SD slot on Dalmore ARM: tegra: add clocks property to AC'97 sound nodes ARM: tegra: add clocks property to sound nodes ARM: tegra: dalmore: add fixed regulator node ARM: tegra: dalmore: add TPS65090 node ARM: tegra: dalmore: add cpu regulator node ARM: tegra: Add sbs-battery node to Dalmore ARM: tegra: add DT binding for i2c-tegra ARM: tegra: add SPI nodes to Tegra114 DT ARM: tegra: add KBC nodes to Tegra114 DT ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114 ARM: tegra: add I2C nodes to Tegra114 DT ARM: tegra: add APB DMA nodes to Tegra114 DT ARM: tegra: add PWM nodes to Tegra114 DT ARM: tegra: fix the status of PWM DT nodes ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2013-04-041-1/+1
| | | | | | | | | | | | | | | | Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix the status of PWM DT nodesAndrew Chew2013-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: Andrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix sort order of USB PHY nodesStephen Warren2013-04-041-25/+25
| | | | | | | | | | | | | | | | | | | | The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: device tree whitespace cleanupStephen Warren2013-04-041-1/+1
| | | | | | | | | | | | Remove white-space from empty line; triggers checkpatch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'tegra/clk' into next/dt2Arnd Bergmann2013-04-091-0/+4
|\| | | | | | | | | | | | | | | | | This is a dependency for the tegra/dt branch. Conflicts: drivers/clocksource/tegra20_timer.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren2013-04-041-0/+4
| |\
| | * ARM: tegra: add clock source of PMC to device treesJoseph Lo2013-04-031-0/+2
| | | | | | | | | | | | | | | | | | | | | Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * clocksource: tegra: move to of_clk_getPeter De Schrijver2013-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | ARM: tegra: fix register address of slink controllerLaxman Dewangan2013-03-221-1/+1
|/ / | | | | | | | | | | | | | | | | | | Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* / ARM: Tegra: Add clock entry for smp_twd clockPrashant Gaikwad2013-03-041-0/+1
|/ | | | | | | | | | | | | As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: remove clock-frequency properties from serial nodesStephen Warren2013-02-131-5/+0
| | | | | | | | | | | | | Currently, the serial nodes define both a clock-frequency and a clocks property. We should not provide both, since they might conflict. In practice, this also causes problems since the of_serial driver uses the clock-frequency property in preference to the clocks property, and hence doesn't clk_prepare_enable() the clock, which may then leave it with no known users, and hence the common clock framework will disable it, thus breaking the port, which is usually the console. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: tegra20: Rename "gart" to "iommu"Hiroshi Doyu2013-01-291-1/+1
| | | | | | | Use functional name for DT entry instead of h/w name. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-07 00:27:02 +0000