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authorThomas Gleixner <tglx@linutronix.de>2016-07-04 12:26:05 +0200
committerThomas Gleixner <tglx@linutronix.de>2016-07-04 12:26:05 +0200
commit8658be133baa92c06b6d832a436d437deb2e2a22 (patch)
tree8f798f4aae5892533831487e4838a85b95414a0f /arch/arm64/mm/context.c
parent4030103b9b2e060512f8292bb62582adfd02ebe8 (diff)
parent5e385a6ef31fbbf2acbda770aecc2bc2ff933d17 (diff)
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Merge branch 'irq/for-block' into irq/core
Pull the irq affinity managing code which is in a seperate branch for block developers to pull.
Diffstat (limited to 'arch/arm64/mm/context.c')
-rw-r--r--arch/arm64/mm/context.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index b7b397802088..efcf1f7ef1e4 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -179,7 +179,7 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
&asid_generation);
flush_context(cpu);
- /* We have at least 1 ASID per CPU, so this will always succeed */
+ /* We have more ASIDs than CPUs, so this will always succeed */
asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
set_asid:
@@ -227,8 +227,11 @@ switch_mm_fastpath:
static int asids_init(void)
{
asid_bits = get_cpu_asid_bits();
- /* If we end up with more CPUs than ASIDs, expect things to crash */
- WARN_ON(NUM_USER_ASIDS < num_possible_cpus());
+ /*
+ * Expect allocation after rollover to fail if we don't have at least
+ * one more ASID than CPUs. ASID #0 is reserved for init_mm.
+ */
+ WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus());
atomic64_set(&asid_generation, ASID_FIRST_VERSION);
asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
GFP_KERNEL);