diff options
| author | Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> | 2021-11-25 01:59:58 +0100 |
|---|---|---|
| committer | Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> | 2021-11-25 02:25:56 +0100 |
| commit | 1361c6221d8256edab90ead704e7ea8d1e65b011 (patch) | |
| tree | 4f8b2dc86c5189b9cb8eda7d759d8b8e572598e0 | |
| parent | b2a0ea8d882d8d340ae7e905b148f9a2224de290 (diff) | |
| download | kernel_replicant_linux-debian/v5.10.70.tar.gz kernel_replicant_linux-debian/v5.10.70.tar.bz2 kernel_replicant_linux-debian/v5.10.70.zip | |
Remove binaries that lack corresponding source codedebian/v5.10.70
While the firmwares being removed here are typically
under GPLv2 compatible free software licenses, they lack
corresponding source code, so they are practically speaking
not free software as we lack the source code and/or
toolchains that are required for modifying them.
And Replicant does not want to ship nonfree firmwares
because Replicant is a fully free software Android
distribution.
In addition, Replicant follows the GNU Free System
Distributions Guidelines (FSDG)[1].
And it is also directly supported by the FSF in various
ways[2] (they help with fundraising, we have a virtual
machine in the FSF infrastructure, etc).
So willingly shipping nonfree software (including firmwares)
is completely out of the question.
Since the Replicant 11 kernel is now based on Linux, we can
leverage projects that remove various nonfree firmwares
found in Linux.
Both linux-libre and Debian kernels remove theses nonfree
firmwares. Both linux-libre and Debian have a policy of
not including nonfree software so if there is any nonfree
software found, it's a bug and they need to be removed.
The Replicant steering commitee and the other people present
in the Replicant Contributors Meeting 2019 in Paris (me
included) decided againt blocking the usage of nonfree
firmwares.
Blocking nonfree firmwares is not required by the GNU Free
System Distribution Guidelines (FSDG).
The internal WiFi interface (and also some less important
hardware components) don't work without nonfree firmwares.
On some devices supported by Replicant, like the Galaxy SIII
(GT-I9300) and the Galaxy SIII 4G (GT-I9305), external WiFi
dongles compatible with the ath9k_htc driver do work fine
with a free firmware in Replicant 6.
And Replicant strongly advises its users to use such
WiFi dongles to get WiFi working.
But despite that, many users, by themselves, without any
guidance or instructions from Replicant, still do install
nonfree firmwares to get the internal WiFi working (and
potentially other hardware components too), probably because
external WiFi dongles are not very convenient to use and
consume a lot of battery.
So until we manage to replace the nonfree firmwares with
free firmwares we still need to not block users who still
install nonfree firmwares on their own, knowing that the
firmwares are nonfree and that they don't come from
Replicant at all.
In addition, if a decision to block nonfree firmwares is
taken, we would need to consult people about it and also to
have the Replicant steering have the final word on the
decision as it could potentially have a major impact on
users.
Because of that linux-libre cannot be used as-is.
So it either need to be modified or we need to find another
way to remove the nonfree firmwares.
It turned out difficult to modify linux-libre to remove the
nonfree firmwares without removing the loading of nonfree
firmwares, so here we used the ./debian/bin/genorig.py
Debian script against the kernel_replicant_linux git
repository to generate a linux_5.10.70.orig.tar.xz tarball
that was then used to produce this patch.
I used the Debian Linux repository[3] at the following
commit for that:
commit 12d3fa3c63f642e03da71e173d614ca7d2a844ba (HEAD, tag: debian/5.10.70-1)
Author: Salvatore Bonaccorso <carnil@debian.org>
Date: Thu Sep 30 21:36:41 2021 +0200
Prepare to release linux (5.10.70-1).
References:
-----------
[1]https://www.gnu.org/distros/free-system-distribution-guidelines.html
[2]https://redmine.replicant.us/projects/replicant/wiki/SteeringCommittee
[3]https://salsa.debian.org/kernel-team/linux.git
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
30 files changed, 0 insertions, 16308 deletions
diff --git a/Documentation/netlabel/draft-ietf-cipso-ipsecurity-01.txt b/Documentation/netlabel/draft-ietf-cipso-ipsecurity-01.txt deleted file mode 100644 index 256c2c9d4f50..000000000000 --- a/Documentation/netlabel/draft-ietf-cipso-ipsecurity-01.txt +++ /dev/null @@ -1,791 +0,0 @@ -IETF CIPSO Working Group -16 July, 1992 - - - - COMMERCIAL IP SECURITY OPTION (CIPSO 2.2) - - - -1. Status - -This Internet Draft provides the high level specification for a Commercial -IP Security Option (CIPSO). This draft reflects the version as approved by -the CIPSO IETF Working Group. Distribution of this memo is unlimited. - -This document is an Internet Draft. Internet Drafts are working documents -of the Internet Engineering Task Force (IETF), its Areas, and its Working -Groups. Note that other groups may also distribute working documents as -Internet Drafts. - -Internet Drafts are draft documents valid for a maximum of six months. -Internet Drafts may be updated, replaced, or obsoleted by other documents -at any time. It is not appropriate to use Internet Drafts as reference -material or to cite them other than as a "working draft" or "work in -progress." - -Please check the I-D abstract listing contained in each Internet Draft -directory to learn the current status of this or any other Internet Draft. - - - - -2. Background - -Currently the Internet Protocol includes two security options. One of -these options is the DoD Basic Security Option (BSO) (Type 130) which allows -IP datagrams to be labeled with security classifications. This option -provides sixteen security classifications and a variable number of handling -restrictions. To handle additional security information, such as security -categories or compartments, another security option (Type 133) exists and -is referred to as the DoD Extended Security Option (ESO). The values for -the fixed fields within these two options are administered by the Defense -Information Systems Agency (DISA). - -Computer vendors are now building commercial operating systems with -mandatory access controls and multi-level security. These systems are -no longer built specifically for a particular group in the defense or -intelligence communities. They are generally available commercial systems -for use in a variety of government and civil sector environments. - -The small number of ESO format codes can not support all the possible -applications of a commercial security option. The BSO and ESO were -designed to only support the United States DoD. CIPSO has been designed -to support multiple security policies. This Internet Draft provides the -format and procedures required to support a Mandatory Access Control -security policy. Support for additional security policies shall be -defined in future RFCs. - - - - -Internet Draft, Expires 15 Jan 93 [PAGE 1] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - - -3. CIPSO Format - -Option type: 134 (Class 0, Number 6, Copy on Fragmentation) -Option length: Variable - -This option permits security related information to be passed between -systems within a single Domain of Interpretation (DOI). A DOI is a -collection of systems which agree on the meaning of particular values -in the security option. An authority that has been assigned a DOI -identifier will define a mapping between appropriate CIPSO field values -and their human readable equivalent. This authority will distribute that -mapping to hosts within the authority's domain. These mappings may be -sensitive, therefore a DOI authority is not required to make these -mappings available to anyone other than the systems that are included in -the DOI. - -This option MUST be copied on fragmentation. This option appears at most -once in a datagram. All multi-octet fields in the option are defined to be -transmitted in network byte order. The format of this option is as follows: - -+----------+----------+------//------+-----------//---------+ -| 10000110 | LLLLLLLL | DDDDDDDDDDDD | TTTTTTTTTTTTTTTTTTTT | -+----------+----------+------//------+-----------//---------+ - - TYPE=134 OPTION DOMAIN OF TAGS - LENGTH INTERPRETATION - - - Figure 1. CIPSO Format - - -3.1 Type - -This field is 1 octet in length. Its value is 134. - - -3.2 Length - -This field is 1 octet in length. It is the total length of the option -including the type and length fields. With the current IP header length -restriction of 40 octets the value of this field MUST not exceed 40. - - -3.3 Domain of Interpretation Identifier - -This field is an unsigned 32 bit integer. The value 0 is reserved and MUST -not appear as the DOI identifier in any CIPSO option. Implementations -should assume that the DOI identifier field is not aligned on any particular -byte boundary. - -To conserve space in the protocol, security levels and categories are -represented by numbers rather than their ASCII equivalent. This requires -a mapping table within CIPSO hosts to map these numbers to their -corresponding ASCII representations. Non-related groups of systems may - - - -Internet Draft, Expires 15 Jan 93 [PAGE 2] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -have their own unique mappings. For example, one group of systems may -use the number 5 to represent Unclassified while another group may use the -number 1 to represent that same security level. The DOI identifier is used -to identify which mapping was used for the values within the option. - - -3.4 Tag Types - -A common format for passing security related information is necessary -for interoperability. CIPSO uses sets of "tags" to contain the security -information relevant to the data in the IP packet. Each tag begins with -a tag type identifier followed by the length of the tag and ends with the -actual security information to be passed. All multi-octet fields in a tag -are defined to be transmitted in network byte order. Like the DOI -identifier field in the CIPSO header, implementations should assume that -all tags, as well as fields within a tag, are not aligned on any particular -octet boundary. The tag types defined in this document contain alignment -bytes to assist alignment of some information, however alignment can not -be guaranteed if CIPSO is not the first IP option. - -CIPSO tag types 0 through 127 are reserved for defining standard tag -formats. Their definitions will be published in RFCs. Tag types whose -identifiers are greater than 127 are defined by the DOI authority and may -only be meaningful in certain Domains of Interpretation. For these tag -types, implementations will require the DOI identifier as well as the tag -number to determine the security policy and the format associated with the -tag. Use of tag types above 127 are restricted to closed networks where -interoperability with other networks will not be an issue. Implementations -that support a tag type greater than 127 MUST support at least one DOI that -requires only tag types 1 to 127. - -Tag type 0 is reserved. Tag types 1, 2, and 5 are defined in this -Internet Draft. Types 3 and 4 are reserved for work in progress. -The standard format for all current and future CIPSO tags is shown below: - -+----------+----------+--------//--------+ -| TTTTTTTT | LLLLLLLL | IIIIIIIIIIIIIIII | -+----------+----------+--------//--------+ - TAG TAG TAG - TYPE LENGTH INFORMATION - - Figure 2: Standard Tag Format - -In the three tag types described in this document, the length and count -restrictions are based on the current IP limitation of 40 octets for all -IP options. If the IP header is later expanded, then the length and count -restrictions specified in this document may increase to use the full area -provided for IP options. - - -3.4.1 Tag Type Classes - -Tag classes consist of tag types that have common processing requirements -and support the same security policy. The three tags defined in this -Internet Draft belong to the Mandatory Access Control (MAC) Sensitivity - - - -Internet Draft, Expires 15 Jan 93 [PAGE 3] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -class and support the MAC Sensitivity security policy. - - -3.4.2 Tag Type 1 - -This is referred to as the "bit-mapped" tag type. Tag type 1 is included -in the MAC Sensitivity tag type class. The format of this tag type is as -follows: - -+----------+----------+----------+----------+--------//---------+ -| 00000001 | LLLLLLLL | 00000000 | LLLLLLLL | CCCCCCCCCCCCCCCCC | -+----------+----------+----------+----------+--------//---------+ - - TAG TAG ALIGNMENT SENSITIVITY BIT MAP OF - TYPE LENGTH OCTET LEVEL CATEGORIES - - Figure 3. Tag Type 1 Format - - -3.4.2.1 Tag Type - -This field is 1 octet in length and has a value of 1. - - -3.4.2.2 Tag Length - -This field is 1 octet in length. It is the total length of the tag type -including the type and length fields. With the current IP header length -restriction of 40 bytes the value within this field is between 4 and 34. - - -3.4.2.3 Alignment Octet - -This field is 1 octet in length and always has the value of 0. Its purpose -is to align the category bitmap field on an even octet boundary. This will -speed many implementations including router implementations. - - -3.4.2.4 Sensitivity Level - -This field is 1 octet in length. Its value is from 0 to 255. The values -are ordered with 0 being the minimum value and 255 representing the maximum -value. - - -3.4.2.5 Bit Map of Categories - -The length of this field is variable and ranges from 0 to 30 octets. This -provides representation of categories 0 to 239. The ordering of the bits -is left to right or MSB to LSB. For example category 0 is represented by -the most significant bit of the first byte and category 15 is represented -by the least significant bit of the second byte. Figure 4 graphically -shows this ordering. Bit N is binary 1 if category N is part of the label -for the datagram, and bit N is binary 0 if category N is not part of the -label. Except for the optimized tag 1 format described in the next section, - - - -Internet Draft, Expires 15 Jan 93 [PAGE 4] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -minimal encoding SHOULD be used resulting in no trailing zero octets in the -category bitmap. - - octet 0 octet 1 octet 2 octet 3 octet 4 octet 5 - XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX . . . -bit 01234567 89111111 11112222 22222233 33333333 44444444 -number 012345 67890123 45678901 23456789 01234567 - - Figure 4. Ordering of Bits in Tag 1 Bit Map - - -3.4.2.6 Optimized Tag 1 Format - -Routers work most efficiently when processing fixed length fields. To -support these routers there is an optimized form of tag type 1. The format -does not change. The only change is to the category bitmap which is set to -a constant length of 10 octets. Trailing octets required to fill out the 10 -octets are zero filled. Ten octets, allowing for 80 categories, was chosen -because it makes the total length of the CIPSO option 20 octets. If CIPSO -is the only option then the option will be full word aligned and additional -filler octets will not be required. - - -3.4.3 Tag Type 2 - -This is referred to as the "enumerated" tag type. It is used to describe -large but sparsely populated sets of categories. Tag type 2 is in the MAC -Sensitivity tag type class. The format of this tag type is as follows: - -+----------+----------+----------+----------+-------------//-------------+ -| 00000010 | LLLLLLLL | 00000000 | LLLLLLLL | CCCCCCCCCCCCCCCCCCCCCCCCCC | -+----------+----------+----------+----------+-------------//-------------+ - - TAG TAG ALIGNMENT SENSITIVITY ENUMERATED - TYPE LENGTH OCTET LEVEL CATEGORIES - - Figure 5. Tag Type 2 Format - - -3.4.3.1 Tag Type - -This field is one octet in length and has a value of 2. - - -3.4.3.2 Tag Length - -This field is 1 octet in length. It is the total length of the tag type -including the type and length fields. With the current IP header length -restriction of 40 bytes the value within this field is between 4 and 34. - - -3.4.3.3 Alignment Octet - -This field is 1 octet in length and always has the value of 0. Its purpose -is to align the category field on an even octet boundary. This will - - - -Internet Draft, Expires 15 Jan 93 [PAGE 5] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -speed many implementations including router implementations. - - -3.4.3.4 Sensitivity Level - -This field is 1 octet in length. Its value is from 0 to 255. The values -are ordered with 0 being the minimum value and 255 representing the -maximum value. - - -3.4.3.5 Enumerated Categories - -In this tag, categories are represented by their actual value rather than -by their position within a bit field. The length of each category is 2 -octets. Up to 15 categories may be represented by this tag. Valid values -for categories are 0 to 65534. Category 65535 is not a valid category -value. The categories MUST be listed in ascending order within the tag. - - -3.4.4 Tag Type 5 - -This is referred to as the "range" tag type. It is used to represent -labels where all categories in a range, or set of ranges, are included -in the sensitivity label. Tag type 5 is in the MAC Sensitivity tag type -class. The format of this tag type is as follows: - -+----------+----------+----------+----------+------------//-------------+ -| 00000101 | LLLLLLLL | 00000000 | LLLLLLLL | Top/Bottom | Top/Bottom | -+----------+----------+----------+----------+------------//-------------+ - - TAG TAG ALIGNMENT SENSITIVITY CATEGORY RANGES - TYPE LENGTH OCTET LEVEL - - Figure 6. Tag Type 5 Format - - -3.4.4.1 Tag Type - -This field is one octet in length and has a value of 5. - - -3.4.4.2 Tag Length - -This field is 1 octet in length. It is the total length of the tag type -including the type and length fields. With the current IP header length -restriction of 40 bytes the value within this field is between 4 and 34. - - -3.4.4.3 Alignment Octet - -This field is 1 octet in length and always has the value of 0. Its purpose -is to align the category range field on an even octet boundary. This will -speed many implementations including router implementations. - - - - - -Internet Draft, Expires 15 Jan 93 [PAGE 6] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -3.4.4.4 Sensitivity Level - -This field is 1 octet in length. Its value is from 0 to 255. The values -are ordered with 0 being the minimum value and 255 representing the maximum -value. - - -3.4.4.5 Category Ranges - -A category range is a 4 octet field comprised of the 2 octet index of the -highest numbered category followed by the 2 octet index of the lowest -numbered category. These range endpoints are inclusive within the range of -categories. All categories within a range are included in the sensitivity -label. This tag may contain a maximum of 7 category pairs. The bottom -category endpoint for the last pair in the tag MAY be omitted and SHOULD be -assumed to be 0. The ranges MUST be non-overlapping and be listed in -descending order. Valid values for categories are 0 to 65534. Category -65535 is not a valid category value. - - -3.4.5 Minimum Requirements - -A CIPSO implementation MUST be capable of generating at least tag type 1 in -the non-optimized form. In addition, a CIPSO implementation MUST be able -to receive any valid tag type 1 even those using the optimized tag type 1 -format. - - -4. Configuration Parameters - -The configuration parameters defined below are required for all CIPSO hosts, -gateways, and routers that support multiple sensitivity labels. A CIPSO -host is defined to be the origination or destination system for an IP -datagram. A CIPSO gateway provides IP routing services between two or more -IP networks and may be required to perform label translations between -networks. A CIPSO gateway may be an enhanced CIPSO host or it may just -provide gateway services with no end system CIPSO capabilities. A CIPSO -router is a dedicated IP router that routes IP datagrams between two or more -IP networks. - -An implementation of CIPSO on a host MUST have the capability to reject a -datagram for reasons that the information contained can not be adequately -protected by the receiving host or if acceptance may result in violation of -the host or network security policy. In addition, a CIPSO gateway or router -MUST be able to reject datagrams going to networks that can not provide -adequate protection or may violate the network's security policy. To -provide this capability the following minimal set of configuration -parameters are required for CIPSO implementations: - -HOST_LABEL_MAX - This parameter contains the maximum sensitivity label that -a CIPSO host is authorized to handle. All datagrams that have a label -greater than this maximum MUST be rejected by the CIPSO host. This -parameter does not apply to CIPSO gateways or routers. This parameter need -not be defined explicitly as it can be implicitly derived from the -PORT_LABEL_MAX parameters for the associated interfaces. - - - -Internet Draft, Expires 15 Jan 93 [PAGE 7] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - - -HOST_LABEL_MIN - This parameter contains the minimum sensitivity label that -a CIPSO host is authorized to handle. All datagrams that have a label less -than this minimum MUST be rejected by the CIPSO host. This parameter does -not apply to CIPSO gateways or routers. This parameter need not be defined -explicitly as it can be implicitly derived from the PORT_LABEL_MIN -parameters for the associated interfaces. - -PORT_LABEL_MAX - This parameter contains the maximum sensitivity label for -all datagrams that may exit a particular network interface port. All -outgoing datagrams that have a label greater than this maximum MUST be -rejected by the CIPSO system. The label within this parameter MUST be -less than or equal to the label within the HOST_LABEL_MAX parameter. This -parameter does not apply to CIPSO hosts that support only one network port. - -PORT_LABEL_MIN - This parameter contains the minimum sensitivity label for -all datagrams that may exit a particular network interface port. All -outgoing datagrams that have a label less than this minimum MUST be -rejected by the CIPSO system. The label within this parameter MUST be -greater than or equal to the label within the HOST_LABEL_MIN parameter. -This parameter does not apply to CIPSO hosts that support only one network -port. - -PORT_DOI - This parameter is used to assign a DOI identifier value to a -particular network interface port. All CIPSO labels within datagrams -going out this port MUST use the specified DOI identifier. All CIPSO -hosts and gateways MUST support either this parameter, the NET_DOI -parameter, or the HOST_DOI parameter. - -NET_DOI - This parameter is used to assign a DOI identifier value to a -particular IP network address. All CIPSO labels within datagrams destined -for the particular IP network MUST use the specified DOI identifier. All -CIPSO hosts and gateways MUST support either this parameter, the PORT_DOI -parameter, or the HOST_DOI parameter. - -HOST_DOI - This parameter is used to assign a DOI identifier value to a -particular IP host address. All CIPSO labels within datagrams destined for -the particular IP host will use the specified DOI identifier. All CIPSO -hosts and gateways MUST support either this parameter, the PORT_DOI -parameter, or the NET_DOI parameter. - -This list represents the minimal set of configuration parameters required -to be compliant. Implementors are encouraged to add to this list to -provide enhanced functionality and control. For example, many security -policies may require both incoming and outgoing datagrams be checked against -the port and host label ranges. - - -4.1 Port Range Parameters - -The labels represented by the PORT_LABEL_MAX and PORT_LABEL_MIN parameters -MAY be in CIPSO or local format. Some CIPSO systems, such as routers, may -want to have the range parameters expressed in CIPSO format so that incoming -labels do not have to be converted to a local format before being compared -against the range. If multiple DOIs are supported by one of these CIPSO - - - -Internet Draft, Expires 15 Jan 93 [PAGE 8] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -systems then multiple port range parameters would be needed, one set for -each DOI supported on a particular port. - -The port range will usually represent the total set of labels that may -exist on the logical network accessed through the corresponding network -interface. It may, however, represent a subset of these labels that are -allowed to enter the CIPSO system. - - -4.2 Single Label CIPSO Hosts - -CIPSO implementations that support only one label are not required to -support the parameters described above. These limited implementations are -only required to support a NET_LABEL parameter. This parameter contains -the CIPSO label that may be inserted in datagrams that exit the host. In -addition, the host MUST reject any incoming datagram that has a label which -is not equivalent to the NET_LABEL parameter. - - -5. Handling Procedures - -This section describes the processing requirements for incoming and -outgoing IP datagrams. Just providing the correct CIPSO label format -is not enough. Assumptions will be made by one system on how a -receiving system will handle the CIPSO label. Wrong assumptions may -lead to non-interoperability or even a security incident. The -requirements described below represent the minimal set needed for -interoperability and that provide users some level of confidence. -Many other requirements could be added to increase user confidence, -however at the risk of restricting creativity and limiting vendor -participation. - - -5.1 Input Procedures - -All datagrams received through a network port MUST have a security label -associated with them, either contained in the datagram or assigned to the -receiving port. Without this label the host, gateway, or router will not -have the information it needs to make security decisions. This security -label will be obtained from the CIPSO if the option is present in the -datagram. See section 4.1.2 for handling procedures for unlabeled -datagrams. This label will be compared against the PORT (if appropriate) -and HOST configuration parameters defined in section 3. - -If any field within the CIPSO option, such as the DOI identifier, is not -recognized the IP datagram is discarded and an ICMP "parameter problem" -(type 12) is generated and returned. The ICMP code field is set to "bad -parameter" (code 0) and the pointer is set to the start of the CIPSO field -that is unrecognized. - -If the contents of the CIPSO are valid but the security label is -outside of the configured host or port label range, the datagram is -discarded and an ICMP "destination unreachable" (type 3) is generated -and returned. The code field of the ICMP is set to "communication with -destination network administratively prohibited" (code 9) or to - - - -Internet Draft, Expires 15 Jan 93 [PAGE 9] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -"communication with destination host administratively prohibited" -(code 10). The value of the code field used is dependent upon whether -the originator of the ICMP message is acting as a CIPSO host or a CIPSO -gateway. The recipient of the ICMP message MUST be able to handle either -value. The same procedure is performed if a CIPSO can not be added to an -IP packet because it is too large to fit in the IP options area. - -If the error is triggered by receipt of an ICMP message, the message -is discarded and no response is permitted (consistent with general ICMP -processing rules). - - -5.1.1 Unrecognized tag types - -The default condition for any CIPSO implementation is that an -unrecognized tag type MUST be treated as a "parameter problem" and -handled as described in section 4.1. A CIPSO implementation MAY allow -the system administrator to identify tag types that may safely be -ignored. This capability is an allowable enhancement, not a -requirement. - - -5.1.2 Unlabeled Packets - -A network port may be configured to not require a CIPSO label for all -incoming datagrams. For this configuration a CIPSO label must be -assigned to that network port and associated with all unlabeled IP -datagrams. This capability might be used for single level networks or -networks that have CIPSO and non-CIPSO hosts and the non-CIPSO hosts -all operate at the same label. - -If a CIPSO option is required and none is found, the datagram is -discarded and an ICMP "parameter problem" (type 12) is generated and -returned to the originator of the datagram. The code field of the ICMP -is set to "option missing" (code 1) and the ICMP pointer is set to 134 -(the value of the option type for the missing CIPSO option). - - -5.2 Output Procedures - -A CIPSO option MUST appear only once in a datagram. Only one tag type -from the MAC Sensitivity class MAY be included in a CIPSO option. Given -the current set of defined tag types, this means that CIPSO labels at -first will contain only one tag. - -All datagrams leaving a CIPSO system MUST meet the following condition: - - PORT_LABEL_MIN <= CIPSO label <= PORT_LABEL_MAX - -If this condition is not satisfied the datagram MUST be discarded. -If the CIPSO system only supports one port, the HOST_LABEL_MIN and the -HOST_LABEL_MAX parameters MAY be substituted for the PORT parameters in -the above condition. - -The DOI identifier to be used for all outgoing datagrams is configured by - - - -Internet Draft, Expires 15 Jan 93 [PAGE 10] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - -the administrator. If port level DOI identifier assignment is used, then -the PORT_DOI configuration parameter MUST contain the DOI identifier to -use. If network level DOI assignment is used, then the NET_DOI parameter -MUST contain the DOI identifier to use. And if host level DOI assignment -is employed, then the HOST_DOI parameter MUST contain the DOI identifier -to use. A CIPSO implementation need only support one level of DOI -assignment. - - -5.3 DOI Processing Requirements - -A CIPSO implementation MUST support at least one DOI and SHOULD support -multiple DOIs. System and network administrators are cautioned to -ensure that at least one DOI is common within an IP network to allow for -broadcasting of IP datagrams. - -CIPSO gateways MUST be capable of translating a CIPSO option from one -DOI to another when forwarding datagrams between networks. For -efficiency purposes this capability is only a desired feature for CIPSO -routers. - - -5.4 Label of ICMP Messages - -The CIPSO label to be used on all outgoing ICMP messages MUST be equivalent -to the label of the datagram that caused the ICMP message. If the ICMP was -generated due to a problem associated with the original CIPSO label then the -following responses are allowed: - - a. Use the CIPSO label of the original IP datagram - b. Drop the original datagram with no return message generated - -In most cases these options will have the same effect. If you can not -interpret the label or if it is outside the label range of your host or -interface then an ICMP message with the same label will probably not be -able to exit the system. - - -6. Assignment of DOI Identifier Numbers = - -Requests for assignment of a DOI identifier number should be addressed to -the Internet Assigned Numbers Authority (IANA). - - -7. Acknowledgements - -Much of the material in this RFC is based on (and copied from) work -done by Gary Winiger of Sun Microsystems and published as Commercial -IP Security Option at the INTEROP 89, Commercial IPSO Workshop. - - -8. Author's Address - -To submit mail for distribution to members of the IETF CIPSO Working -Group, send mail to: cipso@wdl1.wdl.loral.com. - - - -Internet Draft, Expires 15 Jan 93 [PAGE 11] - - - -CIPSO INTERNET DRAFT 16 July, 1992 - - - - -To be added to or deleted from this distribution, send mail to: -cipso-request@wdl1.wdl.loral.com. - - -9. References - -RFC 1038, "Draft Revised IP Security Option", M. St. Johns, IETF, January -1988. - -RFC 1108, "U.S. Department of Defense Security Options -for the Internet Protocol", Stephen Kent, IAB, 1 March, 1991. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Internet Draft, Expires 15 Jan 93 [PAGE 12] - - - diff --git a/arch/powerpc/platforms/8xx/micropatch.c b/arch/powerpc/platforms/8xx/micropatch.c deleted file mode 100644 index aef179fcbd4f..000000000000 --- a/arch/powerpc/platforms/8xx/micropatch.c +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Microcode patches for the CPM as supplied by Motorola. - * This is the one for IIC/SPI. There is a newer one that - * also relocates SMC2, but this would require additional changes - * to uart.c, so I am holding off on that for a moment. - */ -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <asm/irq.h> -#include <asm/page.h> -#include <asm/8xx_immap.h> -#include <asm/cpm.h> -#include <asm/cpm1.h> - -struct patch_params { - ushort rccr; - ushort cpmcr1; - ushort cpmcr2; - ushort cpmcr3; - ushort cpmcr4; -}; - -/* - * I2C/SPI relocation patch arrays. - */ - -#ifdef CONFIG_I2C_SPI_UCODE_PATCH - -static char patch_name[] __initdata = "I2C/SPI"; - -static struct patch_params patch_params __initdata = { - 1, 0x802a, 0x8028, 0x802e, 0x802c, -}; - -static uint patch_2000[] __initdata = { - 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, - 0x5FEFADF7, 0x5F89ADF7, 0x5FEFAFF7, 0x5F89AFF7, - 0x3A9CFBC8, 0xE7C0EDF0, 0x77C1E1BB, 0xF4DC7F1D, - 0xABAD932F, 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF, - 0xFD1FF9CF, 0xABF88DC6, 0xAB5679F7, 0xB0937383, - 0xDFCE79F7, 0xB091E6BB, 0xE5BBE74F, 0xB3FA6F0F, - 0x6FFB76CE, 0xEE0DF9CF, 0x2BFBEFEF, 0xCFEEF9CF, - 0x76CEAD24, 0x90B2DF9A, 0x7FDDD0BF, 0x4BF847FD, - 0x7CCF76CE, 0xCFEF7E1F, 0x7F1D7DFD, 0xF0B6EF71, - 0x7FC177C1, 0xFBC86079, 0xE722FBC8, 0x5FFFDFFF, - 0x5FB2FFFB, 0xFBC8F3C8, 0x94A67F01, 0x7F1D5F39, - 0xAFE85F5E, 0xFFDFDF96, 0xCB9FAF7D, 0x5FC1AFED, - 0x8C1C5FC1, 0xAFDD5FC3, 0xDF9A7EFD, 0xB0B25FB2, - 0xFFFEABAD, 0x5FB2FFFE, 0x5FCE600B, 0xE6BB600B, - 0x5FCEDFC6, 0x27FBEFDF, 0x5FC8CFDE, 0x3A9CE7C0, - 0xEDF0F3C8, 0x7F0154CD, 0x7F1D2D3D, 0x363A7570, - 0x7E0AF1CE, 0x37EF2E68, 0x7FEE10EC, 0xADF8EFDE, - 0xCFEAE52F, 0x7D0FE12B, 0xF1CE5F65, 0x7E0A4DF8, - 0xCFEA5F72, 0x7D0BEFEE, 0xCFEA5F74, 0xE522EFDE, - 0x5F74CFDA, 0x0B627385, 0xDF627E0A, 0x30D8145B, - 0xBFFFF3C8, 0x5FFFDFFF, 0xA7F85F5E, 0xBFFE7F7D, - 0x10D31450, 0x5F36BFFF, 0xAF785F5E, 0xBFFDA7F8, - 0x5F36BFFE, 0x77FD30C0, 0x4E08FDCF, 0xE5FF6E0F, - 0xAFF87E1F, 0x7E0FFD1F, 0xF1CF5F1B, 0xABF80D5E, - 0x5F5EFFEF, 0x79F730A2, 0xAFDD5F34, 0x47F85F34, - 0xAFED7FDD, 0x50B24978, 0x47FD7F1D, 0x7DFD70AD, - 0xEF717EC1, 0x6BA47F01, 0x2D267EFD, 0x30DE5F5E, - 0xFFFD5F5E, 0xFFEF5F5E, 0xFFDF0CA0, 0xAFED0A9E, - 0xAFDD0C3A, 0x5F3AAFBD, 0x7FBDB082, 0x5F8247F8 -}; - -static uint patch_2f00[] __initdata = { - 0x3E303430, 0x34343737, 0xABF7BF9B, 0x994B4FBD, - 0xBD599493, 0x349FFF37, 0xFB9B177D, 0xD9936956, - 0xBBFDD697, 0xBDD2FD11, 0x31DB9BB3, 0x63139637, - 0x93733693, 0x193137F7, 0x331737AF, 0x7BB9B999, - 0xBB197957, 0x7FDFD3D5, 0x73B773F7, 0x37933B99, - 0x1D115316, 0x99315315, 0x31694BF4, 0xFBDBD359, - 0x31497353, 0x76956D69, 0x7B9D9693, 0x13131979, - 0x79376935 -}; - -static uint patch_2e00[] __initdata = {}; -#endif - -/* - * I2C/SPI/SMC1 relocation patch arrays. - */ - -#ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH - -static char patch_name[] __initdata = "I2C/SPI/SMC1"; - -static struct patch_params patch_params __initdata = { - 3, 0x8080, 0x808a, 0x8028, 0x802a, -}; - -static uint patch_2000[] __initdata = { - 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000, - 0x5f13eff8, 0x5eb5eff8, 0x5f88adf7, 0x5fefadf7, - 0x3a9cfbc8, 0x77cae1bb, 0xf4de7fad, 0xabae9330, - 0x4e08fdcf, 0x6e0faff8, 0x7ccf76cf, 0xfdaff9cf, - 0xabf88dc8, 0xab5879f7, 0xb0925d8d, 0xdfd079f7, - 0xb090e6bb, 0xe5bbe74f, 0x9e046f0f, 0x6ffb76ce, - 0xee0cf9cf, 0x2bfbefef, 0xcfeef9cf, 0x76cead23, - 0x90b3df99, 0x7fddd0c1, 0x4bf847fd, 0x7ccf76ce, - 0xcfef77ca, 0x7eaf7fad, 0x7dfdf0b7, 0xef7a7fca, - 0x77cafbc8, 0x6079e722, 0xfbc85fff, 0xdfff5fb3, - 0xfffbfbc8, 0xf3c894a5, 0xe7c9edf9, 0x7f9a7fad, - 0x5f36afe8, 0x5f5bffdf, 0xdf95cb9e, 0xaf7d5fc3, - 0xafed8c1b, 0x5fc3afdd, 0x5fc5df99, 0x7efdb0b3, - 0x5fb3fffe, 0xabae5fb3, 0xfffe5fd0, 0x600be6bb, - 0x600b5fd0, 0xdfc827fb, 0xefdf5fca, 0xcfde3a9c, - 0xe7c9edf9, 0xf3c87f9e, 0x54ca7fed, 0x2d3a3637, - 0x756f7e9a, 0xf1ce37ef, 0x2e677fee, 0x10ebadf8, - 0xefdecfea, 0xe52f7d9f, 0xe12bf1ce, 0x5f647e9a, - 0x4df8cfea, 0x5f717d9b, 0xefeecfea, 0x5f73e522, - 0xefde5f73, 0xcfda0b61, 0x5d8fdf61, 0xe7c9edf9, - 0x7e9a30d5, 0x1458bfff, 0xf3c85fff, 0xdfffa7f8, - 0x5f5bbffe, 0x7f7d10d0, 0x144d5f33, 0xbfffaf78, - 0x5f5bbffd, 0xa7f85f33, 0xbffe77fd, 0x30bd4e08, - 0xfdcfe5ff, 0x6e0faff8, 0x7eef7e9f, 0xfdeff1cf, - 0x5f17abf8, 0x0d5b5f5b, 0xffef79f7, 0x309eafdd, - 0x5f3147f8, 0x5f31afed, 0x7fdd50af, 0x497847fd, - 0x7f9e7fed, 0x7dfd70a9, 0xef7e7ece, 0x6ba07f9e, - 0x2d227efd, 0x30db5f5b, 0xfffd5f5b, 0xffef5f5b, - 0xffdf0c9c, 0xafed0a9a, 0xafdd0c37, 0x5f37afbd, - 0x7fbdb081, 0x5f8147f8, 0x3a11e710, 0xedf0ccdd, - 0xf3186d0a, 0x7f0e5f06, 0x7fedbb38, 0x3afe7468, - 0x7fedf4fc, 0x8ffbb951, 0xb85f77fd, 0xb0df5ddd, - 0xdefe7fed, 0x90e1e74d, 0x6f0dcbf7, 0xe7decfed, - 0xcb74cfed, 0xcfeddf6d, 0x91714f74, 0x5dd2deef, - 0x9e04e7df, 0xefbb6ffb, 0xe7ef7f0e, 0x9e097fed, - 0xebdbeffa, 0xeb54affb, 0x7fea90d7, 0x7e0cf0c3, - 0xbffff318, 0x5fffdfff, 0xac59efea, 0x7fce1ee5, - 0xe2ff5ee1, 0xaffbe2ff, 0x5ee3affb, 0xf9cc7d0f, - 0xaef8770f, 0x7d0fb0c6, 0xeffbbfff, 0xcfef5ede, - 0x7d0fbfff, 0x5ede4cf8, 0x7fddd0bf, 0x49f847fd, - 0x7efdf0bb, 0x7fedfffd, 0x7dfdf0b7, 0xef7e7e1e, - 0x5ede7f0e, 0x3a11e710, 0xedf0ccab, 0xfb18ad2e, - 0x1ea9bbb8, 0x74283b7e, 0x73c2e4bb, 0x2ada4fb8, - 0xdc21e4bb, 0xb2a1ffbf, 0x5e2c43f8, 0xfc87e1bb, - 0xe74ffd91, 0x6f0f4fe8, 0xc7ba32e2, 0xf396efeb, - 0x600b4f78, 0xe5bb760b, 0x53acaef8, 0x4ef88b0e, - 0xcfef9e09, 0xabf8751f, 0xefef5bac, 0x741f4fe8, - 0x751e760d, 0x7fdbf081, 0x741cafce, 0xefcc7fce, - 0x751e70ac, 0x741ce7bb, 0x3372cfed, 0xafdbefeb, - 0xe5bb760b, 0x53f2aef8, 0xafe8e7eb, 0x4bf8771e, - 0x7e247fed, 0x4fcbe2cc, 0x7fbc30a9, 0x7b0f7a0f, - 0x34d577fd, 0x308b5db7, 0xde553e5f, 0xaf78741f, - 0x741f30f0, 0xcfef5e2c, 0x741f3eac, 0xafb8771e, - 0x5e677fed, 0x0bd3e2cc, 0x741ccfec, 0xe5ca53cd, - 0x6fcb4f74, 0x5dadde4b, 0x2ab63d38, 0x4bb3de30, - 0x751f741c, 0x6c42effa, 0xefea7fce, 0x6ffc30be, - 0xefec3fca, 0x30b3de2e, 0xadf85d9e, 0xaf7daefd, - 0x5d9ede2e, 0x5d9eafdd, 0x761f10ac, 0x1da07efd, - 0x30adfffe, 0x4908fb18, 0x5fffdfff, 0xafbb709b, - 0x4ef85e67, 0xadf814ad, 0x7a0f70ad, 0xcfef50ad, - 0x7a0fde30, 0x5da0afed, 0x3c12780f, 0xefef780f, - 0xefef790f, 0xa7f85e0f, 0xffef790f, 0xefef790f, - 0x14adde2e, 0x5d9eadfd, 0x5e2dfffb, 0xe79addfd, - 0xeff96079, 0x607ae79a, 0xddfceff9, 0x60795dff, - 0x607acfef, 0xefefefdf, 0xefbfef7f, 0xeeffedff, - 0xebffe7ff, 0xafefafdf, 0xafbfaf7f, 0xaeffadff, - 0xabffa7ff, 0x6fef6fdf, 0x6fbf6f7f, 0x6eff6dff, - 0x6bff67ff, 0x2fef2fdf, 0x2fbf2f7f, 0x2eff2dff, - 0x2bff27ff, 0x4e08fd1f, 0xe5ff6e0f, 0xaff87eef, - 0x7e0ffdef, 0xf11f6079, 0xabf8f542, 0x7e0af11c, - 0x37cfae3a, 0x7fec90be, 0xadf8efdc, 0xcfeae52f, - 0x7d0fe12b, 0xf11c6079, 0x7e0a4df8, 0xcfea5dc4, - 0x7d0befec, 0xcfea5dc6, 0xe522efdc, 0x5dc6cfda, - 0x4e08fd1f, 0x6e0faff8, 0x7c1f761f, 0xfdeff91f, - 0x6079abf8, 0x761cee24, 0xf91f2bfb, 0xefefcfec, - 0xf91f6079, 0x761c27fb, 0xefdf5da7, 0xcfdc7fdd, - 0xd09c4bf8, 0x47fd7c1f, 0x761ccfcf, 0x7eef7fed, - 0x7dfdf093, 0xef7e7f1e, 0x771efb18, 0x6079e722, - 0xe6bbe5bb, 0xae0ae5bb, 0x600bae85, 0xe2bbe2bb, - 0xe2bbe2bb, 0xaf02e2bb, 0xe2bb2ff9, 0x6079e2bb -}; - -static uint patch_2f00[] __initdata = { - 0x30303030, 0x3e3e3434, 0xabbf9b99, 0x4b4fbdbd, - 0x59949334, 0x9fff37fb, 0x9b177dd9, 0x936956bb, - 0xfbdd697b, 0xdd2fd113, 0x1db9f7bb, 0x36313963, - 0x79373369, 0x3193137f, 0x7331737a, 0xf7bb9b99, - 0x9bb19795, 0x77fdfd3d, 0x573b773f, 0x737933f7, - 0xb991d115, 0x31699315, 0x31531694, 0xbf4fbdbd, - 0x35931497, 0x35376956, 0xbd697b9d, 0x96931313, - 0x19797937, 0x6935af78, 0xb9b3baa3, 0xb8788683, - 0x368f78f7, 0x87778733, 0x3ffffb3b, 0x8e8f78b8, - 0x1d118e13, 0xf3ff3f8b, 0x6bd8e173, 0xd1366856, - 0x68d1687b, 0x3daf78b8, 0x3a3a3f87, 0x8f81378f, - 0xf876f887, 0x77fd8778, 0x737de8d6, 0xbbf8bfff, - 0xd8df87f7, 0xfd876f7b, 0x8bfff8bd, 0x8683387d, - 0xb873d87b, 0x3b8fd7f8, 0xf7338883, 0xbb8ee1f8, - 0xef837377, 0x3337b836, 0x817d11f8, 0x7378b878, - 0xd3368b7d, 0xed731b7d, 0x833731f3, 0xf22f3f23 -}; - -static uint patch_2e00[] __initdata = { - 0x27eeeeee, 0xeeeeeeee, 0xeeeeeeee, 0xeeeeeeee, - 0xee4bf4fb, 0xdbd259bb, 0x1979577f, 0xdfd2d573, - 0xb773f737, 0x4b4fbdbd, 0x25b9b177, 0xd2d17376, - 0x956bbfdd, 0x697bdd2f, 0xff9f79ff, 0xff9ff22f -}; -#endif - -/* - * USB SOF patch arrays. - */ - -#ifdef CONFIG_USB_SOF_UCODE_PATCH - -static char patch_name[] __initdata = "USB SOF"; - -static struct patch_params patch_params __initdata = { - 9, -}; - -static uint patch_2000[] __initdata = { - 0x7fff0000, 0x7ffd0000, 0x7ffb0000, 0x49f7ba5b, - 0xba383ffb, 0xf9b8b46d, 0xe5ab4e07, 0xaf77bffe, - 0x3f7bbf79, 0xba5bba38, 0xe7676076, 0x60750000 -}; - -static uint patch_2f00[] __initdata = { - 0x3030304c, 0xcab9e441, 0xa1aaf220 -}; - -static uint patch_2e00[] __initdata = {}; -#endif - -/* - * SMC relocation patch arrays. - */ - -#ifdef CONFIG_SMC_UCODE_PATCH - -static char patch_name[] __initdata = "SMC"; - -static struct patch_params patch_params __initdata = { - 2, 0x8080, 0x8088, -}; - -static uint patch_2000[] __initdata = { - 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000, - 0x5fefeff8, 0x5f91eff8, 0x3ff30000, 0x3ff10000, - 0x3a11e710, 0xedf0ccb9, 0xf318ed66, 0x7f0e5fe2, - 0x7fedbb38, 0x3afe7468, 0x7fedf4d8, 0x8ffbb92d, - 0xb83b77fd, 0xb0bb5eb9, 0xdfda7fed, 0x90bde74d, - 0x6f0dcbd3, 0xe7decfed, 0xcb50cfed, 0xcfeddf6d, - 0x914d4f74, 0x5eaedfcb, 0x9ee0e7df, 0xefbb6ffb, - 0xe7ef7f0e, 0x9ee57fed, 0xebb7effa, 0xeb30affb, - 0x7fea90b3, 0x7e0cf09f, 0xbffff318, 0x5fffdfff, - 0xac35efea, 0x7fce1fc1, 0xe2ff5fbd, 0xaffbe2ff, - 0x5fbfaffb, 0xf9a87d0f, 0xaef8770f, 0x7d0fb0a2, - 0xeffbbfff, 0xcfef5fba, 0x7d0fbfff, 0x5fba4cf8, - 0x7fddd09b, 0x49f847fd, 0x7efdf097, 0x7fedfffd, - 0x7dfdf093, 0xef7e7e1e, 0x5fba7f0e, 0x3a11e710, - 0xedf0cc87, 0xfb18ad0a, 0x1f85bbb8, 0x74283b7e, - 0x7375e4bb, 0x2ab64fb8, 0x5c7de4bb, 0x32fdffbf, - 0x5f0843f8, 0x7ce3e1bb, 0xe74f7ded, 0x6f0f4fe8, - 0xc7ba32be, 0x73f2efeb, 0x600b4f78, 0xe5bb760b, - 0x5388aef8, 0x4ef80b6a, 0xcfef9ee5, 0xabf8751f, - 0xefef5b88, 0x741f4fe8, 0x751e760d, 0x7fdb70dd, - 0x741cafce, 0xefcc7fce, 0x751e7088, 0x741ce7bb, - 0x334ecfed, 0xafdbefeb, 0xe5bb760b, 0x53ceaef8, - 0xafe8e7eb, 0x4bf8771e, 0x7e007fed, 0x4fcbe2cc, - 0x7fbc3085, 0x7b0f7a0f, 0x34b177fd, 0xb0e75e93, - 0xdf313e3b, 0xaf78741f, 0x741f30cc, 0xcfef5f08, - 0x741f3e88, 0xafb8771e, 0x5f437fed, 0x0bafe2cc, - 0x741ccfec, 0xe5ca53a9, 0x6fcb4f74, 0x5e89df27, - 0x2a923d14, 0x4b8fdf0c, 0x751f741c, 0x6c1eeffa, - 0xefea7fce, 0x6ffc309a, 0xefec3fca, 0x308fdf0a, - 0xadf85e7a, 0xaf7daefd, 0x5e7adf0a, 0x5e7aafdd, - 0x761f1088, 0x1e7c7efd, 0x3089fffe, 0x4908fb18, - 0x5fffdfff, 0xafbbf0f7, 0x4ef85f43, 0xadf81489, - 0x7a0f7089, 0xcfef5089, 0x7a0fdf0c, 0x5e7cafed, - 0xbc6e780f, 0xefef780f, 0xefef790f, 0xa7f85eeb, - 0xffef790f, 0xefef790f, 0x1489df0a, 0x5e7aadfd, - 0x5f09fffb, 0xe79aded9, 0xeff96079, 0x607ae79a, - 0xded8eff9, 0x60795edb, 0x607acfef, 0xefefefdf, - 0xefbfef7f, 0xeeffedff, 0xebffe7ff, 0xafefafdf, - 0xafbfaf7f, 0xaeffadff, 0xabffa7ff, 0x6fef6fdf, - 0x6fbf6f7f, 0x6eff6dff, 0x6bff67ff, 0x2fef2fdf, - 0x2fbf2f7f, 0x2eff2dff, 0x2bff27ff, 0x4e08fd1f, - 0xe5ff6e0f, 0xaff87eef, 0x7e0ffdef, 0xf11f6079, - 0xabf8f51e, 0x7e0af11c, 0x37cfae16, 0x7fec909a, - 0xadf8efdc, 0xcfeae52f, 0x7d0fe12b, 0xf11c6079, - 0x7e0a4df8, 0xcfea5ea0, 0x7d0befec, 0xcfea5ea2, - 0xe522efdc, 0x5ea2cfda, 0x4e08fd1f, 0x6e0faff8, - 0x7c1f761f, 0xfdeff91f, 0x6079abf8, 0x761cee00, - 0xf91f2bfb, 0xefefcfec, 0xf91f6079, 0x761c27fb, - 0xefdf5e83, 0xcfdc7fdd, 0x50f84bf8, 0x47fd7c1f, - 0x761ccfcf, 0x7eef7fed, 0x7dfd70ef, 0xef7e7f1e, - 0x771efb18, 0x6079e722, 0xe6bbe5bb, 0x2e66e5bb, - 0x600b2ee1, 0xe2bbe2bb, 0xe2bbe2bb, 0x2f5ee2bb, - 0xe2bb2ff9, 0x6079e2bb, -}; - -static uint patch_2f00[] __initdata = { - 0x30303030, 0x3e3e3030, 0xaf79b9b3, 0xbaa3b979, - 0x9693369f, 0x79f79777, 0x97333fff, 0xfb3b9e9f, - 0x79b91d11, 0x9e13f3ff, 0x3f9b6bd9, 0xe173d136, - 0x695669d1, 0x697b3daf, 0x79b93a3a, 0x3f979f91, - 0x379ff976, 0xf99777fd, 0x9779737d, 0xe9d6bbf9, - 0xbfffd9df, 0x97f7fd97, 0x6f7b9bff, 0xf9bd9683, - 0x397db973, 0xd97b3b9f, 0xd7f9f733, 0x9993bb9e, - 0xe1f9ef93, 0x73773337, 0xb936917d, 0x11f87379, - 0xb979d336, 0x8b7ded73, 0x1b7d9337, 0x31f3f22f, - 0x3f2327ee, 0xeeeeeeee, 0xeeeeeeee, 0xeeeeeeee, - 0xeeeeee4b, 0xf4fbdbd2, 0x58bb1878, 0x577fdfd2, - 0xd573b773, 0xf7374b4f, 0xbdbd25b8, 0xb177d2d1, - 0x7376856b, 0xbfdd687b, 0xdd2fff8f, 0x78ffff8f, - 0xf22f0000, -}; - -static uint patch_2e00[] __initdata = {}; -#endif - -static void __init cpm_write_patch(cpm8xx_t *cp, int offset, uint *patch, int len) -{ - if (!len) - return; - memcpy_toio(cp->cp_dpmem + offset, patch, len); -} - -void __init cpm_load_patch(cpm8xx_t *cp) -{ - out_be16(&cp->cp_rccr, 0); - - cpm_write_patch(cp, 0, patch_2000, sizeof(patch_2000)); - cpm_write_patch(cp, 0xf00, patch_2f00, sizeof(patch_2f00)); - cpm_write_patch(cp, 0xe00, patch_2e00, sizeof(patch_2e00)); - - if (IS_ENABLED(CONFIG_I2C_SPI_UCODE_PATCH) || - IS_ENABLED(CONFIG_I2C_SPI_SMC1_UCODE_PATCH)) { - u16 rpbase = 0x500; - iic_t *iip; - struct spi_pram *spp; - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - out_be16(&iip->iic_rpbase, rpbase); - - /* Put SPI above the IIC, also 32-byte aligned. */ - spp = (struct spi_pram *)&cp->cp_dparam[PROFF_SPI]; - out_be16(&spp->rpbase, (rpbase + sizeof(iic_t) + 31) & ~31); - - if (IS_ENABLED(CONFIG_I2C_SPI_SMC1_UCODE_PATCH)) { - smc_uart_t *smp; - - smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC1]; - out_be16(&smp->smc_rpbase, 0x1FC0); - } - } - - if (IS_ENABLED(CONFIG_SMC_UCODE_PATCH)) { - smc_uart_t *smp; - - if (IS_ENABLED(CONFIG_PPC_EARLY_DEBUG_CPM)) { - int i; - - for (i = 0; i < sizeof(*smp); i += 4) { - u32 __iomem *src = (u32 __iomem *)&cp->cp_dparam[PROFF_SMC1 + i]; - u32 __iomem *dst = (u32 __iomem *)&cp->cp_dparam[PROFF_DSP1 + i]; - - out_be32(dst, in_be32(src)); - } - } - - smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC1]; - out_be16(&smp->smc_rpbase, 0x1ec0); - smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC2]; - out_be16(&smp->smc_rpbase, 0x1fc0); - } - - out_be16(&cp->cp_cpmcr1, patch_params.cpmcr1); - out_be16(&cp->cp_cpmcr2, patch_params.cpmcr2); - out_be16(&cp->cp_cpmcr3, patch_params.cpmcr3); - out_be16(&cp->cp_cpmcr4, patch_params.cpmcr4); - - out_be16(&cp->cp_rccr, patch_params.rccr); - - pr_info("%s microcode patch installed\n", patch_name); -} diff --git a/drivers/media/i2c/vs6624.c b/drivers/media/i2c/vs6624.c deleted file mode 100644 index c292c92e37b9..000000000000 --- a/drivers/media/i2c/vs6624.c +++ /dev/null @@ -1,856 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * vs6624.c ST VS6624 CMOS image sensor driver - * - * Copyright (c) 2011 Analog Devices Inc. - */ - -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <linux/videodev2.h> - -#include <media/v4l2-ctrls.h> -#include <media/v4l2-device.h> -#include <media/v4l2-mediabus.h> -#include <media/v4l2-image-sizes.h> - -#include "vs6624_regs.h" - -#define MAX_FRAME_RATE 30 - -struct vs6624 { - struct v4l2_subdev sd; - struct v4l2_ctrl_handler hdl; - struct v4l2_fract frame_rate; - struct v4l2_mbus_framefmt fmt; - unsigned ce_pin; -}; - -static const struct vs6624_format { - u32 mbus_code; - enum v4l2_colorspace colorspace; -} vs6624_formats[] = { - { - .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, - .colorspace = V4L2_COLORSPACE_JPEG, - }, - { - .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, - .colorspace = V4L2_COLORSPACE_JPEG, - }, - { - .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, - .colorspace = V4L2_COLORSPACE_SRGB, - }, -}; - -static const struct v4l2_mbus_framefmt vs6624_default_fmt = { - .width = VGA_WIDTH, - .height = VGA_HEIGHT, - .code = MEDIA_BUS_FMT_UYVY8_2X8, - .field = V4L2_FIELD_NONE, - .colorspace = V4L2_COLORSPACE_JPEG, -}; - -static const u16 vs6624_p1[] = { - 0x8104, 0x03, - 0x8105, 0x01, - 0xc900, 0x03, - 0xc904, 0x47, - 0xc905, 0x10, - 0xc906, 0x80, - 0xc907, 0x3a, - 0x903a, 0x02, - 0x903b, 0x47, - 0x903c, 0x15, - 0xc908, 0x31, - 0xc909, 0xdc, - 0xc90a, 0x80, - 0xc90b, 0x44, - 0x9044, 0x02, - 0x9045, 0x31, - 0x9046, 0xe2, - 0xc90c, 0x07, - 0xc90d, 0xe0, - 0xc90e, 0x80, - 0xc90f, 0x47, - 0x9047, 0x90, - 0x9048, 0x83, - 0x9049, 0x81, - 0x904a, 0xe0, - 0x904b, 0x60, - 0x904c, 0x08, - 0x904d, 0x90, - 0x904e, 0xc0, - 0x904f, 0x43, - 0x9050, 0x74, - 0x9051, 0x01, - 0x9052, 0xf0, - 0x9053, 0x80, - 0x9054, 0x05, - 0x9055, 0xE4, - 0x9056, 0x90, - 0x9057, 0xc0, - 0x9058, 0x43, - 0x9059, 0xf0, - 0x905a, 0x02, - 0x905b, 0x07, - 0x905c, 0xec, - 0xc910, 0x5d, - 0xc911, 0xca, - 0xc912, 0x80, - 0xc913, 0x5d, - 0x905d, 0xa3, - 0x905e, 0x04, - 0x905f, 0xf0, - 0x9060, 0xa3, - 0x9061, 0x04, - 0x9062, 0xf0, - 0x9063, 0x22, - 0xc914, 0x72, - 0xc915, 0x92, - 0xc916, 0x80, - 0xc917, 0x64, - 0x9064, 0x74, - 0x9065, 0x01, - 0x9066, 0x02, - 0x9067, 0x72, - 0x9068, 0x95, - 0xc918, 0x47, - 0xc919, 0xf2, - 0xc91a, 0x81, - 0xc91b, 0x69, - 0x9169, 0x74, - 0x916a, 0x02, - 0x916b, 0xf0, - 0x916c, 0xec, - 0x916d, 0xb4, - 0x916e, 0x10, - 0x916f, 0x0a, - 0x9170, 0x90, - 0x9171, 0x80, - 0x9172, 0x16, - 0x9173, 0xe0, - 0x9174, 0x70, - 0x9175, 0x04, - 0x9176, 0x90, - 0x9177, 0xd3, - 0x9178, 0xc4, - 0x9179, 0xf0, - 0x917a, 0x22, - 0xc91c, 0x0a, - 0xc91d, 0xbe, - 0xc91e, 0x80, - 0xc91f, 0x73, - 0x9073, 0xfc, - 0x9074, 0xa3, - 0x9075, 0xe0, - 0x9076, 0xf5, - 0x9077, 0x82, - 0x9078, 0x8c, - 0x9079, 0x83, - 0x907a, 0xa3, - 0x907b, 0xa3, - 0x907c, 0xe0, - 0x907d, 0xfc, - 0x907e, 0xa3, - 0x907f, 0xe0, - 0x9080, 0xc3, - 0x9081, 0x9f, - 0x9082, 0xff, - 0x9083, 0xec, - 0x9084, 0x9e, - 0x9085, 0xfe, - 0x9086, 0x02, - 0x9087, 0x0a, - 0x9088, 0xea, - 0xc920, 0x47, - 0xc921, 0x38, - 0xc922, 0x80, - 0xc923, 0x89, - 0x9089, 0xec, - 0x908a, 0xd3, - 0x908b, 0x94, - 0x908c, 0x20, - 0x908d, 0x40, - 0x908e, 0x01, - 0x908f, 0x1c, - 0x9090, 0x90, - 0x9091, 0xd3, - 0x9092, 0xd4, - 0x9093, 0xec, - 0x9094, 0xf0, - 0x9095, 0x02, - 0x9096, 0x47, - 0x9097, 0x3d, - 0xc924, 0x45, - 0xc925, 0xca, - 0xc926, 0x80, - 0xc927, 0x98, - 0x9098, 0x12, - 0x9099, 0x77, - 0x909a, 0xd6, - 0x909b, 0x02, - 0x909c, 0x45, - 0x909d, 0xcd, - 0xc928, 0x20, - 0xc929, 0xd5, - 0xc92a, 0x80, - 0xc92b, 0x9e, - 0x909e, 0x90, - 0x909f, 0x82, - 0x90a0, 0x18, - 0x90a1, 0xe0, - 0x90a2, 0xb4, - 0x90a3, 0x03, - 0x90a4, 0x0e, - 0x90a5, 0x90, - 0x90a6, 0x83, - 0x90a7, 0xbf, - 0x90a8, 0xe0, - 0x90a9, 0x60, - 0x90aa, 0x08, - 0x90ab, 0x90, - 0x90ac, 0x81, - 0x90ad, 0xfc, - 0x90ae, 0xe0, - 0x90af, 0xff, - 0x90b0, 0xc3, - 0x90b1, 0x13, - 0x90b2, 0xf0, - 0x90b3, 0x90, - 0x90b4, 0x81, - 0x90b5, 0xfc, - 0x90b6, 0xe0, - 0x90b7, 0xff, - 0x90b8, 0x02, - 0x90b9, 0x20, - 0x90ba, 0xda, - 0xc92c, 0x70, - 0xc92d, 0xbc, - 0xc92e, 0x80, - 0xc92f, 0xbb, - 0x90bb, 0x90, - 0x90bc, 0x82, - 0x90bd, 0x18, - 0x90be, 0xe0, - 0x90bf, 0xb4, - 0x90c0, 0x03, - 0x90c1, 0x06, - 0x90c2, 0x90, - 0x90c3, 0xc1, - 0x90c4, 0x06, - 0x90c5, 0x74, - 0x90c6, 0x05, - 0x90c7, 0xf0, - 0x90c8, 0x90, - 0x90c9, 0xd3, - 0x90ca, 0xa0, - 0x90cb, 0x02, - 0x90cc, 0x70, - 0x90cd, 0xbf, - 0xc930, 0x72, - 0xc931, 0x21, - 0xc932, 0x81, - 0xc933, 0x3b, - 0x913b, 0x7d, - 0x913c, 0x02, - 0x913d, 0x7f, - 0x913e, 0x7b, - 0x913f, 0x02, - 0x9140, 0x72, - 0x9141, 0x25, - 0xc934, 0x28, - 0xc935, 0xae, - 0xc936, 0x80, - 0xc937, 0xd2, - 0x90d2, 0xf0, - 0x90d3, 0x90, - 0x90d4, 0xd2, - 0x90d5, 0x0a, - 0x90d6, 0x02, - 0x90d7, 0x28, - 0x90d8, 0xb4, - 0xc938, 0x28, - 0xc939, 0xb1, - 0xc93a, 0x80, - 0xc93b, 0xd9, - 0x90d9, 0x90, - 0x90da, 0x83, - 0x90db, 0xba, - 0x90dc, 0xe0, - 0x90dd, 0xff, - 0x90de, 0x90, - 0x90df, 0xd2, - 0x90e0, 0x08, - 0x90e1, 0xe0, - 0x90e2, 0xe4, - 0x90e3, 0xef, - 0x90e4, 0xf0, - 0x90e5, 0xa3, - 0x90e6, 0xe0, - 0x90e7, 0x74, - 0x90e8, 0xff, - 0x90e9, 0xf0, - 0x90ea, 0x90, - 0x90eb, 0xd2, - 0x90ec, 0x0a, - 0x90ed, 0x02, - 0x90ee, 0x28, - 0x90ef, 0xb4, - 0xc93c, 0x29, - 0xc93d, 0x79, - 0xc93e, 0x80, - 0xc93f, 0xf0, - 0x90f0, 0xf0, - 0x90f1, 0x90, - 0x90f2, 0xd2, - 0x90f3, 0x0e, - 0x90f4, 0x02, - 0x90f5, 0x29, - 0x90f6, 0x7f, - 0xc940, 0x29, - 0xc941, 0x7c, - 0xc942, 0x80, - 0xc943, 0xf7, - 0x90f7, 0x90, - 0x90f8, 0x83, - 0x90f9, 0xba, - 0x90fa, 0xe0, - 0x90fb, 0xff, - 0x90fc, 0x90, - 0x90fd, 0xd2, - 0x90fe, 0x0c, - 0x90ff, 0xe0, - 0x9100, 0xe4, - 0x9101, 0xef, - 0x9102, 0xf0, - 0x9103, 0xa3, - 0x9104, 0xe0, - 0x9105, 0x74, - 0x9106, 0xff, - 0x9107, 0xf0, - 0x9108, 0x90, - 0x9109, 0xd2, - 0x910a, 0x0e, - 0x910b, 0x02, - 0x910c, 0x29, - 0x910d, 0x7f, - 0xc944, 0x2a, - 0xc945, 0x42, - 0xc946, 0x81, - 0xc947, 0x0e, - 0x910e, 0xf0, - 0x910f, 0x90, - 0x9110, 0xd2, - 0x9111, 0x12, - 0x9112, 0x02, - 0x9113, 0x2a, - 0x9114, 0x48, - 0xc948, 0x2a, - 0xc949, 0x45, - 0xc94a, 0x81, - 0xc94b, 0x15, - 0x9115, 0x90, - 0x9116, 0x83, - 0x9117, 0xba, - 0x9118, 0xe0, - 0x9119, 0xff, - 0x911a, 0x90, - 0x911b, 0xd2, - 0x911c, 0x10, - 0x911d, 0xe0, - 0x911e, 0xe4, - 0x911f, 0xef, - 0x9120, 0xf0, - 0x9121, 0xa3, - 0x9122, 0xe0, - 0x9123, 0x74, - 0x9124, 0xff, - 0x9125, 0xf0, - 0x9126, 0x90, - 0x9127, 0xd2, - 0x9128, 0x12, - 0x9129, 0x02, - 0x912a, 0x2a, - 0x912b, 0x48, - 0xc900, 0x01, - 0x0000, 0x00, -}; - -static const u16 vs6624_p2[] = { - 0x806f, 0x01, - 0x058c, 0x01, - 0x0000, 0x00, -}; - -static const u16 vs6624_run_setup[] = { - 0x1d18, 0x00, /* Enableconstrainedwhitebalance */ - VS6624_PEAK_MIN_OUT_G_MSB, 0x3c, /* Damper PeakGain Output MSB */ - VS6624_PEAK_MIN_OUT_G_LSB, 0x66, /* Damper PeakGain Output LSB */ - VS6624_CM_LOW_THR_MSB, 0x65, /* Damper Low MSB */ - VS6624_CM_LOW_THR_LSB, 0xd1, /* Damper Low LSB */ - VS6624_CM_HIGH_THR_MSB, 0x66, /* Damper High MSB */ - VS6624_CM_HIGH_THR_LSB, 0x62, /* Damper High LSB */ - VS6624_CM_MIN_OUT_MSB, 0x00, /* Damper Min output MSB */ - VS6624_CM_MIN_OUT_LSB, 0x00, /* Damper Min output LSB */ - VS6624_NORA_DISABLE, 0x00, /* Nora fDisable */ - VS6624_NORA_USAGE, 0x04, /* Nora usage */ - VS6624_NORA_LOW_THR_MSB, 0x63, /* Damper Low MSB Changed 0x63 to 0x65 */ - VS6624_NORA_LOW_THR_LSB, 0xd1, /* Damper Low LSB */ - VS6624_NORA_HIGH_THR_MSB, 0x68, /* Damper High MSB */ - VS6624_NORA_HIGH_THR_LSB, 0xdd, /* Damper High LSB */ - VS6624_NORA_MIN_OUT_MSB, 0x3a, /* Damper Min output MSB */ - VS6624_NORA_MIN_OUT_LSB, 0x00, /* Damper Min output LSB */ - VS6624_F2B_DISABLE, 0x00, /* Disable */ - 0x1d8a, 0x30, /* MAXWeightHigh */ - 0x1d91, 0x62, /* fpDamperLowThresholdHigh MSB */ - 0x1d92, 0x4a, /* fpDamperLowThresholdHigh LSB */ - 0x1d95, 0x65, /* fpDamperHighThresholdHigh MSB */ - 0x1d96, 0x0e, /* fpDamperHighThresholdHigh LSB */ - 0x1da1, 0x3a, /* fpMinimumDamperOutputLow MSB */ - 0x1da2, 0xb8, /* fpMinimumDamperOutputLow LSB */ - 0x1e08, 0x06, /* MAXWeightLow */ - 0x1e0a, 0x0a, /* MAXWeightHigh */ - 0x1601, 0x3a, /* Red A MSB */ - 0x1602, 0x14, /* Red A LSB */ - 0x1605, 0x3b, /* Blue A MSB */ - 0x1606, 0x85, /* BLue A LSB */ - 0x1609, 0x3b, /* RED B MSB */ - 0x160a, 0x85, /* RED B LSB */ - 0x160d, 0x3a, /* Blue B MSB */ - 0x160e, 0x14, /* Blue B LSB */ - 0x1611, 0x30, /* Max Distance from Locus MSB */ - 0x1612, 0x8f, /* Max Distance from Locus MSB */ - 0x1614, 0x01, /* Enable constrainer */ - 0x0000, 0x00, -}; - -static const u16 vs6624_default[] = { - VS6624_CONTRAST0, 0x84, - VS6624_SATURATION0, 0x75, - VS6624_GAMMA0, 0x11, - VS6624_CONTRAST1, 0x84, - VS6624_SATURATION1, 0x75, - VS6624_GAMMA1, 0x11, - VS6624_MAN_RG, 0x80, - VS6624_MAN_GG, 0x80, - VS6624_MAN_BG, 0x80, - VS6624_WB_MODE, 0x1, - VS6624_EXPO_COMPENSATION, 0xfe, - VS6624_EXPO_METER, 0x0, - VS6624_LIGHT_FREQ, 0x64, - VS6624_PEAK_GAIN, 0xe, - VS6624_PEAK_LOW_THR, 0x28, - VS6624_HMIRROR0, 0x0, - VS6624_VFLIP0, 0x0, - VS6624_ZOOM_HSTEP0_MSB, 0x0, - VS6624_ZOOM_HSTEP0_LSB, 0x1, - VS6624_ZOOM_VSTEP0_MSB, 0x0, - VS6624_ZOOM_VSTEP0_LSB, 0x1, - VS6624_PAN_HSTEP0_MSB, 0x0, - VS6624_PAN_HSTEP0_LSB, 0xf, - VS6624_PAN_VSTEP0_MSB, 0x0, - VS6624_PAN_VSTEP0_LSB, 0xf, - VS6624_SENSOR_MODE, 0x1, - VS6624_SYNC_CODE_SETUP, 0x21, - VS6624_DISABLE_FR_DAMPER, 0x0, - VS6624_FR_DEN, 0x1, - VS6624_FR_NUM_LSB, 0xf, - VS6624_INIT_PIPE_SETUP, 0x0, - VS6624_IMG_FMT0, 0x0, - VS6624_YUV_SETUP, 0x1, - VS6624_IMAGE_SIZE0, 0x2, - 0x0000, 0x00, -}; - -static inline struct vs6624 *to_vs6624(struct v4l2_subdev *sd) -{ - return container_of(sd, struct vs6624, sd); -} -static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) -{ - return &container_of(ctrl->handler, struct vs6624, hdl)->sd; -} - -#ifdef CONFIG_VIDEO_ADV_DEBUG -static int vs6624_read(struct v4l2_subdev *sd, u16 index) -{ - struct i2c_client *client = v4l2_get_subdevdata(sd); - u8 buf[2]; - - buf[0] = index >> 8; - buf[1] = index; - i2c_master_send(client, buf, 2); - i2c_master_recv(client, buf, 1); - - return buf[0]; -} -#endif - -static int vs6624_write(struct v4l2_subdev *sd, u16 index, - u8 value) -{ - struct i2c_client *client = v4l2_get_subdevdata(sd); - u8 buf[3]; - - buf[0] = index >> 8; - buf[1] = index; - buf[2] = value; - - return i2c_master_send(client, buf, 3); -} - -static int vs6624_writeregs(struct v4l2_subdev *sd, const u16 *regs) -{ - u16 reg; - u8 data; - - while (*regs != 0x00) { - reg = *regs++; - data = *regs++; - - vs6624_write(sd, reg, data); - } - return 0; -} - -static int vs6624_s_ctrl(struct v4l2_ctrl *ctrl) -{ - struct v4l2_subdev *sd = to_sd(ctrl); - - switch (ctrl->id) { - case V4L2_CID_CONTRAST: - vs6624_write(sd, VS6624_CONTRAST0, ctrl->val); - break; - case V4L2_CID_SATURATION: - vs6624_write(sd, VS6624_SATURATION0, ctrl->val); - break; - case V4L2_CID_HFLIP: - vs6624_write(sd, VS6624_HMIRROR0, ctrl->val); - break; - case V4L2_CID_VFLIP: - vs6624_write(sd, VS6624_VFLIP0, ctrl->val); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int vs6624_enum_mbus_code(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_mbus_code_enum *code) -{ - if (code->pad || code->index >= ARRAY_SIZE(vs6624_formats)) - return -EINVAL; - - code->code = vs6624_formats[code->index].mbus_code; - return 0; -} - -static int vs6624_set_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *format) -{ - struct v4l2_mbus_framefmt *fmt = &format->format; - struct vs6624 *sensor = to_vs6624(sd); - int index; - - if (format->pad) - return -EINVAL; - - for (index = 0; index < ARRAY_SIZE(vs6624_formats); index++) - if (vs6624_formats[index].mbus_code == fmt->code) - break; - if (index >= ARRAY_SIZE(vs6624_formats)) { - /* default to first format */ - index = 0; - fmt->code = vs6624_formats[0].mbus_code; - } - - /* sensor mode is VGA */ - if (fmt->width > VGA_WIDTH) - fmt->width = VGA_WIDTH; - if (fmt->height > VGA_HEIGHT) - fmt->height = VGA_HEIGHT; - fmt->width = fmt->width & (~3); - fmt->height = fmt->height & (~3); - fmt->field = V4L2_FIELD_NONE; - fmt->colorspace = vs6624_formats[index].colorspace; - - if (format->which == V4L2_SUBDEV_FORMAT_TRY) { - cfg->try_fmt = *fmt; - return 0; - } - - /* set image format */ - switch (fmt->code) { - case MEDIA_BUS_FMT_UYVY8_2X8: - vs6624_write(sd, VS6624_IMG_FMT0, 0x0); - vs6624_write(sd, VS6624_YUV_SETUP, 0x1); - break; - case MEDIA_BUS_FMT_YUYV8_2X8: - vs6624_write(sd, VS6624_IMG_FMT0, 0x0); - vs6624_write(sd, VS6624_YUV_SETUP, 0x3); - break; - case MEDIA_BUS_FMT_RGB565_2X8_LE: - vs6624_write(sd, VS6624_IMG_FMT0, 0x4); - vs6624_write(sd, VS6624_RGB_SETUP, 0x0); - break; - default: - return -EINVAL; - } - - /* set image size */ - if ((fmt->width == VGA_WIDTH) && (fmt->height == VGA_HEIGHT)) - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x2); - else if ((fmt->width == QVGA_WIDTH) && (fmt->height == QVGA_HEIGHT)) - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x4); - else if ((fmt->width == QQVGA_WIDTH) && (fmt->height == QQVGA_HEIGHT)) - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x6); - else if ((fmt->width == CIF_WIDTH) && (fmt->height == CIF_HEIGHT)) - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x3); - else if ((fmt->width == QCIF_WIDTH) && (fmt->height == QCIF_HEIGHT)) - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x5); - else if ((fmt->width == QQCIF_WIDTH) && (fmt->height == QQCIF_HEIGHT)) - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x7); - else { - vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x8); - vs6624_write(sd, VS6624_MAN_HSIZE0_MSB, fmt->width >> 8); - vs6624_write(sd, VS6624_MAN_HSIZE0_LSB, fmt->width & 0xFF); - vs6624_write(sd, VS6624_MAN_VSIZE0_MSB, fmt->height >> 8); - vs6624_write(sd, VS6624_MAN_VSIZE0_LSB, fmt->height & 0xFF); - vs6624_write(sd, VS6624_CROP_CTRL0, 0x1); - } - - sensor->fmt = *fmt; - - return 0; -} - -static int vs6624_get_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *format) -{ - struct vs6624 *sensor = to_vs6624(sd); - - if (format->pad) - return -EINVAL; - - format->format = sensor->fmt; - return 0; -} - -static int vs6624_g_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_frame_interval *ival) -{ - struct vs6624 *sensor = to_vs6624(sd); - - ival->interval.numerator = sensor->frame_rate.denominator; - ival->interval.denominator = sensor->frame_rate.numerator; - return 0; -} - -static int vs6624_s_frame_interval(struct v4l2_subdev *sd, - struct v4l2_subdev_frame_interval *ival) -{ - struct vs6624 *sensor = to_vs6624(sd); - struct v4l2_fract *tpf = &ival->interval; - - - if (tpf->numerator == 0 || tpf->denominator == 0 - || (tpf->denominator > tpf->numerator * MAX_FRAME_RATE)) { - /* reset to max frame rate */ - tpf->numerator = 1; - tpf->denominator = MAX_FRAME_RATE; - } - sensor->frame_rate.numerator = tpf->denominator; - sensor->frame_rate.denominator = tpf->numerator; - vs6624_write(sd, VS6624_DISABLE_FR_DAMPER, 0x0); - vs6624_write(sd, VS6624_FR_NUM_MSB, - sensor->frame_rate.numerator >> 8); - vs6624_write(sd, VS6624_FR_NUM_LSB, - sensor->frame_rate.numerator & 0xFF); - vs6624_write(sd, VS6624_FR_DEN, - sensor->frame_rate.denominator & 0xFF); - return 0; -} - -static int vs6624_s_stream(struct v4l2_subdev *sd, int enable) -{ - if (enable) - vs6624_write(sd, VS6624_USER_CMD, 0x2); - else - vs6624_write(sd, VS6624_USER_CMD, 0x4); - udelay(100); - return 0; -} - -#ifdef CONFIG_VIDEO_ADV_DEBUG -static int vs6624_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) -{ - reg->val = vs6624_read(sd, reg->reg & 0xffff); - reg->size = 1; - return 0; -} - -static int vs6624_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) -{ - vs6624_write(sd, reg->reg & 0xffff, reg->val & 0xff); - return 0; -} -#endif - -static const struct v4l2_ctrl_ops vs6624_ctrl_ops = { - .s_ctrl = vs6624_s_ctrl, -}; - -static const struct v4l2_subdev_core_ops vs6624_core_ops = { -#ifdef CONFIG_VIDEO_ADV_DEBUG - .g_register = vs6624_g_register, - .s_register = vs6624_s_register, -#endif -}; - -static const struct v4l2_subdev_video_ops vs6624_video_ops = { - .s_frame_interval = vs6624_s_frame_interval, - .g_frame_interval = vs6624_g_frame_interval, - .s_stream = vs6624_s_stream, -}; - -static const struct v4l2_subdev_pad_ops vs6624_pad_ops = { - .enum_mbus_code = vs6624_enum_mbus_code, - .get_fmt = vs6624_get_fmt, - .set_fmt = vs6624_set_fmt, -}; - -static const struct v4l2_subdev_ops vs6624_ops = { - .core = &vs6624_core_ops, - .video = &vs6624_video_ops, - .pad = &vs6624_pad_ops, -}; - -static int vs6624_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct vs6624 *sensor; - struct v4l2_subdev *sd; - struct v4l2_ctrl_handler *hdl; - const unsigned *ce; - int ret; - - /* Check if the adapter supports the needed features */ - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) - return -EIO; - - ce = client->dev.platform_data; - if (ce == NULL) - return -EINVAL; - - ret = devm_gpio_request_one(&client->dev, *ce, GPIOF_OUT_INIT_HIGH, - "VS6624 Chip Enable"); - if (ret) { - v4l_err(client, "failed to request GPIO %d\n", *ce); - return ret; - } - /* wait 100ms before any further i2c writes are performed */ - msleep(100); - - sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL); - if (sensor == NULL) - return -ENOMEM; - - sd = &sensor->sd; - v4l2_i2c_subdev_init(sd, client, &vs6624_ops); - - vs6624_writeregs(sd, vs6624_p1); - vs6624_write(sd, VS6624_MICRO_EN, 0x2); - vs6624_write(sd, VS6624_DIO_EN, 0x1); - usleep_range(10000, 11000); - vs6624_writeregs(sd, vs6624_p2); - - vs6624_writeregs(sd, vs6624_default); - vs6624_write(sd, VS6624_HSYNC_SETUP, 0xF); - vs6624_writeregs(sd, vs6624_run_setup); - - /* set frame rate */ - sensor->frame_rate.numerator = MAX_FRAME_RATE; - sensor->frame_rate.denominator = 1; - vs6624_write(sd, VS6624_DISABLE_FR_DAMPER, 0x0); - vs6624_write(sd, VS6624_FR_NUM_MSB, - sensor->frame_rate.numerator >> 8); - vs6624_write(sd, VS6624_FR_NUM_LSB, - sensor->frame_rate.numerator & 0xFF); - vs6624_write(sd, VS6624_FR_DEN, - sensor->frame_rate.denominator & 0xFF); - - sensor->fmt = vs6624_default_fmt; - sensor->ce_pin = *ce; - - v4l_info(client, "chip found @ 0x%02x (%s)\n", - client->addr << 1, client->adapter->name); - - hdl = &sensor->hdl; - v4l2_ctrl_handler_init(hdl, 4); - v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops, - V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x87); - v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops, - V4L2_CID_SATURATION, 0, 0xFF, 1, 0x78); - v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops, - V4L2_CID_HFLIP, 0, 1, 1, 0); - v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops, - V4L2_CID_VFLIP, 0, 1, 1, 0); - /* hook the control handler into the driver */ - sd->ctrl_handler = hdl; - if (hdl->error) { - int err = hdl->error; - - v4l2_ctrl_handler_free(hdl); - return err; - } - - /* initialize the hardware to the default control values */ - ret = v4l2_ctrl_handler_setup(hdl); - if (ret) - v4l2_ctrl_handler_free(hdl); - return ret; -} - -static int vs6624_remove(struct i2c_client *client) -{ - struct v4l2_subdev *sd = i2c_get_clientdata(client); - - v4l2_device_unregister_subdev(sd); - v4l2_ctrl_handler_free(sd->ctrl_handler); - return 0; -} - -static const struct i2c_device_id vs6624_id[] = { - {"vs6624", 0}, - {}, -}; - -MODULE_DEVICE_TABLE(i2c, vs6624_id); - -static struct i2c_driver vs6624_driver = { - .driver = { - .name = "vs6624", - }, - .probe = vs6624_probe, - .remove = vs6624_remove, - .id_table = vs6624_id, -}; - -module_i2c_driver(vs6624_driver); - -MODULE_DESCRIPTION("VS6624 sensor driver"); -MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/usb/dvb-usb/af9005-script.h b/drivers/media/usb/dvb-usb/af9005-script.h deleted file mode 100644 index 870cb59cd904..000000000000 --- a/drivers/media/usb/dvb-usb/af9005-script.h +++ /dev/null @@ -1,204 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* -File automatically generated by createinit.py using data -extracted from AF05BDA.sys (windows driver): - -dd if=AF05BDA.sys of=initsequence bs=1 skip=88316 count=1110 -python createinit.py > af9005-script.h - -*/ - -typedef struct { - u16 reg; - u8 pos; - u8 len; - u8 val; -} RegDesc; - -static RegDesc script[] = { - {0xa180, 0x0, 0x8, 0xa}, - {0xa181, 0x0, 0x8, 0xd7}, - {0xa182, 0x0, 0x8, 0xa3}, - {0xa0a0, 0x0, 0x8, 0x0}, - {0xa0a1, 0x0, 0x5, 0x0}, - {0xa0a1, 0x5, 0x1, 0x1}, - {0xa0c0, 0x0, 0x4, 0x1}, - {0xa20e, 0x4, 0x4, 0xa}, - {0xa20f, 0x0, 0x8, 0x40}, - {0xa210, 0x0, 0x8, 0x8}, - {0xa32a, 0x0, 0x4, 0xa}, - {0xa32c, 0x0, 0x8, 0x20}, - {0xa32b, 0x0, 0x8, 0x15}, - {0xa1a0, 0x1, 0x1, 0x1}, - {0xa000, 0x0, 0x1, 0x1}, - {0xa000, 0x1, 0x1, 0x0}, - {0xa001, 0x1, 0x1, 0x1}, - {0xa001, 0x0, 0x1, 0x0}, - {0xa001, 0x5, 0x1, 0x0}, - {0xa00e, 0x0, 0x5, 0x10}, - {0xa00f, 0x0, 0x3, 0x4}, - {0xa00f, 0x3, 0x3, 0x5}, - {0xa010, 0x0, 0x3, 0x4}, - {0xa010, 0x3, 0x3, 0x5}, - {0xa016, 0x4, 0x4, 0x3}, - {0xa01f, 0x0, 0x6, 0xa}, - {0xa020, 0x0, 0x6, 0xa}, - {0xa2bc, 0x0, 0x1, 0x1}, - {0xa2bc, 0x5, 0x1, 0x1}, - {0xa015, 0x0, 0x8, 0x50}, - {0xa016, 0x0, 0x1, 0x0}, - {0xa02a, 0x0, 0x8, 0x50}, - {0xa029, 0x0, 0x8, 0x4b}, - {0xa614, 0x0, 0x8, 0x46}, - {0xa002, 0x0, 0x5, 0x19}, - {0xa003, 0x0, 0x5, 0x1a}, - {0xa004, 0x0, 0x5, 0x19}, - {0xa005, 0x0, 0x5, 0x1a}, - {0xa008, 0x0, 0x8, 0x69}, - {0xa009, 0x0, 0x2, 0x2}, - {0xae1b, 0x0, 0x8, 0x69}, - {0xae1c, 0x0, 0x8, 0x2}, - {0xae1d, 0x0, 0x8, 0x2a}, - {0xa022, 0x0, 0x8, 0xaa}, - {0xa006, 0x0, 0x8, 0xc8}, - {0xa007, 0x0, 0x2, 0x0}, - {0xa00c, 0x0, 0x8, 0xba}, - {0xa00d, 0x0, 0x2, 0x2}, - {0xa608, 0x0, 0x8, 0xba}, - {0xa60e, 0x0, 0x2, 0x2}, - {0xa609, 0x0, 0x8, 0x80}, - {0xa60e, 0x2, 0x2, 0x3}, - {0xa00a, 0x0, 0x8, 0xb6}, - {0xa00b, 0x0, 0x2, 0x0}, - {0xa011, 0x0, 0x8, 0xb9}, - {0xa012, 0x0, 0x2, 0x0}, - {0xa013, 0x0, 0x8, 0xbd}, - {0xa014, 0x0, 0x2, 0x2}, - {0xa366, 0x0, 0x1, 0x1}, - {0xa2bc, 0x3, 0x1, 0x0}, - {0xa2bd, 0x0, 0x8, 0xa}, - {0xa2be, 0x0, 0x8, 0x14}, - {0xa2bf, 0x0, 0x8, 0x8}, - {0xa60a, 0x0, 0x8, 0xbd}, - {0xa60e, 0x4, 0x2, 0x2}, - {0xa60b, 0x0, 0x8, 0x86}, - {0xa60e, 0x6, 0x2, 0x3}, - {0xa001, 0x2, 0x2, 0x1}, - {0xa1c7, 0x0, 0x8, 0xf5}, - {0xa03d, 0x0, 0x8, 0xb1}, - {0xa616, 0x0, 0x8, 0xff}, - {0xa617, 0x0, 0x8, 0xad}, - {0xa618, 0x0, 0x8, 0xad}, - {0xa61e, 0x3, 0x1, 0x1}, - {0xae1a, 0x0, 0x8, 0x0}, - {0xae19, 0x0, 0x8, 0xc8}, - {0xae18, 0x0, 0x8, 0x61}, - {0xa140, 0x0, 0x8, 0x0}, - {0xa141, 0x0, 0x8, 0xc8}, - {0xa142, 0x0, 0x7, 0x61}, - {0xa023, 0x0, 0x8, 0xff}, - {0xa021, 0x0, 0x8, 0xad}, - {0xa026, 0x0, 0x1, 0x0}, - {0xa024, 0x0, 0x8, 0xff}, - {0xa025, 0x0, 0x8, 0xff}, - {0xa1c8, 0x0, 0x8, 0xf}, - {0xa2bc, 0x1, 0x1, 0x0}, - {0xa60c, 0x0, 0x4, 0x5}, - {0xa60c, 0x4, 0x4, 0x6}, - {0xa60d, 0x0, 0x8, 0xa}, - {0xa371, 0x0, 0x1, 0x1}, - {0xa366, 0x1, 0x3, 0x7}, - {0xa338, 0x0, 0x8, 0x10}, - {0xa339, 0x0, 0x6, 0x7}, - {0xa33a, 0x0, 0x6, 0x1f}, - {0xa33b, 0x0, 0x8, 0xf6}, - {0xa33c, 0x3, 0x5, 0x4}, - {0xa33d, 0x4, 0x4, 0x0}, - {0xa33d, 0x1, 0x1, 0x1}, - {0xa33d, 0x2, 0x1, 0x1}, - {0xa33d, 0x3, 0x1, 0x1}, - {0xa16d, 0x0, 0x4, 0xf}, - {0xa161, 0x0, 0x5, 0x5}, - {0xa162, 0x0, 0x4, 0x5}, - {0xa165, 0x0, 0x8, 0xff}, - {0xa166, 0x0, 0x8, 0x9c}, - {0xa2c3, 0x0, 0x4, 0x5}, - {0xa61a, 0x0, 0x6, 0xf}, - {0xb200, 0x0, 0x8, 0xa1}, - {0xb201, 0x0, 0x8, 0x7}, - {0xa093, 0x0, 0x1, 0x0}, - {0xa093, 0x1, 0x5, 0xf}, - {0xa094, 0x0, 0x8, 0xff}, - {0xa095, 0x0, 0x8, 0xf}, - {0xa080, 0x2, 0x5, 0x3}, - {0xa081, 0x0, 0x4, 0x0}, - {0xa081, 0x4, 0x4, 0x9}, - {0xa082, 0x0, 0x5, 0x1f}, - {0xa08d, 0x0, 0x8, 0x1}, - {0xa083, 0x0, 0x8, 0x32}, - {0xa084, 0x0, 0x1, 0x0}, - {0xa08e, 0x0, 0x8, 0x3}, - {0xa085, 0x0, 0x8, 0x32}, - {0xa086, 0x0, 0x3, 0x0}, - {0xa087, 0x0, 0x8, 0x6e}, - {0xa088, 0x0, 0x5, 0x15}, - {0xa089, 0x0, 0x8, 0x0}, - {0xa08a, 0x0, 0x5, 0x19}, - {0xa08b, 0x0, 0x8, 0x92}, - {0xa08c, 0x0, 0x5, 0x1c}, - {0xa120, 0x0, 0x8, 0x0}, - {0xa121, 0x0, 0x5, 0x10}, - {0xa122, 0x0, 0x8, 0x0}, - {0xa123, 0x0, 0x7, 0x40}, - {0xa123, 0x7, 0x1, 0x0}, - {0xa124, 0x0, 0x8, 0x13}, - {0xa125, 0x0, 0x7, 0x10}, - {0xa1c0, 0x0, 0x8, 0x0}, - {0xa1c1, 0x0, 0x5, 0x4}, - {0xa1c2, 0x0, 0x8, 0x0}, - {0xa1c3, 0x0, 0x5, 0x10}, - {0xa1c3, 0x5, 0x3, 0x0}, - {0xa1c4, 0x0, 0x6, 0x0}, - {0xa1c5, 0x0, 0x7, 0x10}, - {0xa100, 0x0, 0x8, 0x0}, - {0xa101, 0x0, 0x5, 0x10}, - {0xa102, 0x0, 0x8, 0x0}, - {0xa103, 0x0, 0x7, 0x40}, - {0xa103, 0x7, 0x1, 0x0}, - {0xa104, 0x0, 0x8, 0x18}, - {0xa105, 0x0, 0x7, 0xa}, - {0xa106, 0x0, 0x8, 0x20}, - {0xa107, 0x0, 0x8, 0x40}, - {0xa108, 0x0, 0x4, 0x0}, - {0xa38c, 0x0, 0x8, 0xfc}, - {0xa38d, 0x0, 0x8, 0x0}, - {0xa38e, 0x0, 0x8, 0x7e}, - {0xa38f, 0x0, 0x8, 0x0}, - {0xa390, 0x0, 0x8, 0x2f}, - {0xa60f, 0x5, 0x1, 0x1}, - {0xa170, 0x0, 0x8, 0xdc}, - {0xa171, 0x0, 0x2, 0x0}, - {0xa2ae, 0x0, 0x1, 0x1}, - {0xa2ae, 0x1, 0x1, 0x1}, - {0xa392, 0x0, 0x1, 0x1}, - {0xa391, 0x2, 0x1, 0x0}, - {0xabc1, 0x0, 0x8, 0xff}, - {0xabc2, 0x0, 0x8, 0x0}, - {0xabc8, 0x0, 0x8, 0x8}, - {0xabca, 0x0, 0x8, 0x10}, - {0xabcb, 0x0, 0x1, 0x0}, - {0xabc3, 0x5, 0x3, 0x7}, - {0xabc0, 0x6, 0x1, 0x0}, - {0xabc0, 0x4, 0x2, 0x0}, - {0xa344, 0x4, 0x4, 0x1}, - {0xabc0, 0x7, 0x1, 0x1}, - {0xabc0, 0x2, 0x1, 0x1}, - {0xa345, 0x0, 0x8, 0x66}, - {0xa346, 0x0, 0x8, 0x66}, - {0xa347, 0x0, 0x4, 0x0}, - {0xa343, 0x0, 0x4, 0xa}, - {0xa347, 0x4, 0x4, 0x2}, - {0xa348, 0x0, 0x4, 0xc}, - {0xa348, 0x4, 0x4, 0x7}, - {0xa349, 0x0, 0x6, 0x2}, -}; diff --git a/drivers/net/appletalk/cops.c b/drivers/net/appletalk/cops.c deleted file mode 100644 index 6b12ce822e51..000000000000 --- a/drivers/net/appletalk/cops.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* cops.c: LocalTalk driver for Linux. - * - * Authors: - * - Jay Schulist <jschlst@samba.org> - * - * With more than a little help from; - * - Alan Cox <alan@lxorguk.ukuu.org.uk> - * - * Derived from: - * - skeleton.c: A network driver outline for linux. - * Written 1993-94 by Donald Becker. - * - ltpc.c: A driver for the LocalTalk PC card. - * Written by Bradford W. Johnson. - * - * Copyright 1993 United States Government as represented by the - * Director, National Security Agency. - * - * This software may be used and distributed according to the terms - * of the GNU General Public License, incorporated herein by reference. - * - * Changes: - * 19970608 Alan Cox Allowed dual card type support - * Can set board type in insmod - * Hooks for cops_setup routine - * (not yet implemented). - * 19971101 Jay Schulist Fixes for multiple lt* devices. - * 19980607 Steven Hirsch Fixed the badly broken support - * for Tangent type cards. Only - * tested on Daystar LT200. Some - * cleanup of formatting and program - * logic. Added emacs 'local-vars' - * setup for Jay's brace style. - * 20000211 Alan Cox Cleaned up for softnet - */ - -static const char *version = -"cops.c:v0.04 6/7/98 Jay Schulist <jschlst@samba.org>\n"; -/* - * Sources: - * COPS Localtalk SDK. This provides almost all of the information - * needed. - */ - -/* - * insmod/modprobe configurable stuff. - * - IO Port, choose one your card supports or 0 if you dare. - * - IRQ, also choose one your card supports or nothing and let - * the driver figure it out. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/fcntl.h> -#include <linux/interrupt.h> -#include <linux/ptrace.h> -#include <linux/ioport.h> -#include <linux/in.h> -#include <linux/string.h> -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/netdevice.h> -#include <linux/etherdevice.h> -#include <linux/skbuff.h> -#include <linux/if_arp.h> -#include <linux/if_ltalk.h> -#include <linux/delay.h> /* For udelay() */ -#include <linux/atalk.h> -#include <linux/spinlock.h> -#include <linux/bitops.h> -#include <linux/jiffies.h> - -#include <net/Space.h> - -#include <asm/io.h> -#include <asm/dma.h> - -#include "cops.h" /* Our Stuff */ -#include "cops_ltdrv.h" /* Firmware code for Tangent type cards. */ -#include "cops_ffdrv.h" /* Firmware code for Dayna type cards. */ - -/* - * The name of the card. Is used for messages and in the requests for - * io regions, irqs and dma channels - */ - -static const char *cardname = "cops"; - -#ifdef CONFIG_COPS_DAYNA -static int board_type = DAYNA; /* Module exported */ -#else -static int board_type = TANGENT; -#endif - -static int io = 0x240; /* Default IO for Dayna */ -static int irq = 5; /* Default IRQ */ - -/* - * COPS Autoprobe information. - * Right now if port address is right but IRQ is not 5 this will - * return a 5 no matter what since we will still get a status response. - * Need one more additional check to narrow down after we have gotten - * the ioaddr. But since only other possible IRQs is 3 and 4 so no real - * hurry on this. I *STRONGLY* recommend using IRQ 5 for your card with - * this driver. - * - * This driver has 2 modes and they are: Dayna mode and Tangent mode. - * Each mode corresponds with the type of card. It has been found - * that there are 2 main types of cards and all other cards are - * the same and just have different names or only have minor differences - * such as more IO ports. As this driver is tested it will - * become more clear on exactly what cards are supported. The driver - * defaults to using Dayna mode. To change the drivers mode, simply - * select Dayna or Tangent mode when configuring the kernel. - * - * This driver should support: - * TANGENT driver mode: - * Tangent ATB-II, Novell NL-1000, Daystar Digital LT-200, - * COPS LT-1 - * DAYNA driver mode: - * Dayna DL2000/DaynaTalk PC (Half Length), COPS LT-95, - * Farallon PhoneNET PC III, Farallon PhoneNET PC II - * Other cards possibly supported mode unknown though: - * Dayna DL2000 (Full length), COPS LT/M (Micro-Channel) - * - * Cards NOT supported by this driver but supported by the ltpc.c - * driver written by Bradford W. Johnson <johns393@maroon.tc.umn.edu> - * Farallon PhoneNET PC - * Original Apple LocalTalk PC card - * - * N.B. - * - * The Daystar Digital LT200 boards do not support interrupt-driven - * IO. You must specify 'irq=0xff' as a module parameter to invoke - * polled mode. I also believe that the port probing logic is quite - * dangerous at best and certainly hopeless for a polled card. Best to - * specify both. - Steve H. - * - */ - -/* - * Zero terminated list of IO ports to probe. - */ - -static unsigned int ports[] = { - 0x240, 0x340, 0x200, 0x210, 0x220, 0x230, 0x260, - 0x2A0, 0x300, 0x310, 0x320, 0x330, 0x350, 0x360, - 0 -}; - -/* - * Zero terminated list of IRQ ports to probe. - */ - -static int cops_irqlist[] = { - 5, 4, 3, 0 -}; - -static struct timer_list cops_timer; -static struct net_device *cops_timer_dev; - -/* use 0 for production, 1 for verification, 2 for debug, 3 for verbose debug */ -#ifndef COPS_DEBUG -#define COPS_DEBUG 1 -#endif -static unsigned int cops_debug = COPS_DEBUG; - -/* The number of low I/O ports used by the card. */ -#define COPS_IO_EXTENT 8 - -/* Information that needs to be kept for each board. */ - -struct cops_local -{ - int board; /* Holds what board type is. */ - int nodeid; /* Set to 1 once have nodeid. */ - unsigned char node_acquire; /* Node ID when acquired. */ - struct atalk_addr node_addr; /* Full node address */ - spinlock_t lock; /* RX/TX lock */ -}; - -/* Index to functions, as function prototypes. */ -static int cops_probe1 (struct net_device *dev, int ioaddr); -static int cops_irq (int ioaddr, int board); - -static int cops_open (struct net_device *dev); -static int cops_jumpstart (struct net_device *dev); -static void cops_reset (struct net_device *dev, int sleep); -static void cops_load (struct net_device *dev); -static int cops_nodeid (struct net_device *dev, int nodeid); - -static irqreturn_t cops_interrupt (int irq, void *dev_id); -static void cops_poll(struct timer_list *t); -static void cops_timeout(struct net_device *dev, unsigned int txqueue); -static void cops_rx (struct net_device *dev); -static netdev_tx_t cops_send_packet (struct sk_buff *skb, - struct net_device *dev); -static void set_multicast_list (struct net_device *dev); -static int cops_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); -static int cops_close (struct net_device *dev); - -static void cleanup_card(struct net_device *dev) -{ - if (dev->irq) - free_irq(dev->irq, dev); - release_region(dev->base_addr, COPS_IO_EXTENT); -} - -/* - * Check for a network adaptor of this type, and return '0' iff one exists. - * If dev->base_addr == 0, probe all likely locations. - * If dev->base_addr in [1..0x1ff], always return failure. - * otherwise go with what we pass in. - */ -struct net_device * __init cops_probe(int unit) -{ - struct net_device *dev; - unsigned *port; - int base_addr; - int err = 0; - - dev = alloc_ltalkdev(sizeof(struct cops_local)); - if (!dev) - return ERR_PTR(-ENOMEM); - - if (unit >= 0) { - sprintf(dev->name, "lt%d", unit); - netdev_boot_setup_check(dev); - irq = dev->irq; - base_addr = dev->base_addr; - } else { - base_addr = dev->base_addr = io; - } - - if (base_addr > 0x1ff) { /* Check a single specified location. */ - err = cops_probe1(dev, base_addr); - } else if (base_addr != 0) { /* Don't probe at all. */ - err = -ENXIO; - } else { - /* FIXME Does this really work for cards which generate irq? - * It's definitely N.G. for polled Tangent. sh - * Dayna cards don't autoprobe well at all, but if your card is - * at IRQ 5 & IO 0x240 we find it every time. ;) JS - */ - for (port = ports; *port && cops_probe1(dev, *port) < 0; port++) - ; - if (!*port) - err = -ENODEV; - } - if (err) - goto out; - err = register_netdev(dev); - if (err) - goto out1; - return dev; -out1: - cleanup_card(dev); -out: - free_netdev(dev); - return ERR_PTR(err); -} - -static const struct net_device_ops cops_netdev_ops = { - .ndo_open = cops_open, - .ndo_stop = cops_close, - .ndo_start_xmit = cops_send_packet, - .ndo_tx_timeout = cops_timeout, - .ndo_do_ioctl = cops_ioctl, - .ndo_set_rx_mode = set_multicast_list, -}; - -/* - * This is the real probe routine. Linux has a history of friendly device - * probes on the ISA bus. A good device probes avoids doing writes, and - * verifies that the correct device exists and functions. - */ -static int __init cops_probe1(struct net_device *dev, int ioaddr) -{ - struct cops_local *lp; - static unsigned version_printed; - int board = board_type; - int retval; - - if(cops_debug && version_printed++ == 0) - printk("%s", version); - - /* Grab the region so no one else tries to probe our ioports. */ - if (!request_region(ioaddr, COPS_IO_EXTENT, dev->name)) - return -EBUSY; - - /* - * Since this board has jumpered interrupts, allocate the interrupt - * vector now. There is no point in waiting since no other device - * can use the interrupt, and this marks the irq as busy. Jumpered - * interrupts are typically not reported by the boards, and we must - * used AutoIRQ to find them. - */ - dev->irq = irq; - switch (dev->irq) - { - case 0: - /* COPS AutoIRQ routine */ - dev->irq = cops_irq(ioaddr, board); - if (dev->irq) - break; - fallthrough; /* Once no IRQ found on this port */ - case 1: - retval = -EINVAL; - goto err_out; - - /* Fixup for users that don't know that IRQ 2 is really - * IRQ 9, or don't know which one to set. - */ - case 2: - dev->irq = 9; - break; - - /* Polled operation requested. Although irq of zero passed as - * a parameter tells the init routines to probe, we'll - * overload it to denote polled operation at runtime. - */ - case 0xff: - dev->irq = 0; - break; - - default: - break; - } - - dev->base_addr = ioaddr; - - /* Reserve any actual interrupt. */ - if (dev->irq) { - retval = request_irq(dev->irq, cops_interrupt, 0, dev->name, dev); - if (retval) - goto err_out; - } - - lp = netdev_priv(dev); - spin_lock_init(&lp->lock); - - /* Copy local board variable to lp struct. */ - lp->board = board; - - dev->netdev_ops = &cops_netdev_ops; - dev->watchdog_timeo = HZ * 2; - - - /* Tell the user where the card is and what mode we're in. */ - if(board==DAYNA) - printk("%s: %s at %#3x, using IRQ %d, in Dayna mode.\n", - dev->name, cardname, ioaddr, dev->irq); - if(board==TANGENT) { - if(dev->irq) - printk("%s: %s at %#3x, IRQ %d, in Tangent mode\n", - dev->name, cardname, ioaddr, dev->irq); - else - printk("%s: %s at %#3x, using polled IO, in Tangent mode.\n", - dev->name, cardname, ioaddr); - - } - return 0; - -err_out: - release_region(ioaddr, COPS_IO_EXTENT); - return retval; -} - -static int __init cops_irq (int ioaddr, int board) -{ /* - * This does not use the IRQ to determine where the IRQ is. We just - * assume that when we get a correct status response that it's the IRQ. - * This really just verifies the IO port but since we only have access - * to such a small number of IRQs (5, 4, 3) this is not bad. - * This will probably not work for more than one card. - */ - int irqaddr=0; - int i, x, status; - - if(board==DAYNA) - { - outb(0, ioaddr+DAYNA_RESET); - inb(ioaddr+DAYNA_RESET); - mdelay(333); - } - if(board==TANGENT) - { - inb(ioaddr); - outb(0, ioaddr); - outb(0, ioaddr+TANG_RESET); - } - - for(i=0; cops_irqlist[i] !=0; i++) - { - irqaddr = cops_irqlist[i]; - for(x = 0xFFFF; x>0; x --) /* wait for response */ - { - if(board==DAYNA) - { - status = (inb(ioaddr+DAYNA_CARD_STATUS)&3); - if(status == 1) - return irqaddr; - } - if(board==TANGENT) - { - if((inb(ioaddr+TANG_CARD_STATUS)& TANG_TX_READY) !=0) - return irqaddr; - } - } - } - return 0; /* no IRQ found */ -} - -/* - * Open/initialize the board. This is called (in the current kernel) - * sometime after booting when the 'ifconfig' program is run. - */ -static int cops_open(struct net_device *dev) -{ - struct cops_local *lp = netdev_priv(dev); - - if(dev->irq==0) - { - /* - * I don't know if the Dayna-style boards support polled - * operation. For now, only allow it for Tangent. - */ - if(lp->board==TANGENT) /* Poll 20 times per second */ - { - cops_timer_dev = dev; - timer_setup(&cops_timer, cops_poll, 0); - cops_timer.expires = jiffies + HZ/20; - add_timer(&cops_timer); - } - else - { - printk(KERN_WARNING "%s: No irq line set\n", dev->name); - return -EAGAIN; - } - } - - cops_jumpstart(dev); /* Start the card up. */ - - netif_start_queue(dev); - return 0; -} - -/* - * This allows for a dynamic start/restart of the entire card. - */ -static int cops_jumpstart(struct net_device *dev) -{ - struct cops_local *lp = netdev_priv(dev); - - /* - * Once the card has the firmware loaded and has acquired - * the nodeid, if it is reset it will lose it all. - */ - cops_reset(dev,1); /* Need to reset card before load firmware. */ - cops_load(dev); /* Load the firmware. */ - - /* - * If atalkd already gave us a nodeid we will use that - * one again, else we wait for atalkd to give us a nodeid - * in cops_ioctl. This may cause a problem if someone steals - * our nodeid while we are resetting. - */ - if(lp->nodeid == 1) - cops_nodeid(dev,lp->node_acquire); - - return 0; -} - -static void tangent_wait_reset(int ioaddr) -{ - int timeout=0; - - while(timeout++ < 5 && (inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0) - mdelay(1); /* Wait 1 second */ -} - -/* - * Reset the LocalTalk board. - */ -static void cops_reset(struct net_device *dev, int sleep) -{ - struct cops_local *lp = netdev_priv(dev); - int ioaddr=dev->base_addr; - - if(lp->board==TANGENT) - { - inb(ioaddr); /* Clear request latch. */ - outb(0,ioaddr); /* Clear the TANG_TX_READY flop. */ - outb(0, ioaddr+TANG_RESET); /* Reset the adapter. */ - - tangent_wait_reset(ioaddr); - outb(0, ioaddr+TANG_CLEAR_INT); - } - if(lp->board==DAYNA) - { - outb(0, ioaddr+DAYNA_RESET); /* Assert the reset port */ - inb(ioaddr+DAYNA_RESET); /* Clear the reset */ - if (sleep) - msleep(333); - else - mdelay(333); - } - - netif_wake_queue(dev); -} - -static void cops_load (struct net_device *dev) -{ - struct ifreq ifr; - struct ltfirmware *ltf= (struct ltfirmware *)&ifr.ifr_ifru; - struct cops_local *lp = netdev_priv(dev); - int ioaddr=dev->base_addr; - int length, i = 0; - - strcpy(ifr.ifr_name,"lt0"); - - /* Get card's firmware code and do some checks on it. */ -#ifdef CONFIG_COPS_DAYNA - if(lp->board==DAYNA) - { - ltf->length=sizeof(ffdrv_code); - ltf->data=ffdrv_code; - } - else -#endif -#ifdef CONFIG_COPS_TANGENT - if(lp->board==TANGENT) - { - ltf->length=sizeof(ltdrv_code); - ltf->data=ltdrv_code; - } - else -#endif - { - printk(KERN_INFO "%s; unsupported board type.\n", dev->name); - return; - } - - /* Check to make sure firmware is correct length. */ - if(lp->board==DAYNA && ltf->length!=5983) - { - printk(KERN_WARNING "%s: Firmware is not length of FFDRV.BIN.\n", dev->name); - return; - } - if(lp->board==TANGENT && ltf->length!=2501) - { - printk(KERN_WARNING "%s: Firmware is not length of DRVCODE.BIN.\n", dev->name); - return; - } - - if(lp->board==DAYNA) - { - /* - * We must wait for a status response - * with the DAYNA board. - */ - while(++i<65536) - { - if((inb(ioaddr+DAYNA_CARD_STATUS)&3)==1) - break; - } - - if(i==65536) - return; - } - - /* - * Upload the firmware and kick. Byte-by-byte works nicely here. - */ - i=0; - length = ltf->length; - while(length--) - { - outb(ltf->data[i], ioaddr); - i++; - } - - if(cops_debug > 1) - printk("%s: Uploaded firmware - %d bytes of %d bytes.\n", - dev->name, i, ltf->length); - - if(lp->board==DAYNA) /* Tell Dayna to run the firmware code. */ - outb(1, ioaddr+DAYNA_INT_CARD); - else /* Tell Tang to run the firmware code. */ - inb(ioaddr); - - if(lp->board==TANGENT) - { - tangent_wait_reset(ioaddr); - inb(ioaddr); /* Clear initial ready signal. */ - } -} - -/* - * Get the LocalTalk Nodeid from the card. We can suggest - * any nodeid 1-254. The card will try and get that exact - * address else we can specify 0 as the nodeid and the card - * will autoprobe for a nodeid. - */ -static int cops_nodeid (struct net_device *dev, int nodeid) -{ - struct cops_local *lp = netdev_priv(dev); - int ioaddr = dev->base_addr; - - if(lp->board == DAYNA) - { - /* Empty any pending adapter responses. */ - while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0) - { - outb(0, ioaddr+COPS_CLEAR_INT); /* Clear interrupts. */ - if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_REQUEST) - cops_rx(dev); /* Kick any packets waiting. */ - schedule(); - } - - outb(2, ioaddr); /* Output command packet length as 2. */ - outb(0, ioaddr); - outb(LAP_INIT, ioaddr); /* Send LAP_INIT command byte. */ - outb(nodeid, ioaddr); /* Suggest node address. */ - } - - if(lp->board == TANGENT) - { - /* Empty any pending adapter responses. */ - while(inb(ioaddr+TANG_CARD_STATUS)&TANG_RX_READY) - { - outb(0, ioaddr+COPS_CLEAR_INT); /* Clear interrupt. */ - cops_rx(dev); /* Kick out packets waiting. */ - schedule(); - } - - /* Not sure what Tangent does if nodeid picked is used. */ - if(nodeid == 0) /* Seed. */ - nodeid = jiffies&0xFF; /* Get a random try */ - outb(2, ioaddr); /* Command length LSB */ - outb(0, ioaddr); /* Command length MSB */ - outb(LAP_INIT, ioaddr); /* Send LAP_INIT byte */ - outb(nodeid, ioaddr); /* LAP address hint. */ - outb(0xFF, ioaddr); /* Int. level to use */ - } - - lp->node_acquire=0; /* Set nodeid holder to 0. */ - while(lp->node_acquire==0) /* Get *True* nodeid finally. */ - { - outb(0, ioaddr+COPS_CLEAR_INT); /* Clear any interrupt. */ - - if(lp->board == DAYNA) - { - if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_REQUEST) - cops_rx(dev); /* Grab the nodeid put in lp->node_acquire. */ - } - if(lp->board == TANGENT) - { - if(inb(ioaddr+TANG_CARD_STATUS)&TANG_RX_READY) - cops_rx(dev); /* Grab the nodeid put in lp->node_acquire. */ - } - schedule(); - } - - if(cops_debug > 1) - printk(KERN_DEBUG "%s: Node ID %d has been acquired.\n", - dev->name, lp->node_acquire); - - lp->nodeid=1; /* Set got nodeid to 1. */ - - return 0; -} - -/* - * Poll the Tangent type cards to see if we have work. - */ - -static void cops_poll(struct timer_list *unused) -{ - int ioaddr, status; - int boguscount = 0; - struct net_device *dev = cops_timer_dev; - - del_timer(&cops_timer); - - if(dev == NULL) - return; /* We've been downed */ - - ioaddr = dev->base_addr; - do { - status=inb(ioaddr+TANG_CARD_STATUS); - if(status & TANG_RX_READY) - cops_rx(dev); - if(status & TANG_TX_READY) - netif_wake_queue(dev); - status = inb(ioaddr+TANG_CARD_STATUS); - } while((++boguscount < 20) && (status&(TANG_RX_READY|TANG_TX_READY))); - - /* poll 20 times per second */ - cops_timer.expires = jiffies + HZ/20; - add_timer(&cops_timer); -} - -/* - * The typical workload of the driver: - * Handle the network interface interrupts. - */ -static irqreturn_t cops_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct cops_local *lp; - int ioaddr, status; - int boguscount = 0; - - ioaddr = dev->base_addr; - lp = netdev_priv(dev); - - if(lp->board==DAYNA) - { - do { - outb(0, ioaddr + COPS_CLEAR_INT); - status=inb(ioaddr+DAYNA_CARD_STATUS); - if((status&0x03)==DAYNA_RX_REQUEST) - cops_rx(dev); - netif_wake_queue(dev); - } while(++boguscount < 20); - } - else - { - do { - status=inb(ioaddr+TANG_CARD_STATUS); - if(status & TANG_RX_READY) - cops_rx(dev); - if(status & TANG_TX_READY) - netif_wake_queue(dev); - status=inb(ioaddr+TANG_CARD_STATUS); - } while((++boguscount < 20) && (status&(TANG_RX_READY|TANG_TX_READY))); - } - - return IRQ_HANDLED; -} - -/* - * We have a good packet(s), get it/them out of the buffers. - */ -static void cops_rx(struct net_device *dev) -{ - int pkt_len = 0; - int rsp_type = 0; - struct sk_buff *skb = NULL; - struct cops_local *lp = netdev_priv(dev); - int ioaddr = dev->base_addr; - int boguscount = 0; - unsigned long flags; - - - spin_lock_irqsave(&lp->lock, flags); - - if(lp->board==DAYNA) - { - outb(0, ioaddr); /* Send out Zero length. */ - outb(0, ioaddr); - outb(DATA_READ, ioaddr); /* Send read command out. */ - - /* Wait for DMA to turn around. */ - while(++boguscount<1000000) - { - barrier(); - if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_READY) - break; - } - - if(boguscount==1000000) - { - printk(KERN_WARNING "%s: DMA timed out.\n",dev->name); - spin_unlock_irqrestore(&lp->lock, flags); - return; - } - } - - /* Get response length. */ - pkt_len = inb(ioaddr); - pkt_len |= (inb(ioaddr) << 8); - /* Input IO code. */ - rsp_type=inb(ioaddr); - - /* Malloc up new buffer. */ - skb = dev_alloc_skb(pkt_len); - if(skb == NULL) - { - printk(KERN_WARNING "%s: Memory squeeze, dropping packet.\n", - dev->name); - dev->stats.rx_dropped++; - while(pkt_len--) /* Discard packet */ - inb(ioaddr); - spin_unlock_irqrestore(&lp->lock, flags); - return; - } - skb->dev = dev; - skb_put(skb, pkt_len); - skb->protocol = htons(ETH_P_LOCALTALK); - - insb(ioaddr, skb->data, pkt_len); /* Eat the Data */ - - if(lp->board==DAYNA) - outb(1, ioaddr+DAYNA_INT_CARD); /* Interrupt the card */ - - spin_unlock_irqrestore(&lp->lock, flags); /* Restore interrupts. */ - - /* Check for bad response length */ - if(pkt_len < 0 || pkt_len > MAX_LLAP_SIZE) - { - printk(KERN_WARNING "%s: Bad packet length of %d bytes.\n", - dev->name, pkt_len); - dev->stats.tx_errors++; - dev_kfree_skb_any(skb); - return; - } - - /* Set nodeid and then get out. */ - if(rsp_type == LAP_INIT_RSP) - { /* Nodeid taken from received packet. */ - lp->node_acquire = skb->data[0]; - dev_kfree_skb_any(skb); - return; - } - - /* One last check to make sure we have a good packet. */ - if(rsp_type != LAP_RESPONSE) - { - printk(KERN_WARNING "%s: Bad packet type %d.\n", dev->name, rsp_type); - dev->stats.tx_errors++; - dev_kfree_skb_any(skb); - return; - } - - skb_reset_mac_header(skb); /* Point to entire packet. */ - skb_pull(skb,3); - skb_reset_transport_header(skb); /* Point to data (Skip header). */ - - /* Update the counters. */ - dev->stats.rx_packets++; - dev->stats.rx_bytes += skb->len; - - /* Send packet to a higher place. */ - netif_rx(skb); -} - -static void cops_timeout(struct net_device *dev, unsigned int txqueue) -{ - struct cops_local *lp = netdev_priv(dev); - int ioaddr = dev->base_addr; - - dev->stats.tx_errors++; - if(lp->board==TANGENT) - { - if((inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0) - printk(KERN_WARNING "%s: No TX complete interrupt.\n", dev->name); - } - printk(KERN_WARNING "%s: Transmit timed out.\n", dev->name); - cops_jumpstart(dev); /* Restart the card. */ - netif_trans_update(dev); /* prevent tx timeout */ - netif_wake_queue(dev); -} - - -/* - * Make the card transmit a LocalTalk packet. - */ - -static netdev_tx_t cops_send_packet(struct sk_buff *skb, - struct net_device *dev) -{ - struct cops_local *lp = netdev_priv(dev); - int ioaddr = dev->base_addr; - unsigned long flags; - - /* - * Block a timer-based transmit from overlapping. - */ - - netif_stop_queue(dev); - - spin_lock_irqsave(&lp->lock, flags); - if(lp->board == DAYNA) /* Wait for adapter transmit buffer. */ - while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0) - cpu_relax(); - if(lp->board == TANGENT) /* Wait for adapter transmit buffer. */ - while((inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0) - cpu_relax(); - - /* Output IO length. */ - outb(skb->len, ioaddr); - outb(skb->len >> 8, ioaddr); - - /* Output IO code. */ - outb(LAP_WRITE, ioaddr); - - if(lp->board == DAYNA) /* Check the transmit buffer again. */ - while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0); - - outsb(ioaddr, skb->data, skb->len); /* Send out the data. */ - - if(lp->board==DAYNA) /* Dayna requires you kick the card */ - outb(1, ioaddr+DAYNA_INT_CARD); - - spin_unlock_irqrestore(&lp->lock, flags); /* Restore interrupts. */ - - /* Done sending packet, update counters and cleanup. */ - dev->stats.tx_packets++; - dev->stats.tx_bytes += skb->len; - dev_kfree_skb (skb); - return NETDEV_TX_OK; -} - -/* - * Dummy function to keep the Appletalk layer happy. - */ - -static void set_multicast_list(struct net_device *dev) -{ - if(cops_debug >= 3) - printk("%s: set_multicast_list executed\n", dev->name); -} - -/* - * System ioctls for the COPS LocalTalk card. - */ - -static int cops_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -{ - struct cops_local *lp = netdev_priv(dev); - struct sockaddr_at *sa = (struct sockaddr_at *)&ifr->ifr_addr; - struct atalk_addr *aa = &lp->node_addr; - - switch(cmd) - { - case SIOCSIFADDR: - /* Get and set the nodeid and network # atalkd wants. */ - cops_nodeid(dev, sa->sat_addr.s_node); - aa->s_net = sa->sat_addr.s_net; - aa->s_node = lp->node_acquire; - - /* Set broardcast address. */ - dev->broadcast[0] = 0xFF; - - /* Set hardware address. */ - dev->dev_addr[0] = aa->s_node; - dev->addr_len = 1; - return 0; - - case SIOCGIFADDR: - sa->sat_addr.s_net = aa->s_net; - sa->sat_addr.s_node = aa->s_node; - return 0; - - default: - return -EOPNOTSUPP; - } -} - -/* - * The inverse routine to cops_open(). - */ - -static int cops_close(struct net_device *dev) -{ - struct cops_local *lp = netdev_priv(dev); - - /* If we were running polled, yank the timer. - */ - if(lp->board==TANGENT && dev->irq==0) - del_timer(&cops_timer); - - netif_stop_queue(dev); - return 0; -} - - -#ifdef MODULE -static struct net_device *cops_dev; - -MODULE_LICENSE("GPL"); -module_param_hw(io, int, ioport, 0); -module_param_hw(irq, int, irq, 0); -module_param_hw(board_type, int, other, 0); - -static int __init cops_module_init(void) -{ - if (io == 0) - printk(KERN_WARNING "%s: You shouldn't autoprobe with insmod\n", - cardname); - cops_dev = cops_probe(-1); - return PTR_ERR_OR_ZERO(cops_dev); -} - -static void __exit cops_module_exit(void) -{ - unregister_netdev(cops_dev); - cleanup_card(cops_dev); - free_netdev(cops_dev); -} -module_init(cops_module_init); -module_exit(cops_module_exit); -#endif /* MODULE */ diff --git a/drivers/net/appletalk/cops.h b/drivers/net/appletalk/cops.h deleted file mode 100644 index 7a0bfb351929..000000000000 --- a/drivers/net/appletalk/cops.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* cops.h: LocalTalk driver for Linux. - * - * Authors: - * - Jay Schulist <jschlst@samba.org> - */ - -#ifndef __LINUX_COPSLTALK_H -#define __LINUX_COPSLTALK_H - -#ifdef __KERNEL__ - -/* Max LLAP size we will accept. */ -#define MAX_LLAP_SIZE 603 - -/* Tangent */ -#define TANG_CARD_STATUS 1 -#define TANG_CLEAR_INT 1 -#define TANG_RESET 3 - -#define TANG_TX_READY 1 -#define TANG_RX_READY 2 - -/* Dayna */ -#define DAYNA_CMD_DATA 0 -#define DAYNA_CLEAR_INT 1 -#define DAYNA_CARD_STATUS 2 -#define DAYNA_INT_CARD 3 -#define DAYNA_RESET 4 - -#define DAYNA_RX_READY 0 -#define DAYNA_TX_READY 1 -#define DAYNA_RX_REQUEST 3 - -/* Same on both card types */ -#define COPS_CLEAR_INT 1 - -/* LAP response codes received from the cards. */ -#define LAP_INIT 1 /* Init cmd */ -#define LAP_INIT_RSP 2 /* Init response */ -#define LAP_WRITE 3 /* Write cmd */ -#define DATA_READ 4 /* Data read */ -#define LAP_RESPONSE 4 /* Received ALAP frame response */ -#define LAP_GETSTAT 5 /* Get LAP and HW status */ -#define LAP_RSPSTAT 6 /* Status response */ - -#endif - -/* - * Structure to hold the firmware information. - */ -struct ltfirmware -{ - unsigned int length; - const unsigned char *data; -}; - -#define DAYNA 1 -#define TANGENT 2 - -#endif diff --git a/drivers/net/appletalk/cops_ffdrv.h b/drivers/net/appletalk/cops_ffdrv.h deleted file mode 100644 index b02005087c1b..000000000000 --- a/drivers/net/appletalk/cops_ffdrv.h +++ /dev/null @@ -1,532 +0,0 @@ - -/* - * The firmware this driver downloads into the Localtalk card is a - * separate program and is not GPL'd source code, even though the Linux - * side driver and the routine that loads this data into the card are. - * - * It is taken from the COPS SDK and is under the following license - * - * This material is licensed to you strictly for use in conjunction with - * the use of COPS LocalTalk adapters. - * There is no charge for this SDK. And no waranty express or implied - * about its fitness for any purpose. However, we will cheerefully - * refund every penny you paid for this SDK... - * Regards, - * - * Thomas F. Divine - * Chief Scientist - */ - - -/* cops_ffdrv.h: LocalTalk driver firmware dump for Linux. - * - * Authors: - * - Jay Schulist <jschlst@samba.org> - */ - - -#ifdef CONFIG_COPS_DAYNA - -static const unsigned char ffdrv_code[] = { - 58,3,0,50,228,149,33,255,255,34,226,149, - 249,17,40,152,33,202,154,183,237,82,77,68, - 11,107,98,19,54,0,237,176,175,50,80,0, - 62,128,237,71,62,32,237,57,51,62,12,237, - 57,50,237,57,54,62,6,237,57,52,62,12, - 237,57,49,33,107,137,34,32,128,33,83,130, - 34,40,128,33,86,130,34,42,128,33,112,130, - 34,36,128,33,211,130,34,38,128,62,0,237, - 57,16,33,63,148,34,34,128,237,94,205,15, - 130,251,205,168,145,24,141,67,111,112,121,114, - 105,103,104,116,32,40,67,41,32,49,57,56, - 56,32,45,32,68,97,121,110,97,32,67,111, - 109,109,117,110,105,99,97,116,105,111,110,115, - 32,32,32,65,108,108,32,114,105,103,104,116, - 115,32,114,101,115,101,114,118,101,100,46,32, - 32,40,68,40,68,7,16,8,34,7,22,6, - 16,5,12,4,8,3,6,140,0,16,39,128, - 0,4,96,10,224,6,0,7,126,2,64,11, - 118,12,6,13,0,14,193,15,0,5,96,3, - 192,1,64,9,8,62,9,211,66,62,192,211, - 66,62,100,61,32,253,6,28,33,205,129,14, - 66,237,163,194,253,129,6,28,33,205,129,14, - 64,237,163,194,9,130,201,62,47,50,71,152, - 62,47,211,68,58,203,129,237,57,20,58,204, - 129,237,57,21,33,77,152,54,132,205,233,129, - 58,228,149,254,209,40,6,56,4,62,0,24, - 2,219,96,33,233,149,119,230,62,33,232,149, - 119,213,33,8,152,17,7,0,25,119,19,25, - 119,209,201,251,237,77,245,197,213,229,221,229, - 205,233,129,62,1,50,106,137,205,158,139,221, - 225,225,209,193,241,251,237,77,245,197,213,219, - 72,237,56,16,230,46,237,57,16,237,56,12, - 58,72,152,183,32,26,6,20,17,128,2,237, - 56,46,187,32,35,237,56,47,186,32,29,219, - 72,230,1,32,3,5,32,232,175,50,72,152, - 229,221,229,62,1,50,106,137,205,158,139,221, - 225,225,24,25,62,1,50,72,152,58,201,129, - 237,57,12,58,202,129,237,57,13,237,56,16, - 246,17,237,57,16,209,193,241,251,237,77,245, - 197,229,213,221,229,237,56,16,230,17,237,57, - 16,237,56,20,58,34,152,246,16,246,8,211, - 68,62,6,61,32,253,58,34,152,246,8,211, - 68,58,203,129,237,57,20,58,204,129,237,57, - 21,237,56,16,246,34,237,57,16,221,225,209, - 225,193,241,251,237,77,33,2,0,57,126,230, - 3,237,100,1,40,2,246,128,230,130,245,62, - 5,211,64,241,211,64,201,229,213,243,237,56, - 16,230,46,237,57,16,237,56,12,251,70,35, - 35,126,254,175,202,77,133,254,129,202,15,133, - 230,128,194,191,132,43,58,44,152,119,33,76, - 152,119,35,62,132,119,120,254,255,40,4,58, - 49,152,119,219,72,43,43,112,17,3,0,237, - 56,52,230,248,237,57,52,219,72,230,1,194, - 141,131,209,225,237,56,52,246,6,237,57,52, - 62,1,55,251,201,62,3,211,66,62,192,211, - 66,62,48,211,66,0,0,219,66,230,1,40, - 4,219,67,24,240,205,203,135,58,75,152,254, - 255,202,128,132,58,49,152,254,161,250,207,131, - 58,34,152,211,68,62,10,211,66,62,128,211, - 66,62,11,211,66,62,6,211,66,24,0,62, - 14,211,66,62,33,211,66,62,1,211,66,62, - 64,211,66,62,3,211,66,62,209,211,66,62, - 100,71,219,66,230,1,32,6,5,32,247,195, - 248,132,219,67,71,58,44,152,184,194,248,132, - 62,100,71,219,66,230,1,32,6,5,32,247, - 195,248,132,219,67,62,100,71,219,66,230,1, - 32,6,5,32,247,195,248,132,219,67,254,133, - 32,7,62,0,50,74,152,24,17,254,173,32, - 7,62,1,50,74,152,24,6,254,141,194,248, - 132,71,209,225,58,49,152,254,132,32,10,62, - 50,205,2,134,205,144,135,24,27,254,140,32, - 15,62,110,205,2,134,62,141,184,32,5,205, - 144,135,24,8,62,10,205,2,134,205,8,134, - 62,1,50,106,137,205,158,139,237,56,52,246, - 6,237,57,52,175,183,251,201,62,20,135,237, - 57,20,175,237,57,21,237,56,16,246,2,237, - 57,16,237,56,20,95,237,56,21,123,254,10, - 48,244,237,56,16,230,17,237,57,16,209,225, - 205,144,135,62,1,50,106,137,205,158,139,237, - 56,52,246,6,237,57,52,175,183,251,201,209, - 225,243,219,72,230,1,40,13,62,10,211,66, - 0,0,219,66,230,192,202,226,132,237,56,52, - 246,6,237,57,52,62,1,55,251,201,205,203, - 135,62,1,50,106,137,205,158,139,237,56,52, - 246,6,237,57,52,183,251,201,209,225,62,1, - 50,106,137,205,158,139,237,56,52,246,6,237, - 57,52,62,2,55,251,201,209,225,243,219,72, - 230,1,202,213,132,62,10,211,66,0,0,219, - 66,230,192,194,213,132,229,62,1,50,106,137, - 42,40,152,205,65,143,225,17,3,0,205,111, - 136,62,6,211,66,58,44,152,211,66,237,56, - 52,246,6,237,57,52,183,251,201,209,197,237, - 56,52,230,248,237,57,52,219,72,230,1,32, - 15,193,225,237,56,52,246,6,237,57,52,62, - 1,55,251,201,14,23,58,37,152,254,0,40, - 14,14,2,254,1,32,5,62,140,119,24,3, - 62,132,119,43,43,197,205,203,135,193,62,1, - 211,66,62,64,211,66,62,3,211,66,62,193, - 211,66,62,100,203,39,71,219,66,230,1,32, - 6,5,32,247,195,229,133,33,238,151,219,67, - 71,58,44,152,184,194,229,133,119,62,100,71, - 219,66,230,1,32,6,5,32,247,195,229,133, - 219,67,35,119,13,32,234,193,225,62,1,50, - 106,137,205,158,139,237,56,52,246,6,237,57, - 52,175,183,251,201,33,234,151,35,35,62,255, - 119,193,225,62,1,50,106,137,205,158,139,237, - 56,52,246,6,237,57,52,175,251,201,243,61, - 32,253,251,201,62,3,211,66,62,192,211,66, - 58,49,152,254,140,32,19,197,229,213,17,181, - 129,33,185,129,1,2,0,237,176,209,225,193, - 24,27,229,213,33,187,129,58,49,152,230,15, - 87,30,2,237,92,25,17,181,129,126,18,19, - 35,126,18,209,225,58,34,152,246,8,211,68, - 58,49,152,254,165,40,14,254,164,40,10,62, - 10,211,66,62,224,211,66,24,25,58,74,152, - 254,0,40,10,62,10,211,66,62,160,211,66, - 24,8,62,10,211,66,62,128,211,66,62,11, - 211,66,62,6,211,66,205,147,143,62,5,211, - 66,62,224,211,66,62,5,211,66,62,96,211, - 66,62,5,61,32,253,62,5,211,66,62,224, - 211,66,62,14,61,32,253,62,5,211,66,62, - 233,211,66,62,128,211,66,58,181,129,61,32, - 253,62,1,211,66,62,192,211,66,1,254,19, - 237,56,46,187,32,6,13,32,247,195,226,134, - 62,192,211,66,0,0,219,66,203,119,40,250, - 219,66,203,87,40,250,243,237,56,16,230,17, - 237,57,16,237,56,20,251,62,5,211,66,62, - 224,211,66,58,182,129,61,32,253,229,33,181, - 129,58,183,129,203,63,119,35,58,184,129,119, - 225,62,10,211,66,62,224,211,66,62,11,211, - 66,62,118,211,66,62,47,211,68,62,5,211, - 66,62,233,211,66,58,181,129,61,32,253,62, - 5,211,66,62,224,211,66,58,182,129,61,32, - 253,62,5,211,66,62,96,211,66,201,229,213, - 58,50,152,230,15,87,30,2,237,92,33,187, - 129,25,17,181,129,126,18,35,19,126,18,209, - 225,58,71,152,246,8,211,68,58,50,152,254, - 165,40,14,254,164,40,10,62,10,211,66,62, - 224,211,66,24,8,62,10,211,66,62,128,211, - 66,62,11,211,66,62,6,211,66,195,248,135, - 62,3,211,66,62,192,211,66,197,229,213,17, - 181,129,33,183,129,1,2,0,237,176,209,225, - 193,62,47,211,68,62,10,211,66,62,224,211, - 66,62,11,211,66,62,118,211,66,62,1,211, - 66,62,0,211,66,205,147,143,195,16,136,62, - 3,211,66,62,192,211,66,197,229,213,17,181, - 129,33,183,129,1,2,0,237,176,209,225,193, - 62,47,211,68,62,10,211,66,62,224,211,66, - 62,11,211,66,62,118,211,66,205,147,143,62, - 5,211,66,62,224,211,66,62,5,211,66,62, - 96,211,66,62,5,61,32,253,62,5,211,66, - 62,224,211,66,62,14,61,32,253,62,5,211, - 66,62,233,211,66,62,128,211,66,58,181,129, - 61,32,253,62,1,211,66,62,192,211,66,1, - 254,19,237,56,46,187,32,6,13,32,247,195, - 88,136,62,192,211,66,0,0,219,66,203,119, - 40,250,219,66,203,87,40,250,62,5,211,66, - 62,224,211,66,58,182,129,61,32,253,62,5, - 211,66,62,96,211,66,201,197,14,67,6,0, - 62,3,211,66,62,192,211,66,62,48,211,66, - 0,0,219,66,230,1,40,4,219,67,24,240, - 62,5,211,66,62,233,211,66,62,128,211,66, - 58,181,129,61,32,253,237,163,29,62,192,211, - 66,219,66,230,4,40,250,237,163,29,32,245, - 219,66,230,4,40,250,62,255,71,219,66,230, - 4,40,3,5,32,247,219,66,230,4,40,250, - 62,5,211,66,62,224,211,66,58,182,129,61, - 32,253,62,5,211,66,62,96,211,66,58,71, - 152,254,1,202,18,137,62,16,211,66,62,56, - 211,66,62,14,211,66,62,33,211,66,62,1, - 211,66,62,248,211,66,237,56,48,246,153,230, - 207,237,57,48,62,3,211,66,62,221,211,66, - 193,201,58,71,152,211,68,62,10,211,66,62, - 128,211,66,62,11,211,66,62,6,211,66,62, - 6,211,66,58,44,152,211,66,62,16,211,66, - 62,56,211,66,62,48,211,66,0,0,62,14, - 211,66,62,33,211,66,62,1,211,66,62,248, - 211,66,237,56,48,246,145,246,8,230,207,237, - 57,48,62,3,211,66,62,221,211,66,193,201, - 44,3,1,0,70,69,1,245,197,213,229,175, - 50,72,152,237,56,16,230,46,237,57,16,237, - 56,12,62,1,211,66,0,0,219,66,95,230, - 160,32,3,195,20,139,123,230,96,194,72,139, - 62,48,211,66,62,1,211,66,62,64,211,66, - 237,91,40,152,205,207,143,25,43,55,237,82, - 218,70,139,34,42,152,98,107,58,44,152,190, - 194,210,138,35,35,62,130,190,194,200,137,62, - 1,50,48,152,62,175,190,202,82,139,62,132, - 190,32,44,50,50,152,62,47,50,71,152,229, - 175,50,106,137,42,40,152,205,65,143,225,54, - 133,43,70,58,44,152,119,43,112,17,3,0, - 62,10,205,2,134,205,111,136,195,158,138,62, - 140,190,32,19,50,50,152,58,233,149,230,4, - 202,222,138,62,1,50,71,152,195,219,137,126, - 254,160,250,185,138,254,166,242,185,138,50,50, - 152,43,126,35,229,213,33,234,149,95,22,0, - 25,126,254,132,40,18,254,140,40,14,58,50, - 152,230,15,87,126,31,21,242,65,138,56,2, - 175,119,58,50,152,230,15,87,58,233,149,230, - 62,31,21,242,85,138,218,98,138,209,225,195, - 20,139,58,50,152,33,100,137,230,15,95,22, - 0,25,126,50,71,152,209,225,58,50,152,254, - 164,250,135,138,58,73,152,254,0,40,4,54, - 173,24,2,54,133,43,70,58,44,152,119,43, - 112,17,3,0,205,70,135,175,50,106,137,205, - 208,139,58,199,129,237,57,12,58,200,129,237, - 57,13,237,56,16,246,17,237,57,16,225,209, - 193,241,251,237,77,62,129,190,194,227,138,54, - 130,43,70,58,44,152,119,43,112,17,3,0, - 205,144,135,195,20,139,35,35,126,254,132,194, - 227,138,175,50,106,137,205,158,139,24,42,58, - 201,154,254,1,40,7,62,1,50,106,137,24, - 237,58,106,137,254,1,202,222,138,62,128,166, - 194,222,138,221,229,221,33,67,152,205,127,142, - 205,109,144,221,225,225,209,193,241,251,237,77, - 58,106,137,254,1,202,44,139,58,50,152,254, - 164,250,44,139,58,73,152,238,1,50,73,152, - 221,229,221,33,51,152,205,127,142,221,225,62, - 1,50,106,137,205,158,139,195,13,139,24,208, - 24,206,24,204,230,64,40,3,195,20,139,195, - 20,139,43,126,33,8,152,119,35,58,44,152, - 119,43,237,91,35,152,205,203,135,205,158,139, - 195,13,139,175,50,78,152,62,3,211,66,62, - 192,211,66,201,197,33,4,0,57,126,35,102, - 111,62,1,50,106,137,219,72,205,141,139,193, - 201,62,1,50,78,152,34,40,152,54,0,35, - 35,54,0,195,163,139,58,78,152,183,200,229, - 33,181,129,58,183,129,119,35,58,184,129,119, - 225,62,47,211,68,62,14,211,66,62,193,211, - 66,62,10,211,66,62,224,211,66,62,11,211, - 66,62,118,211,66,195,3,140,58,78,152,183, - 200,58,71,152,211,68,254,69,40,4,254,70, - 32,17,58,73,152,254,0,40,10,62,10,211, - 66,62,160,211,66,24,8,62,10,211,66,62, - 128,211,66,62,11,211,66,62,6,211,66,62, - 6,211,66,58,44,152,211,66,62,16,211,66, - 62,56,211,66,62,48,211,66,0,0,219,66, - 230,1,40,4,219,67,24,240,62,14,211,66, - 62,33,211,66,42,40,152,205,65,143,62,1, - 211,66,62,248,211,66,237,56,48,246,145,246, - 8,230,207,237,57,48,62,3,211,66,62,221, - 211,66,201,62,16,211,66,62,56,211,66,62, - 48,211,66,0,0,219,66,230,1,40,4,219, - 67,24,240,62,14,211,66,62,33,211,66,62, - 1,211,66,62,248,211,66,237,56,48,246,153, - 230,207,237,57,48,62,3,211,66,62,221,211, - 66,201,229,213,33,234,149,95,22,0,25,126, - 254,132,40,4,254,140,32,2,175,119,123,209, - 225,201,6,8,14,0,31,48,1,12,16,250, - 121,201,33,4,0,57,94,35,86,33,2,0, - 57,126,35,102,111,221,229,34,89,152,237,83, - 91,152,221,33,63,152,205,127,142,58,81,152, - 50,82,152,58,80,152,135,50,80,152,205,162, - 140,254,3,56,16,58,81,152,135,60,230,15, - 50,81,152,175,50,80,152,24,23,58,79,152, - 205,162,140,254,3,48,13,58,81,152,203,63, - 50,81,152,62,255,50,79,152,58,81,152,50, - 82,152,58,79,152,135,50,79,152,62,32,50, - 83,152,50,84,152,237,56,16,230,17,237,57, - 16,219,72,62,192,50,93,152,62,93,50,94, - 152,58,93,152,61,50,93,152,32,9,58,94, - 152,61,50,94,152,40,44,62,170,237,57,20, - 175,237,57,21,237,56,16,246,2,237,57,16, - 219,72,230,1,202,29,141,237,56,20,71,237, - 56,21,120,254,10,48,237,237,56,16,230,17, - 237,57,16,243,62,14,211,66,62,65,211,66, - 251,58,39,152,23,23,60,50,39,152,71,58, - 82,152,160,230,15,40,22,71,14,10,219,66, - 230,16,202,186,141,219,72,230,1,202,186,141, - 13,32,239,16,235,42,89,152,237,91,91,152, - 205,47,131,48,7,61,202,186,141,195,227,141, - 221,225,33,0,0,201,221,33,55,152,205,127, - 142,58,84,152,61,50,84,152,40,19,58,82, - 152,246,1,50,82,152,58,79,152,246,1,50, - 79,152,195,29,141,221,225,33,1,0,201,221, - 33,59,152,205,127,142,58,80,152,246,1,50, - 80,152,58,82,152,135,246,1,50,82,152,58, - 83,152,61,50,83,152,194,29,141,221,225,33, - 2,0,201,221,229,33,0,0,57,17,4,0, - 25,126,50,44,152,230,128,50,85,152,58,85, - 152,183,40,6,221,33,88,2,24,4,221,33, - 150,0,58,44,152,183,40,53,60,40,50,60, - 40,47,61,61,33,86,152,119,35,119,35,54, - 129,175,50,48,152,221,43,221,229,225,124,181, - 40,42,33,86,152,17,3,0,205,189,140,17, - 232,3,27,123,178,32,251,58,48,152,183,40, - 224,58,44,152,71,62,7,128,230,127,71,58, - 85,152,176,50,44,152,24,162,221,225,201,183, - 221,52,0,192,221,52,1,192,221,52,2,192, - 221,52,3,192,55,201,245,62,1,211,100,241, - 201,245,62,1,211,96,241,201,33,2,0,57, - 126,35,102,111,237,56,48,230,175,237,57,48, - 62,48,237,57,49,125,237,57,32,124,237,57, - 33,62,0,237,57,34,62,88,237,57,35,62, - 0,237,57,36,237,57,37,33,128,2,125,237, - 57,38,124,237,57,39,237,56,48,246,97,230, - 207,237,57,48,62,0,237,57,0,62,0,211, - 96,211,100,201,33,2,0,57,126,35,102,111, - 237,56,48,230,175,237,57,48,62,12,237,57, - 49,62,76,237,57,32,62,0,237,57,33,237, - 57,34,125,237,57,35,124,237,57,36,62,0, - 237,57,37,33,128,2,125,237,57,38,124,237, - 57,39,237,56,48,246,97,230,207,237,57,48, - 62,1,211,96,201,33,2,0,57,126,35,102, - 111,229,237,56,48,230,87,237,57,48,125,237, - 57,40,124,237,57,41,62,0,237,57,42,62, - 67,237,57,43,62,0,237,57,44,58,106,137, - 254,1,32,5,33,6,0,24,3,33,128,2, - 125,237,57,46,124,237,57,47,237,56,50,230, - 252,246,2,237,57,50,225,201,33,4,0,57, - 94,35,86,33,2,0,57,126,35,102,111,237, - 56,48,230,87,237,57,48,125,237,57,40,124, - 237,57,41,62,0,237,57,42,62,67,237,57, - 43,62,0,237,57,44,123,237,57,46,122,237, - 57,47,237,56,50,230,244,246,0,237,57,50, - 237,56,48,246,145,230,207,237,57,48,201,213, - 237,56,46,95,237,56,47,87,237,56,46,111, - 237,56,47,103,183,237,82,32,235,33,128,2, - 183,237,82,209,201,213,237,56,38,95,237,56, - 39,87,237,56,38,111,237,56,39,103,183,237, - 82,32,235,33,128,2,183,237,82,209,201,245, - 197,1,52,0,237,120,230,253,237,121,193,241, - 201,245,197,1,52,0,237,120,246,2,237,121, - 193,241,201,33,2,0,57,126,35,102,111,126, - 35,110,103,201,33,0,0,34,102,152,34,96, - 152,34,98,152,33,202,154,34,104,152,237,91, - 104,152,42,226,149,183,237,82,17,0,255,25, - 34,100,152,203,124,40,6,33,0,125,34,100, - 152,42,104,152,35,35,35,229,205,120,139,193, - 201,205,186,149,229,42,40,152,35,35,35,229, - 205,39,144,193,124,230,3,103,221,117,254,221, - 116,255,237,91,42,152,35,35,35,183,237,82, - 32,12,17,5,0,42,42,152,205,171,149,242, - 169,144,42,40,152,229,205,120,139,193,195,198, - 149,237,91,42,152,42,98,152,25,34,98,152, - 19,19,19,42,102,152,25,34,102,152,237,91, - 100,152,33,158,253,25,237,91,102,152,205,171, - 149,242,214,144,33,0,0,34,102,152,62,1, - 50,95,152,205,225,144,195,198,149,58,95,152, - 183,200,237,91,96,152,42,102,152,205,171,149, - 242,5,145,237,91,102,152,33,98,2,25,237, - 91,96,152,205,171,149,250,37,145,237,91,96, - 152,42,102,152,183,237,82,32,7,42,98,152, - 125,180,40,13,237,91,102,152,42,96,152,205, - 171,149,242,58,145,237,91,104,152,42,102,152, - 25,35,35,35,229,205,120,139,193,175,50,95, - 152,201,195,107,139,205,206,149,250,255,243,205, - 225,144,251,58,230,149,183,194,198,149,17,1, - 0,42,98,152,205,171,149,250,198,149,62,1, - 50,230,149,237,91,96,152,42,104,152,25,221, - 117,252,221,116,253,237,91,104,152,42,96,152, - 25,35,35,35,221,117,254,221,116,255,35,35, - 35,229,205,39,144,124,230,3,103,35,35,35, - 221,117,250,221,116,251,235,221,110,252,221,102, - 253,115,35,114,35,54,4,62,1,211,100,211, - 84,195,198,149,33,0,0,34,102,152,34,96, - 152,34,98,152,33,202,154,34,104,152,237,91, - 104,152,42,226,149,183,237,82,17,0,255,25, - 34,100,152,33,109,152,54,0,33,107,152,229, - 205,240,142,193,62,47,50,34,152,62,132,50, - 49,152,205,241,145,205,61,145,58,39,152,60, - 50,39,152,24,241,205,206,149,251,255,33,109, - 152,126,183,202,198,149,110,221,117,251,33,109, - 152,54,0,221,126,251,254,1,40,28,254,3, - 40,101,254,4,202,190,147,254,5,202,147,147, - 254,8,40,87,33,107,152,229,205,240,142,195, - 198,149,58,201,154,183,32,21,33,111,152,126, - 50,229,149,205,52,144,33,110,152,110,38,0, - 229,205,11,142,193,237,91,96,152,42,104,152, - 25,221,117,254,221,116,255,35,35,54,2,17, - 2,0,43,43,115,35,114,58,44,152,35,35, - 119,58,228,149,35,119,62,1,211,100,211,84, - 62,1,50,201,154,24,169,205,153,142,58,231, - 149,183,40,250,175,50,231,149,33,110,152,126, - 254,255,40,91,58,233,149,230,63,183,40,83, - 94,22,0,33,234,149,25,126,183,40,13,33, - 110,152,94,33,234,150,25,126,254,3,32,36, - 205,81,148,125,180,33,110,152,94,22,0,40, - 17,33,234,149,25,54,0,33,107,152,229,205, - 240,142,193,195,198,149,33,234,150,25,54,0, - 33,110,152,94,22,0,33,234,149,25,126,50, - 49,152,254,132,32,37,62,47,50,34,152,42, - 107,152,229,33,110,152,229,205,174,140,193,193, - 125,180,33,110,152,94,22,0,33,234,150,202, - 117,147,25,52,195,120,147,58,49,152,254,140, - 32,7,62,1,50,34,152,24,210,62,32,50, - 106,152,24,19,58,49,152,95,58,106,152,163, - 183,58,106,152,32,11,203,63,50,106,152,58, - 106,152,183,32,231,254,2,40,51,254,4,40, - 38,254,8,40,26,254,16,40,13,254,32,32, - 158,62,165,50,49,152,62,69,24,190,62,164, - 50,49,152,62,70,24,181,62,163,50,49,152, - 175,24,173,62,162,50,49,152,62,1,24,164, - 62,161,50,49,152,62,3,24,155,25,54,0, - 221,126,251,254,8,40,7,58,230,149,183,202, - 32,146,33,107,152,229,205,240,142,193,211,84, - 195,198,149,237,91,96,152,42,104,152,25,221, - 117,254,221,116,255,35,35,54,6,17,2,0, - 43,43,115,35,114,58,228,149,35,35,119,58, - 233,149,35,119,205,146,142,195,32,146,237,91, - 96,152,42,104,152,25,229,205,160,142,193,58, - 231,149,183,40,250,175,50,231,149,243,237,91, - 96,152,42,104,152,25,221,117,254,221,116,255, - 78,35,70,221,113,252,221,112,253,89,80,42, - 98,152,183,237,82,34,98,152,203,124,40,19, - 33,0,0,34,98,152,34,102,152,34,96,152, - 62,1,50,95,152,24,40,221,94,252,221,86, - 253,19,19,19,42,96,152,25,34,96,152,237, - 91,100,152,33,158,253,25,237,91,96,152,205, - 171,149,242,55,148,33,0,0,34,96,152,175, - 50,230,149,251,195,32,146,245,62,1,50,231, - 149,62,16,237,57,0,211,80,241,251,237,77, - 201,205,186,149,229,229,33,0,0,34,37,152, - 33,110,152,126,50,234,151,58,44,152,33,235, - 151,119,221,54,253,0,221,54,254,0,195,230, - 148,33,236,151,54,175,33,3,0,229,33,234, - 151,229,205,174,140,193,193,33,236,151,126,254, - 255,40,74,33,245,151,110,221,117,255,33,249, - 151,126,221,166,255,221,119,255,33,253,151,126, - 221,166,255,221,119,255,58,232,149,95,221,126, - 255,163,221,119,255,183,40,15,230,191,33,110, - 152,94,22,0,33,234,149,25,119,24,12,33, - 110,152,94,22,0,33,234,149,25,54,132,33, - 0,0,195,198,149,221,110,253,221,102,254,35, - 221,117,253,221,116,254,17,32,0,221,110,253, - 221,102,254,205,171,149,250,117,148,58,233,149, - 203,87,40,84,33,1,0,34,37,152,221,54, - 253,0,221,54,254,0,24,53,33,236,151,54, - 175,33,3,0,229,33,234,151,229,205,174,140, - 193,193,33,236,151,126,254,255,40,14,33,110, - 152,94,22,0,33,234,149,25,54,140,24,159, - 221,110,253,221,102,254,35,221,117,253,221,116, - 254,17,32,0,221,110,253,221,102,254,205,171, - 149,250,12,149,33,2,0,34,37,152,221,54, - 253,0,221,54,254,0,24,54,33,236,151,54, - 175,33,3,0,229,33,234,151,229,205,174,140, - 193,193,33,236,151,126,254,255,40,15,33,110, - 152,94,22,0,33,234,149,25,54,132,195,211, - 148,221,110,253,221,102,254,35,221,117,253,221, - 116,254,17,32,0,221,110,253,221,102,254,205, - 171,149,250,96,149,33,1,0,195,198,149,124, - 170,250,179,149,237,82,201,124,230,128,237,82, - 60,201,225,253,229,221,229,221,33,0,0,221, - 57,233,221,249,221,225,253,225,201,233,225,253, - 229,221,229,221,33,0,0,221,57,94,35,86, - 35,235,57,249,235,233,0,0,0,0,0,0, - 62,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 175,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,133,1,0,0,0,63, - 255,255,255,255,0,0,0,63,0,0,0,0, - 0,0,0,0,0,0,0,24,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0 - } ; - -#endif diff --git a/drivers/net/appletalk/cops_ltdrv.h b/drivers/net/appletalk/cops_ltdrv.h deleted file mode 100644 index c699b1ad31da..000000000000 --- a/drivers/net/appletalk/cops_ltdrv.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * The firmware this driver downloads into the Localtalk card is a - * separate program and is not GPL'd source code, even though the Linux - * side driver and the routine that loads this data into the card are. - * - * It is taken from the COPS SDK and is under the following license - * - * This material is licensed to you strictly for use in conjunction with - * the use of COPS LocalTalk adapters. - * There is no charge for this SDK. And no waranty express or implied - * about its fitness for any purpose. However, we will cheerefully - * refund every penny you paid for this SDK... - * Regards, - * - * Thomas F. Divine - * Chief Scientist - */ - - -/* cops_ltdrv.h: LocalTalk driver firmware dump for Linux. - * - * Authors: - * - Jay Schulist <jschlst@samba.org> - */ - - -#ifdef CONFIG_COPS_TANGENT - -static const unsigned char ltdrv_code[] = { - 58,3,0,50,148,10,33,143,15,62,85,119, - 190,32,9,62,170,119,190,32,3,35,24,241, - 34,146,10,249,17,150,10,33,143,15,183,237, - 82,77,68,11,107,98,19,54,0,237,176,62, - 16,237,57,51,62,0,237,57,50,237,57,54, - 62,12,237,57,49,62,195,33,39,2,50,56, - 0,34,57,0,237,86,205,30,2,251,205,60, - 10,24,169,67,111,112,121,114,105,103,104,116, - 32,40,99,41,32,49,57,56,56,45,49,57, - 57,50,44,32,80,114,105,110,116,105,110,103, - 32,67,111,109,109,117,110,105,99,97,116,105, - 111,110,115,32,65,115,115,111,99,105,97,116, - 101,115,44,32,73,110,99,46,65,108,108,32, - 114,105,103,104,116,115,32,114,101,115,101,114, - 118,101,100,46,32,32,4,4,22,40,255,60, - 4,96,10,224,6,0,7,126,2,64,11,246, - 12,6,13,0,14,193,15,0,5,96,3,192, - 1,0,9,8,62,3,211,82,62,192,211,82, - 201,62,3,211,82,62,213,211,82,201,62,5, - 211,82,62,224,211,82,201,62,5,211,82,62, - 224,211,82,201,62,5,211,82,62,96,211,82, - 201,6,28,33,180,1,14,82,237,163,194,4, - 2,33,39,2,34,64,0,58,3,0,230,1, - 192,62,11,237,121,62,118,237,121,201,33,182, - 10,54,132,205,253,1,201,245,197,213,229,42, - 150,10,14,83,17,98,2,67,20,237,162,58, - 179,1,95,219,82,230,1,32,6,29,32,247, - 195,17,3,62,1,211,82,219,82,95,230,160, - 32,10,237,162,32,225,21,32,222,195,15,3, - 237,162,123,230,96,194,21,3,62,48,211,82, - 62,1,211,82,175,211,82,237,91,150,10,43, - 55,237,82,218,19,3,34,152,10,98,107,58, - 154,10,190,32,81,62,1,50,158,10,35,35, - 62,132,190,32,44,54,133,43,70,58,154,10, - 119,43,112,17,3,0,205,137,3,62,16,211, - 82,62,56,211,82,205,217,1,42,150,10,14, - 83,17,98,2,67,20,58,178,1,95,195,59, - 2,62,129,190,194,227,2,54,130,43,70,58, - 154,10,119,43,112,17,3,0,205,137,3,195, - 254,2,35,35,126,254,132,194,227,2,205,61, - 3,24,20,62,128,166,194,222,2,221,229,221, - 33,175,10,205,93,6,205,144,7,221,225,225, - 209,193,241,251,237,77,221,229,221,33,159,10, - 205,93,6,221,225,205,61,3,195,247,2,24, - 237,24,235,24,233,230,64,40,2,24,227,24, - 225,175,50,179,10,205,208,1,201,197,33,4, - 0,57,126,35,102,111,205,51,3,193,201,62, - 1,50,179,10,34,150,10,54,0,58,179,10, - 183,200,62,14,211,82,62,193,211,82,62,10, - 211,82,62,224,211,82,62,6,211,82,58,154, - 10,211,82,62,16,211,82,62,56,211,82,62, - 48,211,82,219,82,230,1,40,4,219,83,24, - 242,62,14,211,82,62,33,211,82,62,1,211, - 82,62,9,211,82,62,32,211,82,205,217,1, - 201,14,83,205,208,1,24,23,14,83,205,208, - 1,205,226,1,58,174,1,61,32,253,205,244, - 1,58,174,1,61,32,253,205,226,1,58,175, - 1,61,32,253,62,5,211,82,62,233,211,82, - 62,128,211,82,58,176,1,61,32,253,237,163, - 27,62,192,211,82,219,82,230,4,40,250,237, - 163,27,122,179,32,243,219,82,230,4,40,250, - 58,178,1,71,219,82,230,4,40,3,5,32, - 247,219,82,230,4,40,250,205,235,1,58,177, - 1,61,32,253,205,244,1,201,229,213,35,35, - 126,230,128,194,145,4,43,58,154,10,119,43, - 70,33,181,10,119,43,112,17,3,0,243,62, - 10,211,82,219,82,230,128,202,41,4,209,225, - 62,1,55,251,201,205,144,3,58,180,10,254, - 255,202,127,4,205,217,1,58,178,1,71,219, - 82,230,1,32,6,5,32,247,195,173,4,219, - 83,71,58,154,10,184,194,173,4,58,178,1, - 71,219,82,230,1,32,6,5,32,247,195,173, - 4,219,83,58,178,1,71,219,82,230,1,32, - 6,5,32,247,195,173,4,219,83,254,133,194, - 173,4,58,179,1,24,4,58,179,1,135,61, - 32,253,209,225,205,137,3,205,61,3,183,251, - 201,209,225,243,62,10,211,82,219,82,230,128, - 202,164,4,62,1,55,251,201,205,144,3,205, - 61,3,183,251,201,209,225,62,2,55,251,201, - 243,62,14,211,82,62,33,211,82,251,201,33, - 4,0,57,94,35,86,33,2,0,57,126,35, - 102,111,221,229,34,193,10,237,83,195,10,221, - 33,171,10,205,93,6,58,185,10,50,186,10, - 58,184,10,135,50,184,10,205,112,6,254,3, - 56,16,58,185,10,135,60,230,15,50,185,10, - 175,50,184,10,24,23,58,183,10,205,112,6, - 254,3,48,13,58,185,10,203,63,50,185,10, - 62,255,50,183,10,58,185,10,50,186,10,58, - 183,10,135,50,183,10,62,32,50,187,10,50, - 188,10,6,255,219,82,230,16,32,3,5,32, - 247,205,180,4,6,40,219,82,230,16,40,3, - 5,32,247,62,10,211,82,219,82,230,128,194, - 46,5,219,82,230,16,40,214,237,95,71,58, - 186,10,160,230,15,40,32,71,14,10,62,10, - 211,82,219,82,230,128,202,119,5,205,180,4, - 195,156,5,219,82,230,16,202,156,5,13,32, - 229,16,225,42,193,10,237,91,195,10,205,252, - 3,48,7,61,202,156,5,195,197,5,221,225, - 33,0,0,201,221,33,163,10,205,93,6,58, - 188,10,61,50,188,10,40,19,58,186,10,246, - 1,50,186,10,58,183,10,246,1,50,183,10, - 195,46,5,221,225,33,1,0,201,221,33,167, - 10,205,93,6,58,184,10,246,1,50,184,10, - 58,186,10,135,246,1,50,186,10,58,187,10, - 61,50,187,10,194,46,5,221,225,33,2,0, - 201,221,229,33,0,0,57,17,4,0,25,126, - 50,154,10,230,128,50,189,10,58,189,10,183, - 40,6,221,33,88,2,24,4,221,33,150,0, - 58,154,10,183,40,49,60,40,46,61,33,190, - 10,119,35,119,35,54,129,175,50,158,10,221, - 43,221,229,225,124,181,40,42,33,190,10,17, - 3,0,205,206,4,17,232,3,27,123,178,32, - 251,58,158,10,183,40,224,58,154,10,71,62, - 7,128,230,127,71,58,189,10,176,50,154,10, - 24,166,221,225,201,183,221,52,0,192,221,52, - 1,192,221,52,2,192,221,52,3,192,55,201, - 6,8,14,0,31,48,1,12,16,250,121,201, - 33,2,0,57,94,35,86,35,78,35,70,35, - 126,35,102,105,79,120,68,103,237,176,201,33, - 2,0,57,126,35,102,111,62,17,237,57,48, - 125,237,57,40,124,237,57,41,62,0,237,57, - 42,62,64,237,57,43,62,0,237,57,44,33, - 128,2,125,237,57,46,124,237,57,47,62,145, - 237,57,48,211,68,58,149,10,211,66,201,33, - 2,0,57,126,35,102,111,62,33,237,57,48, - 62,64,237,57,32,62,0,237,57,33,237,57, - 34,125,237,57,35,124,237,57,36,62,0,237, - 57,37,33,128,2,125,237,57,38,124,237,57, - 39,62,97,237,57,48,211,67,58,149,10,211, - 66,201,237,56,46,95,237,56,47,87,237,56, - 46,111,237,56,47,103,183,237,82,32,235,33, - 128,2,183,237,82,201,237,56,38,95,237,56, - 39,87,237,56,38,111,237,56,39,103,183,237, - 82,32,235,33,128,2,183,237,82,201,205,106, - 10,221,110,6,221,102,7,126,35,110,103,195, - 118,10,205,106,10,33,0,0,34,205,10,34, - 198,10,34,200,10,33,143,15,34,207,10,237, - 91,207,10,42,146,10,183,237,82,17,0,255, - 25,34,203,10,203,124,40,6,33,0,125,34, - 203,10,42,207,10,229,205,37,3,195,118,10, - 205,106,10,229,42,150,10,35,35,35,229,205, - 70,7,193,124,230,3,103,221,117,254,221,116, - 255,237,91,152,10,35,35,35,183,237,82,32, - 12,17,5,0,42,152,10,205,91,10,242,203, - 7,42,150,10,229,205,37,3,195,118,10,237, - 91,152,10,42,200,10,25,34,200,10,42,205, - 10,25,34,205,10,237,91,203,10,33,158,253, - 25,237,91,205,10,205,91,10,242,245,7,33, - 0,0,34,205,10,62,1,50,197,10,205,5, - 8,33,0,0,57,249,195,118,10,205,106,10, - 58,197,10,183,202,118,10,237,91,198,10,42, - 205,10,205,91,10,242,46,8,237,91,205,10, - 33,98,2,25,237,91,198,10,205,91,10,250, - 78,8,237,91,198,10,42,205,10,183,237,82, - 32,7,42,200,10,125,180,40,13,237,91,205, - 10,42,198,10,205,91,10,242,97,8,237,91, - 207,10,42,205,10,25,229,205,37,3,175,50, - 197,10,195,118,10,205,29,3,33,0,0,57, - 249,195,118,10,205,106,10,58,202,10,183,40, - 22,205,14,7,237,91,209,10,19,19,19,205, - 91,10,242,139,8,33,1,0,195,118,10,33, - 0,0,195,118,10,205,126,10,252,255,205,108, - 8,125,180,194,118,10,237,91,200,10,33,0, - 0,205,91,10,242,118,10,237,91,207,10,42, - 198,10,25,221,117,254,221,116,255,35,35,35, - 229,205,70,7,193,124,230,3,103,35,35,35, - 221,117,252,221,116,253,229,221,110,254,221,102, - 255,229,33,212,10,229,205,124,6,193,193,221, - 110,252,221,102,253,34,209,10,33,211,10,54, - 4,33,209,10,227,205,147,6,193,62,1,50, - 202,10,243,221,94,252,221,86,253,42,200,10, - 183,237,82,34,200,10,203,124,40,17,33,0, - 0,34,200,10,34,205,10,34,198,10,50,197, - 10,24,37,221,94,252,221,86,253,42,198,10, - 25,34,198,10,237,91,203,10,33,158,253,25, - 237,91,198,10,205,91,10,242,68,9,33,0, - 0,34,198,10,205,5,8,33,0,0,57,249, - 251,195,118,10,205,106,10,33,49,13,126,183, - 40,16,205,42,7,237,91,47,13,19,19,19, - 205,91,10,242,117,9,58,142,15,198,1,50, - 142,15,195,118,10,33,49,13,126,254,1,40, - 25,254,3,202,7,10,254,5,202,21,10,33, - 49,13,54,0,33,47,13,229,205,207,6,195, - 118,10,58,141,15,183,32,72,33,51,13,126, - 50,149,10,205,86,7,33,50,13,126,230,127, - 183,32,40,58,142,15,230,127,50,142,15,183, - 32,5,198,1,50,142,15,33,50,13,126,111, - 23,159,103,203,125,58,142,15,40,5,198,128, - 50,142,15,33,50,13,119,33,50,13,126,111, - 23,159,103,229,205,237,5,193,33,211,10,54, - 2,33,2,0,34,209,10,58,154,10,33,212, - 10,119,58,148,10,33,213,10,119,33,209,10, - 229,205,147,6,193,24,128,42,47,13,229,33, - 50,13,229,205,191,4,193,24,239,33,211,10, - 54,6,33,3,0,34,209,10,58,154,10,33, - 212,10,119,58,148,10,33,213,10,119,33,214, - 10,54,5,33,209,10,229,205,147,6,24,200, - 205,106,10,33,49,13,54,0,33,47,13,229, - 205,207,6,33,209,10,227,205,147,6,193,205, - 80,9,205,145,8,24,248,124,170,250,99,10, - 237,82,201,124,230,128,237,82,60,201,225,253, - 229,221,229,221,33,0,0,221,57,233,221,249, - 221,225,253,225,201,233,225,253,229,221,229,221, - 33,0,0,221,57,94,35,86,35,235,57,249, - 235,233,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0 - } ; - -#endif diff --git a/drivers/video/fbdev/nvidia/Makefile b/drivers/video/fbdev/nvidia/Makefile deleted file mode 100644 index cdd6e8ac454a..000000000000 --- a/drivers/video/fbdev/nvidia/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the nVidia framebuffer driver -# - -obj-$(CONFIG_FB_NVIDIA) += nvidiafb.o - -nvidiafb-y := nvidia.o nv_hw.o nv_setup.o \ - nv_accel.o nv_of.o -nvidiafb-$(CONFIG_FB_NVIDIA_I2C) += nv_i2c.o -nvidiafb-$(CONFIG_FB_NVIDIA_BACKLIGHT) += nv_backlight.o - -nvidiafb-objs := $(nvidiafb-y) diff --git a/drivers/video/fbdev/nvidia/nv_accel.c b/drivers/video/fbdev/nvidia/nv_accel.c deleted file mode 100644 index 7341fed63e35..000000000000 --- a/drivers/video/fbdev/nvidia/nv_accel.c +++ /dev/null @@ -1,418 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ - * XFree86 'nv' driver, this source code is provided under MIT-style licensing - * where the source code is provided "as is" without warranty of any kind. - * The only usage restriction is for the copyright notices to be retained - * whenever code is used. - * - * Antonino Daplas <adaplas@pol.net> 2005-03-11 - */ - -#include <linux/fb.h> -#include <linux/nmi.h> - -#include "nv_type.h" -#include "nv_proto.h" -#include "nv_dma.h" -#include "nv_local.h" - -/* There is a HW race condition with videoram command buffers. - You can't jump to the location of your put offset. We write put - at the jump offset + SKIPS dwords with noop padding in between - to solve this problem */ -#define SKIPS 8 - -static const int NVCopyROP[16] = { - 0xCC, /* copy */ - 0x55 /* invert */ -}; - -static const int NVCopyROP_PM[16] = { - 0xCA, /* copy */ - 0x5A, /* invert */ -}; - -static inline void nvidiafb_safe_mode(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - - touch_softlockup_watchdog(); - info->pixmap.scan_align = 1; - par->lockup = 1; -} - -static inline void NVFlush(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - int count = 1000000000; - - while (--count && READ_GET(par) != par->dmaPut) ; - - if (!count) { - printk("nvidiafb: DMA Flush lockup\n"); - nvidiafb_safe_mode(info); - } -} - -static inline void NVSync(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - int count = 1000000000; - - while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; - - if (!count) { - printk("nvidiafb: DMA Sync lockup\n"); - nvidiafb_safe_mode(info); - } -} - -static void NVDmaKickoff(struct nvidia_par *par) -{ - if (par->dmaCurrent != par->dmaPut) { - par->dmaPut = par->dmaCurrent; - WRITE_PUT(par, par->dmaPut); - } -} - -static void NVDmaWait(struct fb_info *info, int size) -{ - struct nvidia_par *par = info->par; - int dmaGet; - int count = 1000000000, cnt; - size++; - - while (par->dmaFree < size && --count && !par->lockup) { - dmaGet = READ_GET(par); - - if (par->dmaPut >= dmaGet) { - par->dmaFree = par->dmaMax - par->dmaCurrent; - if (par->dmaFree < size) { - NVDmaNext(par, 0x20000000); - if (dmaGet <= SKIPS) { - if (par->dmaPut <= SKIPS) - WRITE_PUT(par, SKIPS + 1); - cnt = 1000000000; - do { - dmaGet = READ_GET(par); - } while (--cnt && dmaGet <= SKIPS); - if (!cnt) { - printk("DMA Get lockup\n"); - par->lockup = 1; - } - } - WRITE_PUT(par, SKIPS); - par->dmaCurrent = par->dmaPut = SKIPS; - par->dmaFree = dmaGet - (SKIPS + 1); - } - } else - par->dmaFree = dmaGet - par->dmaCurrent - 1; - } - - if (!count) { - printk("nvidiafb: DMA Wait Lockup\n"); - nvidiafb_safe_mode(info); - } -} - -static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1, - u32 pat0, u32 pat1) -{ - struct nvidia_par *par = info->par; - - NVDmaStart(info, par, PATTERN_COLOR_0, 4); - NVDmaNext(par, clr0); - NVDmaNext(par, clr1); - NVDmaNext(par, pat0); - NVDmaNext(par, pat1); -} - -static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask) -{ - struct nvidia_par *par = info->par; - - if (planemask != ~0) { - NVSetPattern(info, 0, planemask, ~0, ~0); - if (par->currentRop != (rop + 32)) { - NVDmaStart(info, par, ROP_SET, 1); - NVDmaNext(par, NVCopyROP_PM[rop]); - par->currentRop = rop + 32; - } - } else if (par->currentRop != rop) { - if (par->currentRop >= 16) - NVSetPattern(info, ~0, ~0, ~0, ~0); - NVDmaStart(info, par, ROP_SET, 1); - NVDmaNext(par, NVCopyROP[rop]); - par->currentRop = rop; - } -} - -static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1, - int x2, int y2) -{ - struct nvidia_par *par = info->par; - int h = y2 - y1 + 1; - int w = x2 - x1 + 1; - - NVDmaStart(info, par, CLIP_POINT, 2); - NVDmaNext(par, (y1 << 16) | x1); - NVDmaNext(par, (h << 16) | w); -} - -void NVResetGraphics(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - u32 surfaceFormat, patternFormat, rectFormat, lineFormat; - int pitch, i; - - pitch = info->fix.line_length; - - par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]); - - for (i = 0; i < SKIPS; i++) - NV_WR32(&par->dmaBase[i], 0, 0x00000000); - - NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000); - NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010); - NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000); - NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011); - NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000); - NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012); - NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000); - NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013); - NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000); - NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014); - NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000); - NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015); - NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000); - NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016); - NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000); - NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017); - - par->dmaPut = 0; - par->dmaCurrent = 16 + SKIPS; - par->dmaMax = 8191; - par->dmaFree = par->dmaMax - par->dmaCurrent; - - switch (info->var.bits_per_pixel) { - case 32: - case 24: - surfaceFormat = SURFACE_FORMAT_DEPTH24; - patternFormat = PATTERN_FORMAT_DEPTH24; - rectFormat = RECT_FORMAT_DEPTH24; - lineFormat = LINE_FORMAT_DEPTH24; - break; - case 16: - surfaceFormat = SURFACE_FORMAT_DEPTH16; - patternFormat = PATTERN_FORMAT_DEPTH16; - rectFormat = RECT_FORMAT_DEPTH16; - lineFormat = LINE_FORMAT_DEPTH16; - break; - default: - surfaceFormat = SURFACE_FORMAT_DEPTH8; - patternFormat = PATTERN_FORMAT_DEPTH8; - rectFormat = RECT_FORMAT_DEPTH8; - lineFormat = LINE_FORMAT_DEPTH8; - break; - } - - NVDmaStart(info, par, SURFACE_FORMAT, 4); - NVDmaNext(par, surfaceFormat); - NVDmaNext(par, pitch | (pitch << 16)); - NVDmaNext(par, 0); - NVDmaNext(par, 0); - - NVDmaStart(info, par, PATTERN_FORMAT, 1); - NVDmaNext(par, patternFormat); - - NVDmaStart(info, par, RECT_FORMAT, 1); - NVDmaNext(par, rectFormat); - - NVDmaStart(info, par, LINE_FORMAT, 1); - NVDmaNext(par, lineFormat); - - par->currentRop = ~0; /* set to something invalid */ - NVSetRopSolid(info, ROP_COPY, ~0); - - NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual, - info->var.yres_virtual); - - NVDmaKickoff(par); -} - -int nvidiafb_sync(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - - if (info->state != FBINFO_STATE_RUNNING) - return 0; - - if (!par->lockup) - NVFlush(info); - - if (!par->lockup) - NVSync(info); - - return 0; -} - -void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) -{ - struct nvidia_par *par = info->par; - - if (info->state != FBINFO_STATE_RUNNING) - return; - - if (par->lockup) { - cfb_copyarea(info, region); - return; - } - - NVDmaStart(info, par, BLIT_POINT_SRC, 3); - NVDmaNext(par, (region->sy << 16) | region->sx); - NVDmaNext(par, (region->dy << 16) | region->dx); - NVDmaNext(par, (region->height << 16) | region->width); - - NVDmaKickoff(par); -} - -void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) -{ - struct nvidia_par *par = info->par; - u32 color; - - if (info->state != FBINFO_STATE_RUNNING) - return; - - if (par->lockup) { - cfb_fillrect(info, rect); - return; - } - - if (info->var.bits_per_pixel == 8) - color = rect->color; - else - color = ((u32 *) info->pseudo_palette)[rect->color]; - - if (rect->rop != ROP_COPY) - NVSetRopSolid(info, rect->rop, ~0); - - NVDmaStart(info, par, RECT_SOLID_COLOR, 1); - NVDmaNext(par, color); - - NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2); - NVDmaNext(par, (rect->dx << 16) | rect->dy); - NVDmaNext(par, (rect->width << 16) | rect->height); - - NVDmaKickoff(par); - - if (rect->rop != ROP_COPY) - NVSetRopSolid(info, ROP_COPY, ~0); -} - -static void nvidiafb_mono_color_expand(struct fb_info *info, - const struct fb_image *image) -{ - struct nvidia_par *par = info->par; - u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel)); - u32 dsize, width, *data = (u32 *) image->data, tmp; - int j, k = 0; - - width = (image->width + 31) & ~31; - dsize = (width * image->height) >> 5; - - if (info->var.bits_per_pixel == 8) { - fg = image->fg_color | mask; - bg = image->bg_color | mask; - } else { - fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask; - bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask; - } - - NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7); - NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff)); - NVDmaNext(par, ((image->dy + image->height) << 16) | - ((image->dx + image->width) & 0xffff)); - NVDmaNext(par, bg); - NVDmaNext(par, fg); - NVDmaNext(par, (image->height << 16) | width); - NVDmaNext(par, (image->height << 16) | width); - NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff)); - - while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) { - NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), - RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS); - - for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) { - tmp = data[k++]; - reverse_order(&tmp); - NVDmaNext(par, tmp); - } - - dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; - } - - if (dsize) { - NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize); - - for (j = dsize; j--;) { - tmp = data[k++]; - reverse_order(&tmp); - NVDmaNext(par, tmp); - } - } - - NVDmaKickoff(par); -} - -void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image) -{ - struct nvidia_par *par = info->par; - - if (info->state != FBINFO_STATE_RUNNING) - return; - - if (image->depth == 1 && !par->lockup) - nvidiafb_mono_color_expand(info, image); - else - cfb_imageblit(info, image); -} diff --git a/drivers/video/fbdev/nvidia/nv_backlight.c b/drivers/video/fbdev/nvidia/nv_backlight.c deleted file mode 100644 index 2ce53529f636..000000000000 --- a/drivers/video/fbdev/nvidia/nv_backlight.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Backlight code for nVidia based graphic cards - * - * Copyright 2004 Antonino Daplas <adaplas@pol.net> - * Copyright (c) 2006 Michael Hanselmann <linux-kernel@hansmi.ch> - */ - -#include <linux/backlight.h> -#include <linux/fb.h> -#include <linux/pci.h> - -#ifdef CONFIG_PMAC_BACKLIGHT -#include <asm/backlight.h> -#endif - -#include "nv_local.h" -#include "nv_type.h" -#include "nv_proto.h" - -/* We do not have any information about which values are allowed, thus - * we used safe values. - */ -#define MIN_LEVEL 0x158 -#define MAX_LEVEL 0x534 -#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) - -static int nvidia_bl_get_level_brightness(struct nvidia_par *par, - int level) -{ - struct fb_info *info = pci_get_drvdata(par->pci_dev); - int nlevel; - - /* Get and convert the value */ - /* No locking of bl_curve since we read a single value */ - nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; - - if (nlevel < 0) - nlevel = 0; - else if (nlevel < MIN_LEVEL) - nlevel = MIN_LEVEL; - else if (nlevel > MAX_LEVEL) - nlevel = MAX_LEVEL; - - return nlevel; -} - -static int nvidia_bl_update_status(struct backlight_device *bd) -{ - struct nvidia_par *par = bl_get_data(bd); - u32 tmp_pcrt, tmp_pmc, fpcontrol; - int level; - - if (!par->FlatPanel) - return 0; - - if (bd->props.power != FB_BLANK_UNBLANK || - bd->props.fb_blank != FB_BLANK_UNBLANK) - level = 0; - else - level = bd->props.brightness; - - tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; - tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC; - fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC; - - if (level > 0) { - tmp_pcrt |= 0x1; - tmp_pmc |= (1 << 31); /* backlight bit */ - tmp_pmc |= nvidia_bl_get_level_brightness(par, level) << 16; - fpcontrol |= par->fpSyncs; - } else - fpcontrol |= 0x20000022; - - NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt); - NV_WR32(par->PMC, 0x10F0, tmp_pmc); - NV_WR32(par->PRAMDAC, 0x848, fpcontrol); - - return 0; -} - -static const struct backlight_ops nvidia_bl_ops = { - .update_status = nvidia_bl_update_status, -}; - -void nvidia_bl_init(struct nvidia_par *par) -{ - struct backlight_properties props; - struct fb_info *info = pci_get_drvdata(par->pci_dev); - struct backlight_device *bd; - char name[12]; - - if (!par->FlatPanel) - return; - -#ifdef CONFIG_PMAC_BACKLIGHT - if (!machine_is(powermac) || - !pmac_has_backlight_type("mnca")) - return; -#endif - - snprintf(name, sizeof(name), "nvidiabl%d", info->node); - - memset(&props, 0, sizeof(struct backlight_properties)); - props.type = BACKLIGHT_RAW; - props.max_brightness = FB_BACKLIGHT_LEVELS - 1; - bd = backlight_device_register(name, info->dev, par, &nvidia_bl_ops, - &props); - if (IS_ERR(bd)) { - info->bl_dev = NULL; - printk(KERN_WARNING "nvidia: Backlight registration failed\n"); - goto error; - } - - info->bl_dev = bd; - fb_bl_default_curve(info, 0, - 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL, - 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL); - - bd->props.brightness = bd->props.max_brightness; - bd->props.power = FB_BLANK_UNBLANK; - backlight_update_status(bd); - - printk("nvidia: Backlight initialized (%s)\n", name); - -error: - return; -} - -void nvidia_bl_exit(struct nvidia_par *par) -{ - struct fb_info *info = pci_get_drvdata(par->pci_dev); - struct backlight_device *bd = info->bl_dev; - - backlight_device_unregister(bd); - printk("nvidia: Backlight unloaded\n"); -} diff --git a/drivers/video/fbdev/nvidia/nv_dma.h b/drivers/video/fbdev/nvidia/nv_dma.h deleted file mode 100644 index a7ed1c0acbbb..000000000000 --- a/drivers/video/fbdev/nvidia/nv_dma.h +++ /dev/null @@ -1,188 +0,0 @@ - - /***************************************************************************\ -|* *| -|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ - * XFree86 'nv' driver, this source code is provided under MIT-style licensing - * where the source code is provided "as is" without warranty of any kind. - * The only usage restriction is for the copyright notices to be retained - * whenever code is used. - * - * Antonino Daplas <adaplas@pol.net> 2005-03-11 - */ - -#define SURFACE_FORMAT 0x00000300 -#define SURFACE_FORMAT_DEPTH8 0x00000001 -#define SURFACE_FORMAT_DEPTH15 0x00000002 -#define SURFACE_FORMAT_DEPTH16 0x00000004 -#define SURFACE_FORMAT_DEPTH24 0x00000006 -#define SURFACE_PITCH 0x00000304 -#define SURFACE_PITCH_SRC 15:0 -#define SURFACE_PITCH_DST 31:16 -#define SURFACE_OFFSET_SRC 0x00000308 -#define SURFACE_OFFSET_DST 0x0000030C - -#define ROP_SET 0x00002300 - -#define PATTERN_FORMAT 0x00004300 -#define PATTERN_FORMAT_DEPTH8 0x00000003 -#define PATTERN_FORMAT_DEPTH16 0x00000001 -#define PATTERN_FORMAT_DEPTH24 0x00000003 -#define PATTERN_COLOR_0 0x00004310 -#define PATTERN_COLOR_1 0x00004314 -#define PATTERN_PATTERN_0 0x00004318 -#define PATTERN_PATTERN_1 0x0000431C - -#define CLIP_POINT 0x00006300 -#define CLIP_POINT_X 15:0 -#define CLIP_POINT_Y 31:16 -#define CLIP_SIZE 0x00006304 -#define CLIP_SIZE_WIDTH 15:0 -#define CLIP_SIZE_HEIGHT 31:16 - -#define LINE_FORMAT 0x00008300 -#define LINE_FORMAT_DEPTH8 0x00000003 -#define LINE_FORMAT_DEPTH16 0x00000001 -#define LINE_FORMAT_DEPTH24 0x00000003 -#define LINE_COLOR 0x00008304 -#define LINE_MAX_LINES 16 -#define LINE_LINES(i) 0x00008400\ - +(i)*8 -#define LINE_LINES_POINT0_X 15:0 -#define LINE_LINES_POINT0_Y 31:16 -#define LINE_LINES_POINT1_X 47:32 -#define LINE_LINES_POINT1_Y 63:48 - -#define BLIT_POINT_SRC 0x0000A300 -#define BLIT_POINT_SRC_X 15:0 -#define BLIT_POINT_SRC_Y 31:16 -#define BLIT_POINT_DST 0x0000A304 -#define BLIT_POINT_DST_X 15:0 -#define BLIT_POINT_DST_Y 31:16 -#define BLIT_SIZE 0x0000A308 -#define BLIT_SIZE_WIDTH 15:0 -#define BLIT_SIZE_HEIGHT 31:16 - -#define RECT_FORMAT 0x0000C300 -#define RECT_FORMAT_DEPTH8 0x00000003 -#define RECT_FORMAT_DEPTH16 0x00000001 -#define RECT_FORMAT_DEPTH24 0x00000003 -#define RECT_SOLID_COLOR 0x0000C3FC -#define RECT_SOLID_RECTS_MAX_RECTS 32 -#define RECT_SOLID_RECTS(i) 0x0000C400\ - +(i)*8 -#define RECT_SOLID_RECTS_Y 15:0 -#define RECT_SOLID_RECTS_X 31:16 -#define RECT_SOLID_RECTS_HEIGHT 47:32 -#define RECT_SOLID_RECTS_WIDTH 63:48 - -#define RECT_EXPAND_ONE_COLOR_CLIP 0x0000C7EC -#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_X 15:0 -#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y 31:16 -#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_X 47:32 -#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_Y 63:48 -#define RECT_EXPAND_ONE_COLOR_COLOR 0x0000C7F4 -#define RECT_EXPAND_ONE_COLOR_SIZE 0x0000C7F8 -#define RECT_EXPAND_ONE_COLOR_SIZE_WIDTH 15:0 -#define RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT 31:16 -#define RECT_EXPAND_ONE_COLOR_POINT 0x0000C7FC -#define RECT_EXPAND_ONE_COLOR_POINT_X 15:0 -#define RECT_EXPAND_ONE_COLOR_POINT_Y 31:16 -#define RECT_EXPAND_ONE_COLOR_DATA_MAX_DWORDS 128 -#define RECT_EXPAND_ONE_COLOR_DATA(i) 0x0000C800\ - +(i)*4 - -#define RECT_EXPAND_TWO_COLOR_CLIP 0x0000CBE4 -#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_X 15:0 -#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_Y 31:16 -#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_X 47:32 -#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_Y 63:48 -#define RECT_EXPAND_TWO_COLOR_COLOR_0 0x0000CBEC -#define RECT_EXPAND_TWO_COLOR_COLOR_1 0x0000CBF0 -#define RECT_EXPAND_TWO_COLOR_SIZE_IN 0x0000CBF4 -#define RECT_EXPAND_TWO_COLOR_SIZE_IN_WIDTH 15:0 -#define RECT_EXPAND_TWO_COLOR_SIZE_IN_HEIGHT 31:16 -#define RECT_EXPAND_TWO_COLOR_SIZE_OUT 0x0000CBF8 -#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_WIDTH 15:0 -#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_HEIGHT 31:16 -#define RECT_EXPAND_TWO_COLOR_POINT 0x0000CBFC -#define RECT_EXPAND_TWO_COLOR_POINT_X 15:0 -#define RECT_EXPAND_TWO_COLOR_POINT_Y 31:16 -#define RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS 128 -#define RECT_EXPAND_TWO_COLOR_DATA(i) 0x0000CC00\ - +(i)*4 - -#define STRETCH_BLIT_FORMAT 0x0000E300 -#define STRETCH_BLIT_FORMAT_DEPTH8 0x00000004 -#define STRETCH_BLIT_FORMAT_DEPTH16 0x00000007 -#define STRETCH_BLIT_FORMAT_DEPTH24 0x00000004 -#define STRETCH_BLIT_FORMAT_X8R8G8B8 0x00000004 -#define STRETCH_BLIT_FORMAT_YUYV 0x00000005 -#define STRETCH_BLIT_FORMAT_UYVY 0x00000006 -#define STRETCH_BLIT_CLIP_POINT 0x0000E308 -#define STRETCH_BLIT_CLIP_POINT_X 15:0 -#define STRETCH_BLIT_CLIP_POINT_Y 31:16 -#define STRETCH_BLIT_CLIP_POINT 0x0000E308 -#define STRETCH_BLIT_CLIP_SIZE 0x0000E30C -#define STRETCH_BLIT_CLIP_SIZE_WIDTH 15:0 -#define STRETCH_BLIT_CLIP_SIZE_HEIGHT 31:16 -#define STRETCH_BLIT_DST_POINT 0x0000E310 -#define STRETCH_BLIT_DST_POINT_X 15:0 -#define STRETCH_BLIT_DST_POINT_Y 31:16 -#define STRETCH_BLIT_DST_SIZE 0x0000E314 -#define STRETCH_BLIT_DST_SIZE_WIDTH 15:0 -#define STRETCH_BLIT_DST_SIZE_HEIGHT 31:16 -#define STRETCH_BLIT_DU_DX 0x0000E318 -#define STRETCH_BLIT_DV_DY 0x0000E31C -#define STRETCH_BLIT_SRC_SIZE 0x0000E400 -#define STRETCH_BLIT_SRC_SIZE_WIDTH 15:0 -#define STRETCH_BLIT_SRC_SIZE_HEIGHT 31:16 -#define STRETCH_BLIT_SRC_FORMAT 0x0000E404 -#define STRETCH_BLIT_SRC_FORMAT_PITCH 15:0 -#define STRETCH_BLIT_SRC_FORMAT_ORIGIN 23:16 -#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CENTER 0x00000001 -#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CORNER 0x00000002 -#define STRETCH_BLIT_SRC_FORMAT_FILTER 31:24 -#define STRETCH_BLIT_SRC_FORMAT_FILTER_POINT_SAMPLE 0x00000000 -#define STRETCH_BLIT_SRC_FORMAT_FILTER_BILINEAR 0x00000001 -#define STRETCH_BLIT_SRC_OFFSET 0x0000E408 -#define STRETCH_BLIT_SRC_POINT 0x0000E40C -#define STRETCH_BLIT_SRC_POINT_U 15:0 -#define STRETCH_BLIT_SRC_POINT_V 31:16 diff --git a/drivers/video/fbdev/nvidia/nv_hw.c b/drivers/video/fbdev/nvidia/nv_hw.c deleted file mode 100644 index 9b0a324bb1b4..000000000000 --- a/drivers/video/fbdev/nvidia/nv_hw.c +++ /dev/null @@ -1,1688 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ - * XFree86 'nv' driver, this source code is provided under MIT-style licensing - * where the source code is provided "as is" without warranty of any kind. - * The only usage restriction is for the copyright notices to be retained - * whenever code is used. - * - * Antonino Daplas <adaplas@pol.net> 2005-03-11 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */ - -#include <linux/pci.h> -#include "nv_type.h" -#include "nv_local.h" -#include "nv_proto.h" - -void NVLockUnlock(struct nvidia_par *par, int Lock) -{ - u8 cr11; - - VGA_WR08(par->PCIO, 0x3D4, 0x1F); - VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); - - VGA_WR08(par->PCIO, 0x3D4, 0x11); - cr11 = VGA_RD08(par->PCIO, 0x3D5); - if (Lock) - cr11 |= 0x80; - else - cr11 &= ~0x80; - VGA_WR08(par->PCIO, 0x3D5, cr11); -} - -int NVShowHideCursor(struct nvidia_par *par, int ShowHide) -{ - int cur = par->CurrentState->cursor1; - - par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | - (ShowHide & 0x01); - VGA_WR08(par->PCIO, 0x3D4, 0x31); - VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1); - - if (par->Architecture == NV_ARCH_40) - NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300)); - - return (cur & 0x01); -} - -/****************************************************************************\ -* * -* The video arbitration routines calculate some "magic" numbers. Fixes * -* the snow seen when accessing the framebuffer without it. * -* It just works (I hope). * -* * -\****************************************************************************/ - -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv4_fifo_info; - -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv4_sim_state; - -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv10_fifo_info; - -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - u32 memory_type; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv10_sim_state; - -static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk, - unsigned int *NVClk) -{ - unsigned int pll, N, M, MB, NB, P; - - if (par->Architecture >= NV_ARCH_40) { - pll = NV_RD32(par->PMC, 0x4020); - P = (pll >> 16) & 0x07; - pll = NV_RD32(par->PMC, 0x4024); - M = pll & 0xFF; - N = (pll >> 8) & 0xFF; - if (((par->Chipset & 0xfff0) == 0x0290) || - ((par->Chipset & 0xfff0) == 0x0390)) { - MB = 1; - NB = 1; - } else { - MB = (pll >> 16) & 0xFF; - NB = (pll >> 24) & 0xFF; - } - *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; - - pll = NV_RD32(par->PMC, 0x4000); - P = (pll >> 16) & 0x07; - pll = NV_RD32(par->PMC, 0x4004); - M = pll & 0xFF; - N = (pll >> 8) & 0xFF; - MB = (pll >> 16) & 0xFF; - NB = (pll >> 24) & 0xFF; - - *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; - } else if (par->twoStagePLL) { - pll = NV_RD32(par->PRAMDAC0, 0x0504); - M = pll & 0xFF; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x0F; - pll = NV_RD32(par->PRAMDAC0, 0x0574); - if (pll & 0x80000000) { - MB = pll & 0xFF; - NB = (pll >> 8) & 0xFF; - } else { - MB = 1; - NB = 1; - } - *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; - - pll = NV_RD32(par->PRAMDAC0, 0x0500); - M = pll & 0xFF; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x0F; - pll = NV_RD32(par->PRAMDAC0, 0x0570); - if (pll & 0x80000000) { - MB = pll & 0xFF; - NB = (pll >> 8) & 0xFF; - } else { - MB = 1; - NB = 1; - } - *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; - } else - if (((par->Chipset & 0x0ff0) == 0x0300) || - ((par->Chipset & 0x0ff0) == 0x0330)) { - pll = NV_RD32(par->PRAMDAC0, 0x0504); - M = pll & 0x0F; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x07; - if (pll & 0x00000080) { - MB = (pll >> 4) & 0x07; - NB = (pll >> 19) & 0x1f; - } else { - MB = 1; - NB = 1; - } - *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; - - pll = NV_RD32(par->PRAMDAC0, 0x0500); - M = pll & 0x0F; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x07; - if (pll & 0x00000080) { - MB = (pll >> 4) & 0x07; - NB = (pll >> 19) & 0x1f; - } else { - MB = 1; - NB = 1; - } - *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; - } else { - pll = NV_RD32(par->PRAMDAC0, 0x0504); - M = pll & 0xFF; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x0F; - *MClk = (N * par->CrystalFreqKHz / M) >> P; - - pll = NV_RD32(par->PRAMDAC0, 0x0500); - M = pll & 0xFF; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x0F; - *NVClk = (N * par->CrystalFreqKHz / M) >> P; - } -} - -static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb) -{ - int data, pagemiss, cas, width, video_enable, bpp; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; - int found, mclk_extra, mclk_loop, cbs, m1, p1; - int mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; - int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - cas = arb->mem_latency; - width = arb->memory_width >> 6; - video_enable = arb->enable_video; - bpp = arb->pix_bpp; - mp_enable = arb->enable_mp; - clwm = 0; - vlwm = 0; - cbs = 128; - pclks = 2; - nvclks = 2; - nvclks += 2; - nvclks += 1; - mclks = 5; - mclks += 3; - mclks += 1; - mclks += cas; - mclks += 1; - mclks += 1; - mclks += 1; - mclks += 1; - mclk_extra = 3; - nvclks += 2; - nvclks += 1; - nvclks += 1; - nvclks += 1; - if (mp_enable) - mclks += 4; - nvclks += 0; - pclks += 0; - found = 0; - vbs = 0; - while (found != 1) { - fifo->valid = 1; - found = 1; - mclk_loop = mclks + mclk_extra; - us_m = mclk_loop * 1000 * 1000 / mclk_freq; - us_n = nvclks * 1000 * 1000 / nvclk_freq; - us_p = nvclks * 1000 * 1000 / pclk_freq; - if (video_enable) { - video_drain_rate = pclk_freq * 2; - crtc_drain_rate = pclk_freq * bpp / 8; - vpagemiss = 2; - vpagemiss += 1; - crtpagemiss = 2; - vpm_us = - (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = - cbs * 1000 * 1000 / 16 / nvclk_freq; - else - video_fill_us = - cbs * 1000 * 1000 / (8 * width) / - mclk_freq; - us_video = vpm_us + us_m + us_n + us_p + video_fill_us; - vlwm = us_video * video_drain_rate / (1000 * 1000); - vlwm++; - vbs = 128; - if (vlwm > 128) - vbs = 64; - if (vlwm > (256 - 64)) - vbs = 32; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = - vbs * 1000 * 1000 / 16 / nvclk_freq; - else - video_fill_us = - vbs * 1000 * 1000 / (8 * width) / - mclk_freq; - cpm_us = - crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; - us_crt = - us_video + video_fill_us + cpm_us + us_m + us_n + - us_p; - clwm = us_crt * crtc_drain_rate / (1000 * 1000); - clwm++; - } else { - crtc_drain_rate = pclk_freq * bpp / 8; - crtpagemiss = 2; - crtpagemiss += 1; - cpm_us = - crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p; - clwm = us_crt * crtc_drain_rate / (1000 * 1000); - clwm++; - } - m1 = clwm + cbs - 512; - p1 = m1 * pclk_freq / mclk_freq; - p1 = p1 * bpp / 8; - if ((p1 < m1) && (m1 > 0)) { - fifo->valid = 0; - found = 0; - if (mclk_extra == 0) - found = 1; - mclk_extra--; - } else if (video_enable) { - if ((clwm > 511) || (vlwm > 255)) { - fifo->valid = 0; - found = 0; - if (mclk_extra == 0) - found = 1; - mclk_extra--; - } - } else { - if (clwm > 519) { - fifo->valid = 0; - found = 0; - if (mclk_extra == 0) - found = 1; - mclk_extra--; - } - } - if (clwm < 384) - clwm = 384; - if (vlwm < 128) - vlwm = 128; - data = (int)(clwm); - fifo->graphics_lwm = data; - fifo->graphics_burst_size = 128; - data = (int)((vlwm + 15)); - fifo->video_lwm = data; - fifo->video_burst_size = vbs; - } -} - -static void nv4UpdateArbitrationSettings(unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, struct nvidia_par *par) -{ - nv4_fifo_info fifo_data; - nv4_sim_state sim_data; - unsigned int MClk, NVClk, cfg1; - - nvGetClocks(par, &MClk, &NVClk); - - cfg1 = NV_RD32(par->PFB, 0x00000204); - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? - 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = - (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv4CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb) -{ - int data, pagemiss, width, video_enable, bpp; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss; - int nvclk_fill; - int found, mclk_extra, mclk_loop, cbs, m1; - int mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_m_min, us_n, us_p, crtc_drain_rate; - int vus_m; - int vpm_us, us_video, cpm_us, us_crt, clwm; - int clwm_rnd_down; - int m2us, us_pipe_min, p1clk, p2; - int min_mclk_extra; - int us_min_mclk_extra; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; /* freq in KHz */ - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - width = arb->memory_width / 64; - video_enable = arb->enable_video; - bpp = arb->pix_bpp; - mp_enable = arb->enable_mp; - clwm = 0; - - cbs = 512; - - pclks = 4; /* lwm detect. */ - - nvclks = 3; /* lwm -> sync. */ - nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ - /* 2 edge sync. may be very close to edge so just put one. */ - mclks = 1; - mclks += 1; /* arb_hp_req */ - mclks += 5; /* ap_hp_req tiling pipeline */ - - mclks += 2; /* tc_req latency fifo */ - mclks += 2; /* fb_cas_n_ memory request to fbio block */ - mclks += 7; /* sm_d_rdv data returned from fbio block */ - - /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ - if (arb->memory_type == 0) - if (arb->memory_width == 64) /* 64 bit bus */ - mclks += 4; - else - mclks += 2; - else if (arb->memory_width == 64) /* 64 bit bus */ - mclks += 2; - else - mclks += 1; - - if ((!video_enable) && (arb->memory_width == 128)) { - mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ - min_mclk_extra = 17; - } else { - mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ - /* mclk_extra = 4; *//* Margin of error */ - min_mclk_extra = 18; - } - - /* 2 edge sync. may be very close to edge so just put one. */ - nvclks += 1; - nvclks += 1; /* fbi_d_rdv_n */ - nvclks += 1; /* Fbi_d_rdata */ - nvclks += 1; /* crtfifo load */ - - if (mp_enable) - mclks += 4; /* Mp can get in with a burst of 8. */ - /* Extra clocks determined by heuristics */ - - nvclks += 0; - pclks += 0; - found = 0; - while (found != 1) { - fifo->valid = 1; - found = 1; - mclk_loop = mclks + mclk_extra; - /* Mclk latency in us */ - us_m = mclk_loop * 1000 * 1000 / mclk_freq; - /* Minimum Mclk latency in us */ - us_m_min = mclks * 1000 * 1000 / mclk_freq; - us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq; - /* nvclk latency in us */ - us_n = nvclks * 1000 * 1000 / nvclk_freq; - /* nvclk latency in us */ - us_p = pclks * 1000 * 1000 / pclk_freq; - us_pipe_min = us_m_min + us_n + us_p; - - /* Mclk latency in us */ - vus_m = mclk_loop * 1000 * 1000 / mclk_freq; - - if (video_enable) { - crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */ - - vpagemiss = 1; /* self generating page miss */ - vpagemiss += 1; /* One higher priority before */ - - crtpagemiss = 2; /* self generating page miss */ - if (mp_enable) - crtpagemiss += 1; /* if MA0 conflict */ - - vpm_us = - (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq; - - /* Video has separate read return path */ - us_video = vpm_us + vus_m; - - cpm_us = - crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; - /* Wait for video */ - us_crt = us_video - + cpm_us /* CRT Page miss */ - + us_m + us_n + us_p /* other latency */ - ; - - clwm = us_crt * crtc_drain_rate / (1000 * 1000); - /* fixed point <= float_point - 1. Fixes that */ - clwm++; - } else { - /* bpp * pclk/8 */ - crtc_drain_rate = pclk_freq * bpp / 8; - - crtpagemiss = 1; /* self generating page miss */ - crtpagemiss += 1; /* MA0 page miss */ - if (mp_enable) - crtpagemiss += 1; /* if MA0 conflict */ - cpm_us = - crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p; - clwm = us_crt * crtc_drain_rate / (1000 * 1000); - /* fixed point <= float_point - 1. Fixes that */ - clwm++; - - /* Finally, a heuristic check when width == 64 bits */ - if (width == 1) { - nvclk_fill = nvclk_freq * 8; - if (crtc_drain_rate * 100 >= nvclk_fill * 102) - /*Large number to fail */ - clwm = 0xfff; - - else if (crtc_drain_rate * 100 >= - nvclk_fill * 98) { - clwm = 1024; - cbs = 512; - } - } - } - - /* - Overfill check: - */ - - clwm_rnd_down = ((int)clwm / 8) * 8; - if (clwm_rnd_down < clwm) - clwm += 8; - - m1 = clwm + cbs - 1024; /* Amount of overfill */ - m2us = us_pipe_min + us_min_mclk_extra; - - /* pclk cycles to drain */ - p1clk = m2us * pclk_freq / (1000 * 1000); - p2 = p1clk * bpp / 8; /* bytes drained. */ - - if ((p2 < m1) && (m1 > 0)) { - fifo->valid = 0; - found = 0; - if (min_mclk_extra == 0) { - if (cbs <= 32) { - /* Can't adjust anymore! */ - found = 1; - } else { - /* reduce the burst size */ - cbs = cbs / 2; - } - } else { - min_mclk_extra--; - } - } else { - if (clwm > 1023) { /* Have some margin */ - fifo->valid = 0; - found = 0; - if (min_mclk_extra == 0) - /* Can't adjust anymore! */ - found = 1; - else - min_mclk_extra--; - } - } - - if (clwm < (1024 - cbs + 8)) - clwm = 1024 - cbs + 8; - data = (int)(clwm); - /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", - clwm, data ); */ - fifo->graphics_lwm = data; - fifo->graphics_burst_size = cbs; - - fifo->video_lwm = 1024; - fifo->video_burst_size = 512; - } -} - -static void nv10UpdateArbitrationSettings(unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - struct nvidia_par *par) -{ - nv10_fifo_info fifo_data; - nv10_sim_state sim_data; - unsigned int MClk, NVClk, cfg1; - - nvGetClocks(par, &MClk, &NVClk); - - cfg1 = NV_RD32(par->PFB, 0x0204); - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 1; - sim_data.enable_mp = 0; - sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; - sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? - 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = - (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv10CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -static void nv30UpdateArbitrationSettings ( - struct nvidia_par *par, - unsigned int *burst, - unsigned int *lwm -) -{ - unsigned int MClk, NVClk; - unsigned int fifo_size, burst_size, graphics_lwm; - - fifo_size = 2048; - burst_size = 512; - graphics_lwm = fifo_size - burst_size; - - nvGetClocks(par, &MClk, &NVClk); - - *burst = 0; - burst_size >>= 5; - while(burst_size >>= 1) (*burst)++; - *lwm = graphics_lwm >> 3; -} - -static void nForceUpdateArbitrationSettings(unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - struct nvidia_par *par) -{ - nv10_fifo_info fifo_data; - nv10_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk, memctrl; - struct pci_dev *dev; - int domain = pci_domain_nr(par->pci_dev->bus); - - if ((par->Chipset & 0x0FF0) == 0x01A0) { - unsigned int uMClkPostDiv; - dev = pci_get_domain_bus_and_slot(domain, 0, 3); - pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); - uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; - - if (!uMClkPostDiv) - uMClkPostDiv = 4; - MClk = 400000 / uMClkPostDiv; - } else { - dev = pci_get_domain_bus_and_slot(domain, 0, 5); - pci_read_config_dword(dev, 0x4c, &MClk); - MClk /= 1000; - } - pci_dev_put(dev); - pll = NV_RD32(par->PRAMDAC0, 0x0500); - M = (pll >> 0) & 0xFF; - N = (pll >> 8) & 0xFF; - P = (pll >> 16) & 0x0F; - NVClk = (N * par->CrystalFreqKHz / M) >> P; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - dev = pci_get_domain_bus_and_slot(domain, 0, 1); - pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); - pci_dev_put(dev); - sim_data.memory_type = (sim_data.memory_type >> 12) & 1; - sim_data.memory_width = 64; - - dev = pci_get_domain_bus_and_slot(domain, 0, 3); - pci_read_config_dword(dev, 0, &memctrl); - pci_dev_put(dev); - memctrl >>= 16; - - if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) { - u32 dimm[3]; - - dev = pci_get_domain_bus_and_slot(domain, 0, 2); - pci_read_config_dword(dev, 0x40, &dimm[0]); - dimm[0] = (dimm[0] >> 8) & 0x4f; - pci_read_config_dword(dev, 0x44, &dimm[1]); - dimm[1] = (dimm[1] >> 8) & 0x4f; - pci_read_config_dword(dev, 0x48, &dimm[2]); - dimm[2] = (dimm[2] >> 8) & 0x4f; - - if ((dimm[0] + dimm[1]) != dimm[2]) { - printk("nvidiafb: your nForce DIMMs are not arranged " - "in optimal banks!\n"); - } - pci_dev_put(dev); - } - - sim_data.mem_latency = 3; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 10; - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv10CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -/****************************************************************************\ -* * -* RIVA Mode State Routines * -* * -\****************************************************************************/ - -/* - * Calculate the Video Clock parameters for the PLL. - */ -static void CalcVClock(int clockIn, - int *clockOut, u32 * pllOut, struct nvidia_par *par) -{ - unsigned lowM, highM; - unsigned DeltaNew, DeltaOld; - unsigned VClk, Freq; - unsigned M, N, P; - - DeltaOld = 0xFFFFFFFF; - - VClk = (unsigned)clockIn; - - if (par->CrystalFreqKHz == 13500) { - lowM = 7; - highM = 13; - } else { - lowM = 8; - highM = 14; - } - - for (P = 0; P <= 4; P++) { - Freq = VClk << P; - if ((Freq >= 128000) && (Freq <= 350000)) { - for (M = lowM; M <= highM; M++) { - N = ((VClk << P) * M) / par->CrystalFreqKHz; - if (N <= 255) { - Freq = - ((par->CrystalFreqKHz * N) / - M) >> P; - if (Freq > VClk) - DeltaNew = Freq - VClk; - else - DeltaNew = VClk - Freq; - if (DeltaNew < DeltaOld) { - *pllOut = - (P << 16) | (N << 8) | M; - *clockOut = Freq; - DeltaOld = DeltaNew; - } - } - } - } - } -} - -static void CalcVClock2Stage(int clockIn, - int *clockOut, - u32 * pllOut, - u32 * pllBOut, struct nvidia_par *par) -{ - unsigned DeltaNew, DeltaOld; - unsigned VClk, Freq; - unsigned M, N, P; - - DeltaOld = 0xFFFFFFFF; - - *pllBOut = 0x80000401; /* fixed at x4 for now */ - - VClk = (unsigned)clockIn; - - for (P = 0; P <= 6; P++) { - Freq = VClk << P; - if ((Freq >= 400000) && (Freq <= 1000000)) { - for (M = 1; M <= 13; M++) { - N = ((VClk << P) * M) / - (par->CrystalFreqKHz << 2); - if ((N >= 5) && (N <= 255)) { - Freq = - (((par->CrystalFreqKHz << 2) * N) / - M) >> P; - if (Freq > VClk) - DeltaNew = Freq - VClk; - else - DeltaNew = VClk - Freq; - if (DeltaNew < DeltaOld) { - *pllOut = - (P << 16) | (N << 8) | M; - *clockOut = Freq; - DeltaOld = DeltaNew; - } - } - } - } - } -} - -/* - * Calculate extended mode parameters (SVGA) and save in a - * mode state structure. - */ -void NVCalcStateExt(struct nvidia_par *par, - RIVA_HW_STATE * state, - int bpp, - int width, - int hDisplaySize, int height, int dotClock, int flags) -{ - int pixelDepth, VClk = 0; - /* - * Save mode parameters. - */ - state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ - state->width = width; - state->height = height; - /* - * Extended RIVA registers. - */ - pixelDepth = (bpp + 1) / 8; - if (par->twoStagePLL) - CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, - par); - else - CalcVClock(dotClock, &VClk, &state->pll, par); - - switch (par->Architecture) { - case NV_ARCH_04: - nv4UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), par); - state->cursor0 = 0x00; - state->cursor1 = 0xbC; - if (flags & FB_VMODE_DOUBLE) - state->cursor1 |= 2; - state->cursor2 = 0x00000000; - state->pllsel = 0x10000700; - state->config = 0x00001114; - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - case NV_ARCH_40: - if (!par->FlatPanel) - state->control = NV_RD32(par->PRAMDAC0, 0x0580) & - 0xeffffeff; - fallthrough; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - default: - if ((par->Chipset & 0xfff0) == 0x0240 || - (par->Chipset & 0xfff0) == 0x03d0) { - state->arbitration0 = 256; - state->arbitration1 = 0x0480; - } else if (((par->Chipset & 0xffff) == 0x01A0) || - ((par->Chipset & 0xffff) == 0x01f0)) { - nForceUpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - par); - } else if (par->Architecture < NV_ARCH_30) { - nv10UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - par); - } else { - nv30UpdateArbitrationSettings(par, - &(state->arbitration0), - &(state->arbitration1)); - } - - state->cursor0 = 0x80 | (par->CursorStart >> 17); - state->cursor1 = (par->CursorStart >> 11) << 2; - state->cursor2 = par->CursorStart >> 24; - if (flags & FB_VMODE_DOUBLE) - state->cursor1 |= 2; - state->pllsel = 0x10000700; - state->config = NV_RD32(par->PFB, 0x00000200); - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - } - - if (bpp != 8) /* DirectColor */ - state->general |= 0x00000030; - - state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3; - state->pixel = (pixelDepth > 2) ? 3 : pixelDepth; -} - -void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) -{ - int i, j; - - NV_WR32(par->PMC, 0x0140, 0x00000000); - NV_WR32(par->PMC, 0x0200, 0xFFFF00FF); - NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF); - - NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008); - NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003); - NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000); - NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF); - - if (par->Architecture == NV_ARCH_04) { - if (state) - NV_WR32(par->PFB, 0x0200, state->config); - } else if ((par->Architecture < NV_ARCH_40) || - (par->Chipset & 0xfff0) == 0x0040) { - for (i = 0; i < 8; i++) { - NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); - NV_WR32(par->PFB, 0x0244 + (i * 0x10), - par->FbMapSize - 1); - } - } else { - int regions = 12; - - if (((par->Chipset & 0xfff0) == 0x0090) || - ((par->Chipset & 0xfff0) == 0x01D0) || - ((par->Chipset & 0xfff0) == 0x0290) || - ((par->Chipset & 0xfff0) == 0x0390) || - ((par->Chipset & 0xfff0) == 0x03D0)) - regions = 15; - for(i = 0; i < regions; i++) { - NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0); - NV_WR32(par->PFB, 0x0604 + (i * 0x10), - par->FbMapSize - 1); - } - } - - if (par->Architecture >= NV_ARCH_40) { - NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010); - NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202); - NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011); - NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204); - NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012); - NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206); - NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013); - NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208); - NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014); - NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A); - NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015); - NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C); - NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016); - NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E); - NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017); - NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210); - NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000); - NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1); - NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002); - NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062); - NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200); - NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200); - NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043); - NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044); - NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000); - NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019); - NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C); - NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F); - NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200); - NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200); - NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A); - NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000); - NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077); - NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200); - NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200); - NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002); - NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF); - NV_WR32(par->PRAMIN, 0x084E * 4, - par->FbUsableSize | 0x00000002); - -#ifdef __BIG_ENDIAN - NV_WR32(par->PRAMIN, 0x080A * 4, - NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x0812 * 4, - NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x081A * 4, - NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x0822 * 4, - NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x082A * 4, - NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x0832 * 4, - NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x083A * 4, - NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x0842 * 4, - NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000); - NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000); - NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000); -#endif - } else { - NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010); - NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201); - NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011); - NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202); - NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012); - NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203); - NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013); - NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204); - NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014); - NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205); - NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015); - NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206); - NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016); - NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207); - NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017); - NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208); - NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000); - NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1); - NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002); - NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002); - if (par->Architecture >= NV_ARCH_10) - NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062); - else - NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042); - NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200); - NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043); - NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044); - NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002); - NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019); - NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C); - NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000); - if (par->WaitVSyncPossible) - NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F); - else - NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F); - NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200); - NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A); - NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002); - NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077); - NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200); - NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000); - NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002); - NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF); - NV_WR32(par->PRAMIN, 0x0826 * 4, - par->FbUsableSize | 0x00000002); - NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002); -#ifdef __BIG_ENDIAN - NV_WR32(par->PRAMIN, 0x0804 * 4, - NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x0808 * 4, - NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x080C * 4, - NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x0810 * 4, - NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x0814 * 4, - NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x0818 * 4, - NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x081C * 4, - NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x0820 * 4, - NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000); - NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001); - NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001); -#endif - } - if (par->Architecture < NV_ARCH_10) { - if ((par->Chipset & 0x0fff) == 0x0020) { - NV_WR32(par->PRAMIN, 0x0824 * 4, - NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000); - NV_WR32(par->PRAMIN, 0x0826 * 4, - NV_RD32(par->PRAMIN, - 0x0826 * 4) + par->FbAddress); - } - NV_WR32(par->PGRAPH, 0x0080, 0x000001FF); - NV_WR32(par->PGRAPH, 0x0080, 0x1230C000); - NV_WR32(par->PGRAPH, 0x0084, 0x72111101); - NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071); - NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31); - NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31); - NV_WR32(par->PGRAPH, 0x0140, 0x00000000); - NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF); - NV_WR32(par->PGRAPH, 0x0170, 0x10010100); - NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF); - NV_WR32(par->PGRAPH, 0x0720, 0x00000001); - NV_WR32(par->PGRAPH, 0x0810, 0x00000000); - NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF); - } else { - NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF); - NV_WR32(par->PGRAPH, 0x0080, 0x00000000); - - NV_WR32(par->PGRAPH, 0x0140, 0x00000000); - NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF); - NV_WR32(par->PGRAPH, 0x0144, 0x10010100); - NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF); - NV_WR32(par->PGRAPH, 0x0720, 0x00000001); - NV_WR32(par->PGRAPH, 0x0710, - NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00); - NV_WR32(par->PGRAPH, 0x0710, - NV_RD32(par->PGRAPH, 0x0710) | 0x00020100); - - if (par->Architecture == NV_ARCH_10) { - NV_WR32(par->PGRAPH, 0x0084, 0x00118700); - NV_WR32(par->PGRAPH, 0x0088, 0x24E00810); - NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030); - - for (i = 0; i < 32; i++) - NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0, - NV_RD32(&par->PFB[(0x0240 / 4) + i], - 0)); - - NV_WR32(par->PGRAPH, 0x640, 0); - NV_WR32(par->PGRAPH, 0x644, 0); - NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1); - NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1); - - NV_WR32(par->PGRAPH, 0x0810, 0x00000000); - NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF); - } else { - if (par->Architecture >= NV_ARCH_40) { - NV_WR32(par->PGRAPH, 0x0084, 0x401287c0); - NV_WR32(par->PGRAPH, 0x008C, 0x60de8051); - NV_WR32(par->PGRAPH, 0x0090, 0x00008000); - NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f); - NV_WR32(par->PGRAPH, 0x0bc4, - NV_RD32(par->PGRAPH, 0x0bc4) | - 0x00008000); - - j = NV_RD32(par->REGS, 0x1540) & 0xff; - - if (j) { - for (i = 0; !(j & 1); j >>= 1, i++); - NV_WR32(par->PGRAPH, 0x5000, i); - } - - if ((par->Chipset & 0xfff0) == 0x0040) { - NV_WR32(par->PGRAPH, 0x09b0, - 0x83280fff); - NV_WR32(par->PGRAPH, 0x09b4, - 0x000000a0); - } else { - NV_WR32(par->PGRAPH, 0x0820, - 0x83280eff); - NV_WR32(par->PGRAPH, 0x0824, - 0x000000a0); - } - - switch (par->Chipset & 0xfff0) { - case 0x0040: - case 0x0210: - NV_WR32(par->PGRAPH, 0x09b8, - 0x0078e366); - NV_WR32(par->PGRAPH, 0x09bc, - 0x0000014c); - NV_WR32(par->PFB, 0x033C, - NV_RD32(par->PFB, 0x33C) & - 0xffff7fff); - break; - case 0x00C0: - case 0x0120: - NV_WR32(par->PGRAPH, 0x0828, - 0x007596ff); - NV_WR32(par->PGRAPH, 0x082C, - 0x00000108); - break; - case 0x0160: - case 0x01D0: - case 0x0240: - case 0x03D0: - NV_WR32(par->PMC, 0x1700, - NV_RD32(par->PFB, 0x020C)); - NV_WR32(par->PMC, 0x1704, 0); - NV_WR32(par->PMC, 0x1708, 0); - NV_WR32(par->PMC, 0x170C, - NV_RD32(par->PFB, 0x020C)); - NV_WR32(par->PGRAPH, 0x0860, 0); - NV_WR32(par->PGRAPH, 0x0864, 0); - NV_WR32(par->PRAMDAC, 0x0608, - NV_RD32(par->PRAMDAC, - 0x0608) | 0x00100000); - break; - case 0x0140: - NV_WR32(par->PGRAPH, 0x0828, - 0x0072cb77); - NV_WR32(par->PGRAPH, 0x082C, - 0x00000108); - break; - case 0x0220: - NV_WR32(par->PGRAPH, 0x0860, 0); - NV_WR32(par->PGRAPH, 0x0864, 0); - NV_WR32(par->PRAMDAC, 0x0608, - NV_RD32(par->PRAMDAC, 0x0608) | - 0x00100000); - break; - case 0x0090: - case 0x0290: - case 0x0390: - NV_WR32(par->PRAMDAC, 0x0608, - NV_RD32(par->PRAMDAC, 0x0608) | - 0x00100000); - NV_WR32(par->PGRAPH, 0x0828, - 0x07830610); - NV_WR32(par->PGRAPH, 0x082C, - 0x0000016A); - break; - default: - break; - } - - NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800); - NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000); - NV_WR32(par->PGRAPH, 0x032C, 0x01000000); - NV_WR32(par->PGRAPH, 0x0220, 0x00001200); - } else if (par->Architecture == NV_ARCH_30) { - NV_WR32(par->PGRAPH, 0x0084, 0x40108700); - NV_WR32(par->PGRAPH, 0x0890, 0x00140000); - NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431); - NV_WR32(par->PGRAPH, 0x0090, 0x00008000); - NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36); - NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888); - NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f); - } else { - NV_WR32(par->PGRAPH, 0x0084, 0x00118700); - NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431); - NV_WR32(par->PGRAPH, 0x0090, 0x00000000); - NV_WR32(par->PGRAPH, 0x009C, 0x00000040); - - if ((par->Chipset & 0x0ff0) >= 0x0250) { - NV_WR32(par->PGRAPH, 0x0890, - 0x00080000); - NV_WR32(par->PGRAPH, 0x0610, - 0x304B1FB6); - NV_WR32(par->PGRAPH, 0x0B80, - 0x18B82880); - NV_WR32(par->PGRAPH, 0x0B84, - 0x44000000); - NV_WR32(par->PGRAPH, 0x0098, - 0x40000080); - NV_WR32(par->PGRAPH, 0x0B88, - 0x000000ff); - } else { - NV_WR32(par->PGRAPH, 0x0880, - 0x00080000); - NV_WR32(par->PGRAPH, 0x0094, - 0x00000005); - NV_WR32(par->PGRAPH, 0x0B80, - 0x45CAA208); - NV_WR32(par->PGRAPH, 0x0B84, - 0x24000000); - NV_WR32(par->PGRAPH, 0x0098, - 0x00000040); - NV_WR32(par->PGRAPH, 0x0750, - 0x00E00038); - NV_WR32(par->PGRAPH, 0x0754, - 0x00000030); - NV_WR32(par->PGRAPH, 0x0750, - 0x00E10038); - NV_WR32(par->PGRAPH, 0x0754, - 0x00000030); - } - } - - if ((par->Architecture < NV_ARCH_40) || - ((par->Chipset & 0xfff0) == 0x0040)) { - for (i = 0; i < 32; i++) { - NV_WR32(par->PGRAPH, 0x0900 + i*4, - NV_RD32(par->PFB, 0x0240 +i*4)); - NV_WR32(par->PGRAPH, 0x6900 + i*4, - NV_RD32(par->PFB, 0x0240 +i*4)); - } - } else { - if (((par->Chipset & 0xfff0) == 0x0090) || - ((par->Chipset & 0xfff0) == 0x01D0) || - ((par->Chipset & 0xfff0) == 0x0290) || - ((par->Chipset & 0xfff0) == 0x0390) || - ((par->Chipset & 0xfff0) == 0x03D0)) { - for (i = 0; i < 60; i++) { - NV_WR32(par->PGRAPH, - 0x0D00 + i*4, - NV_RD32(par->PFB, - 0x0600 + i*4)); - NV_WR32(par->PGRAPH, - 0x6900 + i*4, - NV_RD32(par->PFB, - 0x0600 + i*4)); - } - } else { - for (i = 0; i < 48; i++) { - NV_WR32(par->PGRAPH, - 0x0900 + i*4, - NV_RD32(par->PFB, - 0x0600 + i*4)); - if(((par->Chipset & 0xfff0) - != 0x0160) && - ((par->Chipset & 0xfff0) - != 0x0220) && - ((par->Chipset & 0xfff0) - != 0x240)) - NV_WR32(par->PGRAPH, - 0x6900 + i*4, - NV_RD32(par->PFB, - 0x0600 + i*4)); - } - } - } - - if (par->Architecture >= NV_ARCH_40) { - if ((par->Chipset & 0xfff0) == 0x0040) { - NV_WR32(par->PGRAPH, 0x09A4, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x09A8, - NV_RD32(par->PFB, 0x0204)); - NV_WR32(par->PGRAPH, 0x69A4, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x69A8, - NV_RD32(par->PFB, 0x0204)); - - NV_WR32(par->PGRAPH, 0x0820, 0); - NV_WR32(par->PGRAPH, 0x0824, 0); - NV_WR32(par->PGRAPH, 0x0864, - par->FbMapSize - 1); - NV_WR32(par->PGRAPH, 0x0868, - par->FbMapSize - 1); - } else { - if ((par->Chipset & 0xfff0) == 0x0090 || - (par->Chipset & 0xfff0) == 0x01D0 || - (par->Chipset & 0xfff0) == 0x0290 || - (par->Chipset & 0xfff0) == 0x0390) { - NV_WR32(par->PGRAPH, 0x0DF0, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x0DF4, - NV_RD32(par->PFB, 0x0204)); - } else { - NV_WR32(par->PGRAPH, 0x09F0, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x09F4, - NV_RD32(par->PFB, 0x0204)); - } - NV_WR32(par->PGRAPH, 0x69F0, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x69F4, - NV_RD32(par->PFB, 0x0204)); - - NV_WR32(par->PGRAPH, 0x0840, 0); - NV_WR32(par->PGRAPH, 0x0844, 0); - NV_WR32(par->PGRAPH, 0x08a0, - par->FbMapSize - 1); - NV_WR32(par->PGRAPH, 0x08a4, - par->FbMapSize - 1); - } - } else { - NV_WR32(par->PGRAPH, 0x09A4, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x09A8, - NV_RD32(par->PFB, 0x0204)); - NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000); - NV_WR32(par->PGRAPH, 0x0754, - NV_RD32(par->PFB, 0x0200)); - NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004); - NV_WR32(par->PGRAPH, 0x0754, - NV_RD32(par->PFB, 0x0204)); - - NV_WR32(par->PGRAPH, 0x0820, 0); - NV_WR32(par->PGRAPH, 0x0824, 0); - NV_WR32(par->PGRAPH, 0x0864, - par->FbMapSize - 1); - NV_WR32(par->PGRAPH, 0x0868, - par->FbMapSize - 1); - } - NV_WR32(par->PGRAPH, 0x0B20, 0x00000000); - NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF); - } - } - NV_WR32(par->PGRAPH, 0x053C, 0); - NV_WR32(par->PGRAPH, 0x0540, 0); - NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF); - NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF); - - NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001); - NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000); - if (par->Architecture >= NV_ARCH_40) - NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000); - else - NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100); - NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000); - if (par->Architecture >= NV_ARCH_40) - NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213); - else - NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209); - NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100); - NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110); - NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112); - NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF); - NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF); - NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF); - NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001); - NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000); - NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000); -#ifdef __BIG_ENDIAN - NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078); -#else - NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078); -#endif - NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001); - NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001); - NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001); - NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001); - NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001); - - if (!state) { - par->CurrentState = NULL; - return; - } - - if (par->Architecture >= NV_ARCH_10) { - if (par->twoHeads) { - NV_WR32(par->PCRTC0, 0x0860, state->head); - NV_WR32(par->PCRTC0, 0x2860, state->head2); - } - NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) | - (1 << 25)); - - NV_WR32(par->PMC, 0x8704, 1); - NV_WR32(par->PMC, 0x8140, 0); - NV_WR32(par->PMC, 0x8920, 0); - NV_WR32(par->PMC, 0x8924, 0); - NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1); - NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1); - NV_WR32(par->PMC, 0x1588, 0); - - NV_WR32(par->PCRTC, 0x0810, state->cursorConfig); - NV_WR32(par->PCRTC, 0x0830, state->displayV - 3); - NV_WR32(par->PCRTC, 0x0834, state->displayV - 1); - - if (par->FlatPanel) { - if ((par->Chipset & 0x0ff0) == 0x0110) { - NV_WR32(par->PRAMDAC, 0x0528, state->dither); - } else if (par->twoHeads) { - NV_WR32(par->PRAMDAC, 0x083C, state->dither); - } - - VGA_WR08(par->PCIO, 0x03D4, 0x53); - VGA_WR08(par->PCIO, 0x03D5, state->timingH); - VGA_WR08(par->PCIO, 0x03D4, 0x54); - VGA_WR08(par->PCIO, 0x03D5, state->timingV); - VGA_WR08(par->PCIO, 0x03D4, 0x21); - VGA_WR08(par->PCIO, 0x03D5, 0xfa); - } - - VGA_WR08(par->PCIO, 0x03D4, 0x41); - VGA_WR08(par->PCIO, 0x03D5, state->extra); - } - - VGA_WR08(par->PCIO, 0x03D4, 0x19); - VGA_WR08(par->PCIO, 0x03D5, state->repaint0); - VGA_WR08(par->PCIO, 0x03D4, 0x1A); - VGA_WR08(par->PCIO, 0x03D5, state->repaint1); - VGA_WR08(par->PCIO, 0x03D4, 0x25); - VGA_WR08(par->PCIO, 0x03D5, state->screen); - VGA_WR08(par->PCIO, 0x03D4, 0x28); - VGA_WR08(par->PCIO, 0x03D5, state->pixel); - VGA_WR08(par->PCIO, 0x03D4, 0x2D); - VGA_WR08(par->PCIO, 0x03D5, state->horiz); - VGA_WR08(par->PCIO, 0x03D4, 0x1C); - VGA_WR08(par->PCIO, 0x03D5, state->fifo); - VGA_WR08(par->PCIO, 0x03D4, 0x1B); - VGA_WR08(par->PCIO, 0x03D5, state->arbitration0); - VGA_WR08(par->PCIO, 0x03D4, 0x20); - VGA_WR08(par->PCIO, 0x03D5, state->arbitration1); - - if(par->Architecture >= NV_ARCH_30) { - VGA_WR08(par->PCIO, 0x03D4, 0x47); - VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8); - } - - VGA_WR08(par->PCIO, 0x03D4, 0x30); - VGA_WR08(par->PCIO, 0x03D5, state->cursor0); - VGA_WR08(par->PCIO, 0x03D4, 0x31); - VGA_WR08(par->PCIO, 0x03D5, state->cursor1); - VGA_WR08(par->PCIO, 0x03D4, 0x2F); - VGA_WR08(par->PCIO, 0x03D5, state->cursor2); - VGA_WR08(par->PCIO, 0x03D4, 0x39); - VGA_WR08(par->PCIO, 0x03D5, state->interlace); - - if (!par->FlatPanel) { - if (par->Architecture >= NV_ARCH_40) - NV_WR32(par->PRAMDAC0, 0x0580, state->control); - - NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel); - NV_WR32(par->PRAMDAC0, 0x0508, state->vpll); - if (par->twoHeads) - NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2); - if (par->twoStagePLL) { - NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB); - NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B); - } - } else { - NV_WR32(par->PRAMDAC, 0x0848, state->scale); - NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync + - par->PanelTweak); - } - - NV_WR32(par->PRAMDAC, 0x0600, state->general); - - NV_WR32(par->PCRTC, 0x0140, 0); - NV_WR32(par->PCRTC, 0x0100, 1); - - par->CurrentState = state; -} - -void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) { - VGA_WR08(par->PCIO, 0x03D4, 0x19); - state->repaint0 = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x1A); - state->repaint1 = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x25); - state->screen = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x28); - state->pixel = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x2D); - state->horiz = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x1C); - state->fifo = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x1B); - state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x20); - state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5); - - if(par->Architecture >= NV_ARCH_30) { - VGA_WR08(par->PCIO, 0x03D4, 0x47); - state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8; - } - - VGA_WR08(par->PCIO, 0x03D4, 0x30); - state->cursor0 = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x31); - state->cursor1 = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x2F); - state->cursor2 = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x39); - state->interlace = VGA_RD08(par->PCIO, 0x03D5); - state->vpll = NV_RD32(par->PRAMDAC0, 0x0508); - if (par->twoHeads) - state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); - if (par->twoStagePLL) { - state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578); - state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); - } - state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C); - state->general = NV_RD32(par->PRAMDAC, 0x0600); - state->scale = NV_RD32(par->PRAMDAC, 0x0848); - state->config = NV_RD32(par->PFB, 0x0200); - - if (par->Architecture >= NV_ARCH_40 && !par->FlatPanel) - state->control = NV_RD32(par->PRAMDAC0, 0x0580); - - if (par->Architecture >= NV_ARCH_10) { - if (par->twoHeads) { - state->head = NV_RD32(par->PCRTC0, 0x0860); - state->head2 = NV_RD32(par->PCRTC0, 0x2860); - VGA_WR08(par->PCIO, 0x03D4, 0x44); - state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5); - } - VGA_WR08(par->PCIO, 0x03D4, 0x41); - state->extra = VGA_RD08(par->PCIO, 0x03D5); - state->cursorConfig = NV_RD32(par->PCRTC, 0x0810); - - if ((par->Chipset & 0x0ff0) == 0x0110) { - state->dither = NV_RD32(par->PRAMDAC, 0x0528); - } else if (par->twoHeads) { - state->dither = NV_RD32(par->PRAMDAC, 0x083C); - } - - if (par->FlatPanel) { - VGA_WR08(par->PCIO, 0x03D4, 0x53); - state->timingH = VGA_RD08(par->PCIO, 0x03D5); - VGA_WR08(par->PCIO, 0x03D4, 0x54); - state->timingV = VGA_RD08(par->PCIO, 0x03D5); - } - } -} - -void NVSetStartAddress(struct nvidia_par *par, u32 start) -{ - NV_WR32(par->PCRTC, 0x800, start); -} diff --git a/drivers/video/fbdev/nvidia/nv_i2c.c b/drivers/video/fbdev/nvidia/nv_i2c.c deleted file mode 100644 index d7994a173245..000000000000 --- a/drivers/video/fbdev/nvidia/nv_i2c.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c - * - * Copyright 2004 Antonino A. Daplas <adaplas @pol.net> - * - * Based on rivafb-i2c.c - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/gfp.h> -#include <linux/pci.h> -#include <linux/fb.h> - -#include <asm/io.h> - -#include "nv_type.h" -#include "nv_local.h" -#include "nv_proto.h" - -#include "../edid.h" - -static void nvidia_gpio_setscl(void *data, int state) -{ - struct nvidia_i2c_chan *chan = data; - struct nvidia_par *par = chan->par; - u32 val; - - val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; - - if (state) - val |= 0x20; - else - val &= ~0x20; - - NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); -} - -static void nvidia_gpio_setsda(void *data, int state) -{ - struct nvidia_i2c_chan *chan = data; - struct nvidia_par *par = chan->par; - u32 val; - - val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; - - if (state) - val |= 0x10; - else - val &= ~0x10; - - NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); -} - -static int nvidia_gpio_getscl(void *data) -{ - struct nvidia_i2c_chan *chan = data; - struct nvidia_par *par = chan->par; - u32 val = 0; - - if (NVReadCrtc(par, chan->ddc_base) & 0x04) - val = 1; - - return val; -} - -static int nvidia_gpio_getsda(void *data) -{ - struct nvidia_i2c_chan *chan = data; - struct nvidia_par *par = chan->par; - u32 val = 0; - - if (NVReadCrtc(par, chan->ddc_base) & 0x08) - val = 1; - - return val; -} - -static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name, - unsigned int i2c_class) -{ - int rc; - - strcpy(chan->adapter.name, name); - chan->adapter.owner = THIS_MODULE; - chan->adapter.class = i2c_class; - chan->adapter.algo_data = &chan->algo; - chan->adapter.dev.parent = &chan->par->pci_dev->dev; - chan->algo.setsda = nvidia_gpio_setsda; - chan->algo.setscl = nvidia_gpio_setscl; - chan->algo.getsda = nvidia_gpio_getsda; - chan->algo.getscl = nvidia_gpio_getscl; - chan->algo.udelay = 40; - chan->algo.timeout = msecs_to_jiffies(2); - chan->algo.data = chan; - - i2c_set_adapdata(&chan->adapter, chan); - - /* Raise SCL and SDA */ - nvidia_gpio_setsda(chan, 1); - nvidia_gpio_setscl(chan, 1); - udelay(20); - - rc = i2c_bit_add_bus(&chan->adapter); - if (rc == 0) - dev_dbg(&chan->par->pci_dev->dev, - "I2C bus %s registered.\n", name); - else { - dev_warn(&chan->par->pci_dev->dev, - "Failed to register I2C bus %s.\n", name); - chan->par = NULL; - } - - return rc; -} - -void nvidia_create_i2c_busses(struct nvidia_par *par) -{ - par->chan[0].par = par; - par->chan[1].par = par; - par->chan[2].par = par; - - par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e; - nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0", - (par->reverse_i2c) ? I2C_CLASS_HWMON : 0); - - par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36; - nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1", - (par->reverse_i2c) ? 0 : I2C_CLASS_HWMON); - - par->chan[2].ddc_base = 0x50; - nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0); -} - -void nvidia_delete_i2c_busses(struct nvidia_par *par) -{ - int i; - - for (i = 0; i < 3; i++) { - if (!par->chan[i].par) - continue; - i2c_del_adapter(&par->chan[i].adapter); - par->chan[i].par = NULL; - } -} - -int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid) -{ - struct nvidia_par *par = info->par; - u8 *edid = NULL; - - if (par->chan[conn - 1].par) - edid = fb_ddc_read(&par->chan[conn - 1].adapter); - - if (!edid && conn == 1) { - /* try to get from firmware */ - const u8 *e = fb_firmware_edid(info->device); - - if (e != NULL) - edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL); - } - - *out_edid = edid; - - return (edid) ? 0 : 1; -} diff --git a/drivers/video/fbdev/nvidia/nv_local.h b/drivers/video/fbdev/nvidia/nv_local.h deleted file mode 100644 index 68e508daa417..000000000000 --- a/drivers/video/fbdev/nvidia/nv_local.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************\ -|* *| -|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ - * XFree86 'nv' driver, this source code is provided under MIT-style licensing - * where the source code is provided "as is" without warranty of any kind. - * The only usage restriction is for the copyright notices to be retained - * whenever code is used. - * - * Antonino Daplas <adaplas@pol.net> 2005-03-11 - */ - -#ifndef __NV_LOCAL_H__ -#define __NV_LOCAL_H__ - -/* - * This file includes any environment or machine specific values to access the - * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files - * can stay generic in nature. - */ - -/* - * HW access macros. These assume memory-mapped I/O, and not normal I/O space. - */ -#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i))) -#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i))) -#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i))) -#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i))) -#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i))) -#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) - -/* VGA I/O is now always done through MMIO */ -#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i))) -#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i))) - -#define NVDmaNext(par, data) \ - NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data)) - -#define NVDmaStart(info, par, tag, size) { \ - if((par)->dmaFree <= (size)) \ - NVDmaWait(info, size); \ - NVDmaNext(par, ((size) << 18) | (tag)); \ - (par)->dmaFree -= ((size) + 1); \ -} - -#if defined(__i386__) -#define _NV_FENCE() outb(0, 0x3D0); -#else -#define _NV_FENCE() mb(); -#endif - -#define WRITE_PUT(par, data) { \ - _NV_FENCE() \ - NV_RD08((par)->FbStart, 0); \ - NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \ - mb(); \ -} - -#define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2) - -#ifdef __LITTLE_ENDIAN - -#include <linux/bitrev.h> - -#define reverse_order(l) \ -do { \ - u8 *a = (u8 *)(l); \ - a[0] = bitrev8(a[0]); \ - a[1] = bitrev8(a[1]); \ - a[2] = bitrev8(a[2]); \ - a[3] = bitrev8(a[3]); \ -} while(0) -#else -#define reverse_order(l) do { } while(0) -#endif /* __LITTLE_ENDIAN */ - -#endif /* __NV_LOCAL_H__ */ diff --git a/drivers/video/fbdev/nvidia/nv_of.c b/drivers/video/fbdev/nvidia/nv_of.c deleted file mode 100644 index 5f3e5179c25a..000000000000 --- a/drivers/video/fbdev/nvidia/nv_of.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/drivers/video/nvidia/nv_of.c - * - * Copyright 2004 Antonino A. Daplas <adaplas @pol.net> - * - * Based on rivafb-i2c.c - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/gfp.h> -#include <linux/pci.h> -#include <linux/fb.h> - -#include <asm/io.h> - -#include "nv_type.h" -#include "nv_local.h" -#include "nv_proto.h" - -#include "../edid.h" - -int nvidia_probe_of_connector(struct fb_info *info, int conn, u8 **out_edid) -{ - struct nvidia_par *par = info->par; - struct device_node *parent, *dp; - const unsigned char *pedid = NULL; - static char *propnames[] = { - "DFP,EDID", "LCD,EDID", "EDID", "EDID1", - "EDID,B", "EDID,A", NULL }; - int i; - - parent = pci_device_to_OF_node(par->pci_dev); - if (parent == NULL) - return -1; - if (par->twoHeads) { - const char *pname; - int len; - - for (dp = NULL; - (dp = of_get_next_child(parent, dp)) != NULL;) { - pname = of_get_property(dp, "name", NULL); - if (!pname) - continue; - len = strlen(pname); - if ((pname[len-1] == 'A' && conn == 1) || - (pname[len-1] == 'B' && conn == 2)) { - for (i = 0; propnames[i] != NULL; ++i) { - pedid = of_get_property(dp, - propnames[i], NULL); - if (pedid != NULL) - break; - } - of_node_put(dp); - break; - } - } - } - if (pedid == NULL) { - for (i = 0; propnames[i] != NULL; ++i) { - pedid = of_get_property(parent, propnames[i], NULL); - if (pedid != NULL) - break; - } - } - if (pedid) { - *out_edid = kmemdup(pedid, EDID_LENGTH, GFP_KERNEL); - if (*out_edid == NULL) - return -1; - printk(KERN_DEBUG "nvidiafb: Found OF EDID for head %d\n", conn); - return 0; - } - return -1; -} diff --git a/drivers/video/fbdev/nvidia/nv_proto.h b/drivers/video/fbdev/nvidia/nv_proto.h deleted file mode 100644 index fb9c5ebf2958..000000000000 --- a/drivers/video/fbdev/nvidia/nv_proto.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h,v 1.10 2003/07/31 20:24:29 mvojkovi Exp $ */ - -#ifndef __NV_PROTO_H__ -#define __NV_PROTO_H__ - -/* in nv_setup.c */ -int NVCommonSetup(struct fb_info *info); -void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value); -u8 NVReadCrtc(struct nvidia_par *par, u8 index); -void NVWriteGr(struct nvidia_par *par, u8 index, u8 value); -u8 NVReadGr(struct nvidia_par *par, u8 index); -void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value); -u8 NVReadSeq(struct nvidia_par *par, u8 index); -void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value); -u8 NVReadAttr(struct nvidia_par *par, u8 index); -void NVWriteMiscOut(struct nvidia_par *par, u8 value); -u8 NVReadMiscOut(struct nvidia_par *par); -void NVWriteDacMask(struct nvidia_par *par, u8 value); -void NVWriteDacReadAddr(struct nvidia_par *par, u8 value); -void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value); -void NVWriteDacData(struct nvidia_par *par, u8 value); -u8 NVReadDacData(struct nvidia_par *par); - -/* in nv_hw.c */ -void NVCalcStateExt(struct nvidia_par *par, struct _riva_hw_state *, - int, int, int, int, int, int); -void NVLoadStateExt(struct nvidia_par *par, struct _riva_hw_state *); -void NVUnloadStateExt(struct nvidia_par *par, struct _riva_hw_state *); -void NVSetStartAddress(struct nvidia_par *par, u32); -int NVShowHideCursor(struct nvidia_par *par, int); -void NVLockUnlock(struct nvidia_par *par, int); - -/* in nvidia-i2c.c */ -#ifdef CONFIG_FB_NVIDIA_I2C -void nvidia_create_i2c_busses(struct nvidia_par *par); -void nvidia_delete_i2c_busses(struct nvidia_par *par); -int nvidia_probe_i2c_connector(struct fb_info *info, int conn, - u8 ** out_edid); -#else -#define nvidia_create_i2c_busses(...) -#define nvidia_delete_i2c_busses(...) -#define nvidia_probe_i2c_connector(p, c, edid) (-1) -#endif - -int nvidia_probe_of_connector(struct fb_info *info, int conn, - u8 ** out_edid); - -/* in nv_accel.c */ -extern void NVResetGraphics(struct fb_info *info); -extern void nvidiafb_copyarea(struct fb_info *info, - const struct fb_copyarea *region); -extern void nvidiafb_fillrect(struct fb_info *info, - const struct fb_fillrect *rect); -extern void nvidiafb_imageblit(struct fb_info *info, - const struct fb_image *image); -extern int nvidiafb_sync(struct fb_info *info); - -/* in nv_backlight.h */ -#ifdef CONFIG_FB_NVIDIA_BACKLIGHT -extern void nvidia_bl_init(struct nvidia_par *par); -extern void nvidia_bl_exit(struct nvidia_par *par); -#else -static inline void nvidia_bl_init(struct nvidia_par *par) {} -static inline void nvidia_bl_exit(struct nvidia_par *par) {} -#endif - -#endif /* __NV_PROTO_H__ */ diff --git a/drivers/video/fbdev/nvidia/nv_setup.c b/drivers/video/fbdev/nvidia/nv_setup.c deleted file mode 100644 index 2fa68669613a..000000000000 --- a/drivers/video/fbdev/nvidia/nv_setup.c +++ /dev/null @@ -1,652 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ - * XFree86 'nv' driver, this source code is provided under MIT-style licensing - * where the source code is provided "as is" without warranty of any kind. - * The only usage restriction is for the copyright notices to be retained - * whenever code is used. - * - * Antonino Daplas <adaplas@pol.net> 2005-03-11 - */ - -#include <video/vga.h> -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/slab.h> -#include "nv_type.h" -#include "nv_local.h" -#include "nv_proto.h" -/* - * Override VGA I/O routines. - */ -void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) -{ - VGA_WR08(par->PCIO, par->IOBase + 0x04, index); - VGA_WR08(par->PCIO, par->IOBase + 0x05, value); -} -u8 NVReadCrtc(struct nvidia_par *par, u8 index) -{ - VGA_WR08(par->PCIO, par->IOBase + 0x04, index); - return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); -} -void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) -{ - VGA_WR08(par->PVIO, VGA_GFX_I, index); - VGA_WR08(par->PVIO, VGA_GFX_D, value); -} -u8 NVReadGr(struct nvidia_par *par, u8 index) -{ - VGA_WR08(par->PVIO, VGA_GFX_I, index); - return (VGA_RD08(par->PVIO, VGA_GFX_D)); -} -void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value) -{ - VGA_WR08(par->PVIO, VGA_SEQ_I, index); - VGA_WR08(par->PVIO, VGA_SEQ_D, value); -} -u8 NVReadSeq(struct nvidia_par *par, u8 index) -{ - VGA_WR08(par->PVIO, VGA_SEQ_I, index); - return (VGA_RD08(par->PVIO, VGA_SEQ_D)); -} -void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value) -{ - volatile u8 tmp; - - tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); - if (par->paletteEnabled) - index &= ~0x20; - else - index |= 0x20; - VGA_WR08(par->PCIO, VGA_ATT_IW, index); - VGA_WR08(par->PCIO, VGA_ATT_W, value); -} -u8 NVReadAttr(struct nvidia_par *par, u8 index) -{ - volatile u8 tmp; - - tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); - if (par->paletteEnabled) - index &= ~0x20; - else - index |= 0x20; - VGA_WR08(par->PCIO, VGA_ATT_IW, index); - return (VGA_RD08(par->PCIO, VGA_ATT_R)); -} -void NVWriteMiscOut(struct nvidia_par *par, u8 value) -{ - VGA_WR08(par->PVIO, VGA_MIS_W, value); -} -u8 NVReadMiscOut(struct nvidia_par *par) -{ - return (VGA_RD08(par->PVIO, VGA_MIS_R)); -} -void NVWriteDacMask(struct nvidia_par *par, u8 value) -{ - VGA_WR08(par->PDIO, VGA_PEL_MSK, value); -} -void NVWriteDacReadAddr(struct nvidia_par *par, u8 value) -{ - VGA_WR08(par->PDIO, VGA_PEL_IR, value); -} -void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value) -{ - VGA_WR08(par->PDIO, VGA_PEL_IW, value); -} -void NVWriteDacData(struct nvidia_par *par, u8 value) -{ - VGA_WR08(par->PDIO, VGA_PEL_D, value); -} -u8 NVReadDacData(struct nvidia_par *par) -{ - return (VGA_RD08(par->PDIO, VGA_PEL_D)); -} - -static int NVIsConnected(struct nvidia_par *par, int output) -{ - volatile u32 __iomem *PRAMDAC = par->PRAMDAC0; - u32 reg52C, reg608, dac0_reg608 = 0; - int present; - - if (output) { - dac0_reg608 = NV_RD32(PRAMDAC, 0x0608); - PRAMDAC += 0x800; - } - - reg52C = NV_RD32(PRAMDAC, 0x052C); - reg608 = NV_RD32(PRAMDAC, 0x0608); - - NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000); - - NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE); - msleep(1); - NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); - - NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140); - NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) | - 0x00001000); - - msleep(1); - - present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0; - - if (present) - printk("nvidiafb: CRTC%i analog found\n", output); - else - printk("nvidiafb: CRTC%i analog not found\n", output); - - if (output) - NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608); - - NV_WR32(PRAMDAC, 0x052C, reg52C); - NV_WR32(PRAMDAC, 0x0608, reg608); - - return present; -} - -static void NVSelectHeadRegisters(struct nvidia_par *par, int head) -{ - if (head) { - par->PCIO = par->PCIO0 + 0x2000; - par->PCRTC = par->PCRTC0 + 0x800; - par->PRAMDAC = par->PRAMDAC0 + 0x800; - par->PDIO = par->PDIO0 + 0x2000; - } else { - par->PCIO = par->PCIO0; - par->PCRTC = par->PCRTC0; - par->PRAMDAC = par->PRAMDAC0; - par->PDIO = par->PDIO0; - } -} - -static void nv4GetConfig(struct nvidia_par *par) -{ - if (NV_RD32(par->PFB, 0x0000) & 0x00000100) { - par->RamAmountKBytes = - ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 + - 1024 * 2; - } else { - switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) { - case 0: - par->RamAmountKBytes = 1024 * 32; - break; - case 1: - par->RamAmountKBytes = 1024 * 4; - break; - case 2: - par->RamAmountKBytes = 1024 * 8; - break; - case 3: - default: - par->RamAmountKBytes = 1024 * 16; - break; - } - } - par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? - 14318 : 13500; - par->CURSOR = &par->PRAMIN[0x1E00]; - par->MinVClockFreqKHz = 12000; - par->MaxVClockFreqKHz = 350000; -} - -static void nv10GetConfig(struct nvidia_par *par) -{ - struct pci_dev *dev; - u32 implementation = par->Chipset & 0x0ff0; - -#ifdef __BIG_ENDIAN - /* turn on big endian register access */ - if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { - NV_WR32(par->PMC, 0x0004, 0x01000001); - mb(); - } -#endif - - dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus), - 0, 1); - if ((par->Chipset & 0xffff) == 0x01a0) { - u32 amt; - - pci_read_config_dword(dev, 0x7c, &amt); - par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; - } else if ((par->Chipset & 0xffff) == 0x01f0) { - u32 amt; - - pci_read_config_dword(dev, 0x84, &amt); - par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; - } else { - par->RamAmountKBytes = - (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; - } - pci_dev_put(dev); - - par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? - 14318 : 13500; - - if (par->twoHeads && (implementation != 0x0110)) { - if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22)) - par->CrystalFreqKHz = 27000; - } - - par->CURSOR = NULL; /* can't set this here */ - par->MinVClockFreqKHz = 12000; - par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000; -} - -int NVCommonSetup(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - struct fb_var_screeninfo *var; - u16 implementation = par->Chipset & 0x0ff0; - u8 *edidA = NULL, *edidB = NULL; - struct fb_monspecs *monitorA, *monitorB; - struct fb_monspecs *monA = NULL, *monB = NULL; - int mobile = 0; - int tvA = 0; - int tvB = 0; - int FlatPanel = -1; /* really means the CRTC is slaved */ - int Television = 0; - int err = 0; - - var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL); - monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); - monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); - - if (!var || !monitorA || !monitorB) { - err = -ENOMEM; - goto done; - } - - par->PRAMIN = par->REGS + (0x00710000 / 4); - par->PCRTC0 = par->REGS + (0x00600000 / 4); - par->PRAMDAC0 = par->REGS + (0x00680000 / 4); - par->PFB = par->REGS + (0x00100000 / 4); - par->PFIFO = par->REGS + (0x00002000 / 4); - par->PGRAPH = par->REGS + (0x00400000 / 4); - par->PEXTDEV = par->REGS + (0x00101000 / 4); - par->PTIMER = par->REGS + (0x00009000 / 4); - par->PMC = par->REGS + (0x00000000 / 4); - par->FIFO = par->REGS + (0x00800000 / 4); - - /* 8 bit registers */ - par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000; - par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000; - par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000; - - par->twoHeads = (par->Architecture >= NV_ARCH_10) && - (implementation != 0x0100) && - (implementation != 0x0150) && - (implementation != 0x01A0) && (implementation != 0x0200); - - par->fpScaler = (par->FpScale && par->twoHeads && - (implementation != 0x0110)); - - par->twoStagePLL = (implementation == 0x0310) || - (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40); - - par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) && - (implementation != 0x0100); - - par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020); - - /* look for known laptop chips */ - switch (par->Chipset & 0xffff) { - case 0x0112: - case 0x0174: - case 0x0175: - case 0x0176: - case 0x0177: - case 0x0179: - case 0x017C: - case 0x017D: - case 0x0186: - case 0x0187: - case 0x018D: - case 0x01D7: - case 0x0228: - case 0x0286: - case 0x028C: - case 0x0316: - case 0x0317: - case 0x031A: - case 0x031B: - case 0x031C: - case 0x031D: - case 0x031E: - case 0x031F: - case 0x0324: - case 0x0325: - case 0x0328: - case 0x0329: - case 0x032C: - case 0x032D: - case 0x0347: - case 0x0348: - case 0x0349: - case 0x034B: - case 0x034C: - case 0x0160: - case 0x0166: - case 0x0169: - case 0x016B: - case 0x016C: - case 0x016D: - case 0x00C8: - case 0x00CC: - case 0x0144: - case 0x0146: - case 0x0147: - case 0x0148: - case 0x0098: - case 0x0099: - mobile = 1; - break; - default: - break; - } - - if (par->Architecture == NV_ARCH_04) - nv4GetConfig(par); - else - nv10GetConfig(par); - - NVSelectHeadRegisters(par, 0); - - NVLockUnlock(par, 0); - - par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0; - - par->Television = 0; - - nvidia_create_i2c_busses(par); - if (!par->twoHeads) { - par->CRTCnumber = 0; - if (nvidia_probe_i2c_connector(info, 1, &edidA)) - nvidia_probe_of_connector(info, 1, &edidA); - if (edidA && !fb_parse_edid(edidA, var)) { - printk("nvidiafb: EDID found from BUS1\n"); - monA = monitorA; - fb_edid_to_monspecs(edidA, monA); - FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0; - - /* NV4 doesn't support FlatPanels */ - if ((par->Chipset & 0x0fff) <= 0x0020) - FlatPanel = 0; - } else { - VGA_WR08(par->PCIO, 0x03D4, 0x28); - if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) { - VGA_WR08(par->PCIO, 0x03D4, 0x33); - if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01)) - Television = 1; - FlatPanel = 1; - } else { - FlatPanel = 0; - } - printk("nvidiafb: HW is currently programmed for %s\n", - FlatPanel ? (Television ? "TV" : "DFP") : - "CRT"); - } - - if (par->FlatPanel == -1) { - par->FlatPanel = FlatPanel; - par->Television = Television; - } else { - printk("nvidiafb: Forcing display type to %s as " - "specified\n", par->FlatPanel ? "DFP" : "CRT"); - } - } else { - u8 outputAfromCRTC, outputBfromCRTC; - int CRTCnumber = -1; - u8 slaved_on_A, slaved_on_B; - int analog_on_A, analog_on_B; - u32 oldhead; - u8 cr44; - - if (implementation != 0x0110) { - if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100) - outputAfromCRTC = 1; - else - outputAfromCRTC = 0; - if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100) - outputBfromCRTC = 1; - else - outputBfromCRTC = 0; - analog_on_A = NVIsConnected(par, 0); - analog_on_B = NVIsConnected(par, 1); - } else { - outputAfromCRTC = 0; - outputBfromCRTC = 1; - analog_on_A = 0; - analog_on_B = 0; - } - - VGA_WR08(par->PCIO, 0x03D4, 0x44); - cr44 = VGA_RD08(par->PCIO, 0x03D5); - - VGA_WR08(par->PCIO, 0x03D5, 3); - NVSelectHeadRegisters(par, 1); - NVLockUnlock(par, 0); - - VGA_WR08(par->PCIO, 0x03D4, 0x28); - slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80; - if (slaved_on_B) { - VGA_WR08(par->PCIO, 0x03D4, 0x33); - tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); - } - - VGA_WR08(par->PCIO, 0x03D4, 0x44); - VGA_WR08(par->PCIO, 0x03D5, 0); - NVSelectHeadRegisters(par, 0); - NVLockUnlock(par, 0); - - VGA_WR08(par->PCIO, 0x03D4, 0x28); - slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80; - if (slaved_on_A) { - VGA_WR08(par->PCIO, 0x03D4, 0x33); - tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); - } - - oldhead = NV_RD32(par->PCRTC0, 0x00000860); - NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010); - - if (nvidia_probe_i2c_connector(info, 1, &edidA)) - nvidia_probe_of_connector(info, 1, &edidA); - if (edidA && !fb_parse_edid(edidA, var)) { - printk("nvidiafb: EDID found from BUS1\n"); - monA = monitorA; - fb_edid_to_monspecs(edidA, monA); - } - - if (nvidia_probe_i2c_connector(info, 2, &edidB)) - nvidia_probe_of_connector(info, 2, &edidB); - if (edidB && !fb_parse_edid(edidB, var)) { - printk("nvidiafb: EDID found from BUS2\n"); - monB = monitorB; - fb_edid_to_monspecs(edidB, monB); - } - - if (slaved_on_A && !tvA) { - CRTCnumber = 0; - FlatPanel = 1; - printk("nvidiafb: CRTC 0 is currently programmed for " - "DFP\n"); - } else if (slaved_on_B && !tvB) { - CRTCnumber = 1; - FlatPanel = 1; - printk("nvidiafb: CRTC 1 is currently programmed " - "for DFP\n"); - } else if (analog_on_A) { - CRTCnumber = outputAfromCRTC; - FlatPanel = 0; - printk("nvidiafb: CRTC %i appears to have a " - "CRT attached\n", CRTCnumber); - } else if (analog_on_B) { - CRTCnumber = outputBfromCRTC; - FlatPanel = 0; - printk("nvidiafb: CRTC %i appears to have a " - "CRT attached\n", CRTCnumber); - } else if (slaved_on_A) { - CRTCnumber = 0; - FlatPanel = 1; - Television = 1; - printk("nvidiafb: CRTC 0 is currently programmed " - "for TV\n"); - } else if (slaved_on_B) { - CRTCnumber = 1; - FlatPanel = 1; - Television = 1; - printk("nvidiafb: CRTC 1 is currently programmed for " - "TV\n"); - } else if (monA) { - FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0; - } else if (monB) { - FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0; - } - - if (par->FlatPanel == -1) { - if (FlatPanel != -1) { - par->FlatPanel = FlatPanel; - par->Television = Television; - } else { - printk("nvidiafb: Unable to detect display " - "type...\n"); - if (mobile) { - printk("...On a laptop, assuming " - "DFP\n"); - par->FlatPanel = 1; - } else { - printk("...Using default of CRT\n"); - par->FlatPanel = 0; - } - } - } else { - printk("nvidiafb: Forcing display type to %s as " - "specified\n", par->FlatPanel ? "DFP" : "CRT"); - } - - if (par->CRTCnumber == -1) { - if (CRTCnumber != -1) - par->CRTCnumber = CRTCnumber; - else { - printk("nvidiafb: Unable to detect which " - "CRTCNumber...\n"); - if (par->FlatPanel) - par->CRTCnumber = 1; - else - par->CRTCnumber = 0; - printk("...Defaulting to CRTCNumber %i\n", - par->CRTCnumber); - } - } else { - printk("nvidiafb: Forcing CRTCNumber %i as " - "specified\n", par->CRTCnumber); - } - - if (monA) { - if (((monA->input & FB_DISP_DDI) && - par->FlatPanel) || - ((!(monA->input & FB_DISP_DDI)) && - !par->FlatPanel)) { - if (monB) { - fb_destroy_modedb(monB->modedb); - monB = NULL; - } - } else { - fb_destroy_modedb(monA->modedb); - monA = NULL; - } - } - - if (monB) { - if (((monB->input & FB_DISP_DDI) && - !par->FlatPanel) || - ((!(monB->input & FB_DISP_DDI)) && - par->FlatPanel)) { - fb_destroy_modedb(monB->modedb); - monB = NULL; - } else - monA = monB; - } - - if (implementation == 0x0110) - cr44 = par->CRTCnumber * 0x3; - - NV_WR32(par->PCRTC0, 0x00000860, oldhead); - - VGA_WR08(par->PCIO, 0x03D4, 0x44); - VGA_WR08(par->PCIO, 0x03D5, cr44); - NVSelectHeadRegisters(par, par->CRTCnumber); - } - - printk("nvidiafb: Using %s on CRTC %i\n", - par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT", - par->CRTCnumber); - - if (par->FlatPanel && !par->Television) { - par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1; - par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1; - par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033; - - printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight); - } - - if (monA) - info->monspecs = *monA; - - if (!par->FlatPanel || !par->twoHeads) - par->FPDither = 0; - - par->LVDS = 0; - if (par->FlatPanel && par->twoHeads) { - NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004); - if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1) - par->LVDS = 1; - printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); - } - - kfree(edidA); - kfree(edidB); -done: - kfree(var); - kfree(monitorA); - kfree(monitorB); - return err; -} diff --git a/drivers/video/fbdev/nvidia/nv_type.h b/drivers/video/fbdev/nvidia/nv_type.h deleted file mode 100644 index d7a1d4363d5f..000000000000 --- a/drivers/video/fbdev/nvidia/nv_type.h +++ /dev/null @@ -1,176 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __NV_TYPE_H__ -#define __NV_TYPE_H__ - -#include <linux/fb.h> -#include <linux/types.h> -#include <linux/i2c.h> -#include <linux/i2c-algo-bit.h> -#include <video/vga.h> - -#define NV_ARCH_04 0x04 -#define NV_ARCH_10 0x10 -#define NV_ARCH_20 0x20 -#define NV_ARCH_30 0x30 -#define NV_ARCH_40 0x40 - -#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) -#define MASKEXPAND(mask) BITMASK(1?mask,0?mask) -#define SetBF(mask,value) ((value) << (0?mask)) -#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) -#define SetBitField(value,from,to) SetBF(to, GetBF(value,from)) -#define SetBit(n) (1<<(n)) -#define Set8Bits(value) ((value)&0xff) - -#define V_DBLSCAN 1 - -typedef struct { - int bitsPerPixel; - int depth; - int displayWidth; - int weight; -} NVFBLayout; - -#define NUM_SEQ_REGS 0x05 -#define NUM_CRT_REGS 0x41 -#define NUM_GRC_REGS 0x09 -#define NUM_ATC_REGS 0x15 - -struct nvidia_par; - -struct nvidia_i2c_chan { - struct nvidia_par *par; - unsigned long ddc_base; - struct i2c_adapter adapter; - struct i2c_algo_bit_data algo; -}; - -typedef struct _riva_hw_state { - u8 attr[NUM_ATC_REGS]; - u8 crtc[NUM_CRT_REGS]; - u8 gra[NUM_GRC_REGS]; - u8 seq[NUM_SEQ_REGS]; - u8 misc_output; - u32 bpp; - u32 width; - u32 height; - u32 interlace; - u32 repaint0; - u32 repaint1; - u32 screen; - u32 scale; - u32 dither; - u32 extra; - u32 fifo; - u32 pixel; - u32 horiz; - u32 arbitration0; - u32 arbitration1; - u32 pll; - u32 pllB; - u32 vpll; - u32 vpll2; - u32 vpllB; - u32 vpll2B; - u32 pllsel; - u32 general; - u32 crtcOwner; - u32 head; - u32 head2; - u32 config; - u32 cursorConfig; - u32 cursor0; - u32 cursor1; - u32 cursor2; - u32 timingH; - u32 timingV; - u32 displayV; - u32 crtcSync; - u32 control; -} RIVA_HW_STATE; - -struct riva_regs { - RIVA_HW_STATE ext; -}; - -struct nvidia_par { - RIVA_HW_STATE SavedReg; - RIVA_HW_STATE ModeReg; - RIVA_HW_STATE initial_state; - RIVA_HW_STATE *CurrentState; - struct vgastate vgastate; - u32 pseudo_palette[16]; - struct pci_dev *pci_dev; - u32 Architecture; - u32 CursorStart; - int Chipset; - unsigned long FbAddress; - u8 __iomem *FbStart; - u32 FbMapSize; - u32 FbUsableSize; - u32 ScratchBufferSize; - u32 ScratchBufferStart; - int FpScale; - u32 MinVClockFreqKHz; - u32 MaxVClockFreqKHz; - u32 CrystalFreqKHz; - u32 RamAmountKBytes; - u32 IOBase; - NVFBLayout CurrentLayout; - int cursor_reset; - int lockup; - int videoKey; - int FlatPanel; - int FPDither; - int Television; - int CRTCnumber; - int alphaCursor; - int twoHeads; - int twoStagePLL; - int fpScaler; - int fpWidth; - int fpHeight; - int PanelTweak; - int paneltweak; - int LVDS; - int pm_state; - int reverse_i2c; - u32 crtcSync_read; - u32 fpSyncs; - u32 dmaPut; - u32 dmaCurrent; - u32 dmaFree; - u32 dmaMax; - u32 __iomem *dmaBase; - u32 currentRop; - int WaitVSyncPossible; - int BlendingPossible; - u32 paletteEnabled; - u32 forceCRTC; - u32 open_count; - u8 DDCBase; - int wc_cookie; - struct nvidia_i2c_chan chan[3]; - - volatile u32 __iomem *REGS; - volatile u32 __iomem *PCRTC0; - volatile u32 __iomem *PCRTC; - volatile u32 __iomem *PRAMDAC0; - volatile u32 __iomem *PFB; - volatile u32 __iomem *PFIFO; - volatile u32 __iomem *PGRAPH; - volatile u32 __iomem *PEXTDEV; - volatile u32 __iomem *PTIMER; - volatile u32 __iomem *PMC; - volatile u32 __iomem *PRAMIN; - volatile u32 __iomem *FIFO; - volatile u32 __iomem *CURSOR; - volatile u8 __iomem *PCIO0; - volatile u8 __iomem *PCIO; - volatile u8 __iomem *PVIO; - volatile u8 __iomem *PDIO0; - volatile u8 __iomem *PDIO; - volatile u32 __iomem *PRAMDAC; -}; - -#endif /* __NV_TYPE_H__ */ diff --git a/drivers/video/fbdev/nvidia/nvidia.c b/drivers/video/fbdev/nvidia/nvidia.c deleted file mode 100644 index a372a183c1f0..000000000000 --- a/drivers/video/fbdev/nvidia/nvidia.c +++ /dev/null @@ -1,1581 +0,0 @@ -/* - * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver - * - * Copyright 2004 Antonino Daplas <adaplas@pol.net> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/console.h> -#include <linux/backlight.h> -#ifdef CONFIG_BOOTX_TEXT -#include <asm/btext.h> -#endif - -#include "nv_local.h" -#include "nv_type.h" -#include "nv_proto.h" -#include "nv_dma.h" - -#ifdef CONFIG_FB_NVIDIA_DEBUG -#define NVTRACE printk -#else -#define NVTRACE if (0) printk -#endif - -#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) -#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) - -#ifdef CONFIG_FB_NVIDIA_DEBUG -#define assert(expr) \ - if (!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n",\ - #expr,__FILE__,__func__,__LINE__); \ - BUG(); \ - } -#else -#define assert(expr) -#endif - -#define PFX "nvidiafb: " - -/* HW cursor parameters */ -#define MAX_CURS 32 - -static const struct pci_device_id nvidiafb_pci_tbl[] = { - {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0}, - { 0, } -}; -MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl); - -/* command line data, set in nvidiafb_setup() */ -static int flatpanel = -1; /* Autodetect later */ -static int fpdither = -1; -static int forceCRTC = -1; -static int hwcur = 0; -static int noaccel = 0; -static int noscale = 0; -static int paneltweak = 0; -static int vram = 0; -static int bpp = 8; -static int reverse_i2c; -static bool nomtrr = false; -static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); - -static char *mode_option = NULL; - -static struct fb_fix_screeninfo nvidiafb_fix = { - .type = FB_TYPE_PACKED_PIXELS, - .xpanstep = 8, - .ypanstep = 1, -}; - -static struct fb_var_screeninfo nvidiafb_default_var = { - .xres = 640, - .yres = 480, - .xres_virtual = 640, - .yres_virtual = 480, - .bits_per_pixel = 8, - .red = {0, 8, 0}, - .green = {0, 8, 0}, - .blue = {0, 8, 0}, - .transp = {0, 0, 0}, - .activate = FB_ACTIVATE_NOW, - .height = -1, - .width = -1, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .vmode = FB_VMODE_NONINTERLACED -}; - -static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, - u16 bg, u16 fg, u32 w, u32 h) -{ - u32 *data = (u32 *) data8; - int i, j, k = 0; - u32 b, tmp; - - w = (w + 1) & ~1; - - for (i = 0; i < h; i++) { - b = *data++; - reverse_order(&b); - - for (j = 0; j < w / 2; j++) { - tmp = 0; -#if defined (__BIG_ENDIAN) - tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; - b <<= 1; - tmp |= (b & (1 << 31)) ? fg : bg; - b <<= 1; -#else - tmp = (b & 1) ? fg : bg; - b >>= 1; - tmp |= (b & 1) ? fg << 16 : bg << 16; - b >>= 1; -#endif - NV_WR32(&par->CURSOR[k++], 0, tmp); - } - k += (MAX_CURS - w) / 2; - } -} - -static void nvidia_write_clut(struct nvidia_par *par, - u8 regnum, u8 red, u8 green, u8 blue) -{ - NVWriteDacMask(par, 0xff); - NVWriteDacWriteAddr(par, regnum); - NVWriteDacData(par, red); - NVWriteDacData(par, green); - NVWriteDacData(par, blue); -} - -static void nvidia_read_clut(struct nvidia_par *par, - u8 regnum, u8 * red, u8 * green, u8 * blue) -{ - NVWriteDacMask(par, 0xff); - NVWriteDacReadAddr(par, regnum); - *red = NVReadDacData(par); - *green = NVReadDacData(par); - *blue = NVReadDacData(par); -} - -static int nvidia_panel_tweak(struct nvidia_par *par, - struct _riva_hw_state *state) -{ - int tweak = 0; - - if (par->paneltweak) { - tweak = par->paneltweak; - } else { - /* Begin flat panel hacks. - * This is unfortunate, but some chips need this register - * tweaked or else you get artifacts where adjacent pixels are - * swapped. There are no hard rules for what to set here so all - * we can do is experiment and apply hacks. - */ - if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { - /* At least one NV34 laptop needs this workaround. */ - tweak = -1; - } - - if ((par->Chipset & 0xfff0) == 0x0310) - tweak = 1; - /* end flat panel hacks */ - } - - return tweak; -} - -static void nvidia_screen_off(struct nvidia_par *par, int on) -{ - unsigned char tmp; - - if (on) { - /* - * Turn off screen and disable sequencer. - */ - tmp = NVReadSeq(par, 0x01); - - NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ - NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ - } else { - /* - * Reenable sequencer, then turn on screen. - */ - - tmp = NVReadSeq(par, 0x01); - - NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ - NVWriteSeq(par, 0x00, 0x03); /* End Reset */ - } -} - -static void nvidia_save_vga(struct nvidia_par *par, - struct _riva_hw_state *state) -{ - int i; - - NVTRACE_ENTER(); - NVLockUnlock(par, 0); - - NVUnloadStateExt(par, state); - - state->misc_output = NVReadMiscOut(par); - - for (i = 0; i < NUM_CRT_REGS; i++) - state->crtc[i] = NVReadCrtc(par, i); - - for (i = 0; i < NUM_ATC_REGS; i++) - state->attr[i] = NVReadAttr(par, i); - - for (i = 0; i < NUM_GRC_REGS; i++) - state->gra[i] = NVReadGr(par, i); - - for (i = 0; i < NUM_SEQ_REGS; i++) - state->seq[i] = NVReadSeq(par, i); - NVTRACE_LEAVE(); -} - -#undef DUMP_REG - -static void nvidia_write_regs(struct nvidia_par *par, - struct _riva_hw_state *state) -{ - int i; - - NVTRACE_ENTER(); - - NVLoadStateExt(par, state); - - NVWriteMiscOut(par, state->misc_output); - - for (i = 1; i < NUM_SEQ_REGS; i++) { -#ifdef DUMP_REG - printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); -#endif - NVWriteSeq(par, i, state->seq[i]); - } - - /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ - NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); - - for (i = 0; i < NUM_CRT_REGS; i++) { - switch (i) { - case 0x19: - case 0x20 ... 0x40: - break; - default: -#ifdef DUMP_REG - printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); -#endif - NVWriteCrtc(par, i, state->crtc[i]); - } - } - - for (i = 0; i < NUM_GRC_REGS; i++) { -#ifdef DUMP_REG - printk(" GRA[%02x] = %08x\n", i, state->gra[i]); -#endif - NVWriteGr(par, i, state->gra[i]); - } - - for (i = 0; i < NUM_ATC_REGS; i++) { -#ifdef DUMP_REG - printk("ATTR[%02x] = %08x\n", i, state->attr[i]); -#endif - NVWriteAttr(par, i, state->attr[i]); - } - - NVTRACE_LEAVE(); -} - -static int nvidia_calc_regs(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - struct _riva_hw_state *state = &par->ModeReg; - int i, depth = fb_get_color_depth(&info->var, &info->fix); - int h_display = info->var.xres / 8 - 1; - int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; - int h_end = (info->var.xres + info->var.right_margin + - info->var.hsync_len) / 8 - 1; - int h_total = (info->var.xres + info->var.right_margin + - info->var.hsync_len + info->var.left_margin) / 8 - 5; - int h_blank_s = h_display; - int h_blank_e = h_total + 4; - int v_display = info->var.yres - 1; - int v_start = info->var.yres + info->var.lower_margin - 1; - int v_end = (info->var.yres + info->var.lower_margin + - info->var.vsync_len) - 1; - int v_total = (info->var.yres + info->var.lower_margin + - info->var.vsync_len + info->var.upper_margin) - 2; - int v_blank_s = v_display; - int v_blank_e = v_total + 1; - - /* - * Set all CRTC values. - */ - - if (info->var.vmode & FB_VMODE_INTERLACED) - v_total |= 1; - - if (par->FlatPanel == 1) { - v_start = v_total - 3; - v_end = v_total - 2; - v_blank_s = v_start; - h_start = h_total - 5; - h_end = h_total - 2; - h_blank_e = h_total + 4; - } - - state->crtc[0x0] = Set8Bits(h_total); - state->crtc[0x1] = Set8Bits(h_display); - state->crtc[0x2] = Set8Bits(h_blank_s); - state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) - | SetBit(7); - state->crtc[0x4] = Set8Bits(h_start); - state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) - | SetBitField(h_end, 4: 0, 4:0); - state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); - state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) - | SetBitField(v_display, 8: 8, 1:1) - | SetBitField(v_start, 8: 8, 2:2) - | SetBitField(v_blank_s, 8: 8, 3:3) - | SetBit(4) - | SetBitField(v_total, 9: 9, 5:5) - | SetBitField(v_display, 9: 9, 6:6) - | SetBitField(v_start, 9: 9, 7:7); - state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) - | SetBit(6) - | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); - state->crtc[0x10] = Set8Bits(v_start); - state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); - state->crtc[0x12] = Set8Bits(v_display); - state->crtc[0x13] = ((info->var.xres_virtual / 8) * - (info->var.bits_per_pixel / 8)); - state->crtc[0x15] = Set8Bits(v_blank_s); - state->crtc[0x16] = Set8Bits(v_blank_e); - - state->attr[0x10] = 0x01; - - if (par->Television) - state->attr[0x11] = 0x00; - - state->screen = SetBitField(h_blank_e, 6: 6, 4:4) - | SetBitField(v_blank_s, 10: 10, 3:3) - | SetBitField(v_start, 10: 10, 2:2) - | SetBitField(v_display, 10: 10, 1:1) - | SetBitField(v_total, 10: 10, 0:0); - - state->horiz = SetBitField(h_total, 8: 8, 0:0) - | SetBitField(h_display, 8: 8, 1:1) - | SetBitField(h_blank_s, 8: 8, 2:2) - | SetBitField(h_start, 8: 8, 3:3); - - state->extra = SetBitField(v_total, 11: 11, 0:0) - | SetBitField(v_display, 11: 11, 2:2) - | SetBitField(v_start, 11: 11, 4:4) - | SetBitField(v_blank_s, 11: 11, 6:6); - - if (info->var.vmode & FB_VMODE_INTERLACED) { - h_total = (h_total >> 1) & ~1; - state->interlace = Set8Bits(h_total); - state->horiz |= SetBitField(h_total, 8: 8, 4:4); - } else { - state->interlace = 0xff; /* interlace off */ - } - - /* - * Calculate the extended registers. - */ - - if (depth < 24) - i = depth; - else - i = 32; - - if (par->Architecture >= NV_ARCH_10) - par->CURSOR = (volatile u32 __iomem *)(info->screen_base + - par->CursorStart); - - if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) - state->misc_output &= ~0x40; - else - state->misc_output |= 0x40; - if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) - state->misc_output &= ~0x80; - else - state->misc_output |= 0x80; - - NVCalcStateExt(par, state, i, info->var.xres_virtual, - info->var.xres, info->var.yres_virtual, - 1000000000 / info->var.pixclock, info->var.vmode); - - state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; - if (par->FlatPanel == 1) { - state->pixel |= (1 << 7); - - if (!par->fpScaler || (par->fpWidth <= info->var.xres) - || (par->fpHeight <= info->var.yres)) { - state->scale |= (1 << 8); - } - - if (!par->crtcSync_read) { - state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); - par->crtcSync_read = 1; - } - - par->PanelTweak = nvidia_panel_tweak(par, state); - } - - state->vpll = state->pll; - state->vpll2 = state->pll; - state->vpllB = state->pllB; - state->vpll2B = state->pllB; - - VGA_WR08(par->PCIO, 0x03D4, 0x1C); - state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); - - if (par->CRTCnumber) { - state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; - state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; - state->crtcOwner = 3; - state->pllsel |= 0x20000800; - state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); - if (par->twoStagePLL) - state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); - } else if (par->twoHeads) { - state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; - state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; - state->crtcOwner = 0; - state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); - if (par->twoStagePLL) - state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); - } - - state->cursorConfig = 0x00000100; - - if (info->var.vmode & FB_VMODE_DOUBLE) - state->cursorConfig |= (1 << 4); - - if (par->alphaCursor) { - if ((par->Chipset & 0x0ff0) != 0x0110) - state->cursorConfig |= 0x04011000; - else - state->cursorConfig |= 0x14011000; - state->general |= (1 << 29); - } else - state->cursorConfig |= 0x02000000; - - if (par->twoHeads) { - if ((par->Chipset & 0x0ff0) == 0x0110) { - state->dither = NV_RD32(par->PRAMDAC, 0x0528) & - ~0x00010000; - if (par->FPDither) - state->dither |= 0x00010000; - } else { - state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; - if (par->FPDither) - state->dither |= 1; - } - } - - state->timingH = 0; - state->timingV = 0; - state->displayV = info->var.xres; - - return 0; -} - -static void nvidia_init_vga(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - struct _riva_hw_state *state = &par->ModeReg; - int i; - - for (i = 0; i < 0x10; i++) - state->attr[i] = i; - state->attr[0x10] = 0x41; - state->attr[0x11] = 0xff; - state->attr[0x12] = 0x0f; - state->attr[0x13] = 0x00; - state->attr[0x14] = 0x00; - - memset(state->crtc, 0x00, NUM_CRT_REGS); - state->crtc[0x0a] = 0x20; - state->crtc[0x17] = 0xe3; - state->crtc[0x18] = 0xff; - state->crtc[0x28] = 0x40; - - memset(state->gra, 0x00, NUM_GRC_REGS); - state->gra[0x05] = 0x40; - state->gra[0x06] = 0x05; - state->gra[0x07] = 0x0f; - state->gra[0x08] = 0xff; - - state->seq[0x00] = 0x03; - state->seq[0x01] = 0x01; - state->seq[0x02] = 0x0f; - state->seq[0x03] = 0x00; - state->seq[0x04] = 0x0e; - - state->misc_output = 0xeb; -} - -static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - struct nvidia_par *par = info->par; - u8 data[MAX_CURS * MAX_CURS / 8]; - int i, set = cursor->set; - u16 fg, bg; - - if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) - return -ENXIO; - - NVShowHideCursor(par, 0); - - if (par->cursor_reset) { - set = FB_CUR_SETALL; - par->cursor_reset = 0; - } - - if (set & FB_CUR_SETSIZE) - memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); - - if (set & FB_CUR_SETPOS) { - u32 xx, yy, temp; - - yy = cursor->image.dy - info->var.yoffset; - xx = cursor->image.dx - info->var.xoffset; - temp = xx & 0xFFFF; - temp |= yy << 16; - - NV_WR32(par->PRAMDAC, 0x0000300, temp); - } - - if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { - u32 bg_idx = cursor->image.bg_color; - u32 fg_idx = cursor->image.fg_color; - u32 s_pitch = (cursor->image.width + 7) >> 3; - u32 d_pitch = MAX_CURS / 8; - u8 *dat = (u8 *) cursor->image.data; - u8 *msk = (u8 *) cursor->mask; - u8 *src; - - src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC); - - if (src) { - switch (cursor->rop) { - case ROP_XOR: - for (i = 0; i < s_pitch * cursor->image.height; i++) - src[i] = dat[i] ^ msk[i]; - break; - case ROP_COPY: - default: - for (i = 0; i < s_pitch * cursor->image.height; i++) - src[i] = dat[i] & msk[i]; - break; - } - - fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, - cursor->image.height); - - bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | - ((info->cmap.green[bg_idx] & 0xf8) << 2) | - ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; - - fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | - ((info->cmap.green[fg_idx] & 0xf8) << 2) | - ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; - - NVLockUnlock(par, 0); - - nvidiafb_load_cursor_image(par, data, bg, fg, - cursor->image.width, - cursor->image.height); - kfree(src); - } - } - - if (cursor->enable) - NVShowHideCursor(par, 1); - - return 0; -} - -static struct fb_ops nvidia_fb_ops; - -static int nvidiafb_set_par(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - - NVTRACE_ENTER(); - - NVLockUnlock(par, 1); - if (!par->FlatPanel || !par->twoHeads) - par->FPDither = 0; - - if (par->FPDither < 0) { - if ((par->Chipset & 0x0ff0) == 0x0110) - par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) - & 0x00010000); - else - par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); - printk(KERN_INFO PFX "Flat panel dithering %s\n", - par->FPDither ? "enabled" : "disabled"); - } - - info->fix.visual = (info->var.bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - - nvidia_init_vga(info); - nvidia_calc_regs(info); - - NVLockUnlock(par, 0); - if (par->twoHeads) { - VGA_WR08(par->PCIO, 0x03D4, 0x44); - VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); - NVLockUnlock(par, 0); - } - - nvidia_screen_off(par, 1); - - nvidia_write_regs(par, &par->ModeReg); - NVSetStartAddress(par, 0); - -#if defined (__BIG_ENDIAN) - /* turn on LFB swapping */ - { - unsigned char tmp; - - VGA_WR08(par->PCIO, 0x3d4, 0x46); - tmp = VGA_RD08(par->PCIO, 0x3d5); - tmp |= (1 << 7); - VGA_WR08(par->PCIO, 0x3d5, tmp); - } -#endif - - info->fix.line_length = (info->var.xres_virtual * - info->var.bits_per_pixel) >> 3; - if (info->var.accel_flags) { - nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit; - nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect; - nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea; - nvidia_fb_ops.fb_sync = nvidiafb_sync; - info->pixmap.scan_align = 4; - info->flags &= ~FBINFO_HWACCEL_DISABLED; - info->flags |= FBINFO_READS_FAST; - NVResetGraphics(info); - } else { - nvidia_fb_ops.fb_imageblit = cfb_imageblit; - nvidia_fb_ops.fb_fillrect = cfb_fillrect; - nvidia_fb_ops.fb_copyarea = cfb_copyarea; - nvidia_fb_ops.fb_sync = NULL; - info->pixmap.scan_align = 1; - info->flags |= FBINFO_HWACCEL_DISABLED; - info->flags &= ~FBINFO_READS_FAST; - } - - par->cursor_reset = 1; - - nvidia_screen_off(par, 0); - -#ifdef CONFIG_BOOTX_TEXT - /* Update debug text engine */ - btext_update_display(info->fix.smem_start, - info->var.xres, info->var.yres, - info->var.bits_per_pixel, info->fix.line_length); -#endif - - NVLockUnlock(par, 0); - NVTRACE_LEAVE(); - return 0; -} - -static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct nvidia_par *par = info->par; - int i; - - NVTRACE_ENTER(); - if (regno >= (1 << info->var.green.length)) - return -EINVAL; - - if (info->var.grayscale) { - /* gray = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - } - - if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { - ((u32 *) info->pseudo_palette)[regno] = - (regno << info->var.red.offset) | - (regno << info->var.green.offset) | - (regno << info->var.blue.offset); - } - - switch (info->var.bits_per_pixel) { - case 8: - /* "transparent" stuff is completely ignored. */ - nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); - break; - case 16: - if (info->var.green.length == 5) { - for (i = 0; i < 8; i++) { - nvidia_write_clut(par, regno * 8 + i, red >> 8, - green >> 8, blue >> 8); - } - } else { - u8 r, g, b; - - if (regno < 32) { - for (i = 0; i < 8; i++) { - nvidia_write_clut(par, regno * 8 + i, - red >> 8, green >> 8, - blue >> 8); - } - } - - nvidia_read_clut(par, regno * 4, &r, &g, &b); - - for (i = 0; i < 4; i++) - nvidia_write_clut(par, regno * 4 + i, r, - green >> 8, b); - } - break; - case 32: - nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); - break; - default: - /* do nothing */ - break; - } - - NVTRACE_LEAVE(); - return 0; -} - -static int nvidiafb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct nvidia_par *par = info->par; - int memlen, vramlen, mode_valid = 0; - int pitch, err = 0; - - NVTRACE_ENTER(); - - var->transp.offset = 0; - var->transp.length = 0; - - var->xres &= ~7; - - if (var->bits_per_pixel <= 8) - var->bits_per_pixel = 8; - else if (var->bits_per_pixel <= 16) - var->bits_per_pixel = 16; - else - var->bits_per_pixel = 32; - - switch (var->bits_per_pixel) { - case 8: - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; - case 16: - var->green.length = (var->green.length < 6) ? 5 : 6; - var->red.length = 5; - var->blue.length = 5; - var->transp.length = 6 - var->green.length; - var->blue.offset = 0; - var->green.offset = 5; - var->red.offset = 5 + var->green.length; - var->transp.offset = (5 + var->red.offset) & 15; - break; - case 32: /* RGBA 8888 */ - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 24; - break; - } - - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - var->transp.msb_right = 0; - - if (!info->monspecs.hfmax || !info->monspecs.vfmax || - !info->monspecs.dclkmax || !fb_validate_mode(var, info)) - mode_valid = 1; - - /* calculate modeline if supported by monitor */ - if (!mode_valid && info->monspecs.gtf) { - if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) - mode_valid = 1; - } - - if (!mode_valid) { - const struct fb_videomode *mode; - - mode = fb_find_best_mode(var, &info->modelist); - if (mode) { - fb_videomode_to_var(var, mode); - mode_valid = 1; - } - } - - if (!mode_valid && info->monspecs.modedb_len) - return -EINVAL; - - /* - * If we're on a flat panel, check if the mode is outside of the - * panel dimensions. If so, cap it and try for the next best mode - * before bailing out. - */ - if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || - par->fpHeight < var->yres)) { - const struct fb_videomode *mode; - - var->xres = par->fpWidth; - var->yres = par->fpHeight; - - mode = fb_find_best_mode(var, &info->modelist); - if (!mode) { - printk(KERN_ERR PFX "mode out of range of flat " - "panel dimensions\n"); - return -EINVAL; - } - - fb_videomode_to_var(var, mode); - } - - if (var->yres_virtual < var->yres) - var->yres_virtual = var->yres; - - if (var->xres_virtual < var->xres) - var->xres_virtual = var->xres; - - var->xres_virtual = (var->xres_virtual + 63) & ~63; - - vramlen = info->screen_size; - pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; - memlen = pitch * var->yres_virtual; - - if (memlen > vramlen) { - var->yres_virtual = vramlen / pitch; - - if (var->yres_virtual < var->yres) { - var->yres_virtual = var->yres; - var->xres_virtual = vramlen / var->yres_virtual; - var->xres_virtual /= var->bits_per_pixel / 8; - var->xres_virtual &= ~63; - pitch = (var->xres_virtual * - var->bits_per_pixel + 7) / 8; - memlen = pitch * var->yres; - - if (var->xres_virtual < var->xres) { - printk("nvidiafb: required video memory, " - "%d bytes, for %dx%d-%d (virtual) " - "is out of range\n", - memlen, var->xres_virtual, - var->yres_virtual, var->bits_per_pixel); - err = -ENOMEM; - } - } - } - - if (var->accel_flags) { - if (var->yres_virtual > 0x7fff) - var->yres_virtual = 0x7fff; - if (var->xres_virtual > 0x7fff) - var->xres_virtual = 0x7fff; - } - - var->xres_virtual &= ~63; - - NVTRACE_LEAVE(); - - return err; -} - -static int nvidiafb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct nvidia_par *par = info->par; - u32 total; - - total = var->yoffset * info->fix.line_length + var->xoffset; - - NVSetStartAddress(par, total); - - return 0; -} - -static int nvidiafb_blank(int blank, struct fb_info *info) -{ - struct nvidia_par *par = info->par; - unsigned char tmp, vesa; - - tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ - vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ - - NVTRACE_ENTER(); - - if (blank) - tmp |= 0x20; - - switch (blank) { - case FB_BLANK_UNBLANK: - case FB_BLANK_NORMAL: - break; - case FB_BLANK_VSYNC_SUSPEND: - vesa |= 0x80; - break; - case FB_BLANK_HSYNC_SUSPEND: - vesa |= 0x40; - break; - case FB_BLANK_POWERDOWN: - vesa |= 0xc0; - break; - } - - NVWriteSeq(par, 0x01, tmp); - NVWriteCrtc(par, 0x1a, vesa); - - NVTRACE_LEAVE(); - - return 0; -} - -/* - * Because the VGA registers are not mapped linearly in its MMIO space, - * restrict VGA register saving and restore to x86 only, where legacy VGA IO - * access is legal. Consequently, we must also check if the device is the - * primary display. - */ -#ifdef CONFIG_X86 -static void save_vga_x86(struct nvidia_par *par) -{ - struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; - - if (res && res->flags & IORESOURCE_ROM_SHADOW) { - memset(&par->vgastate, 0, sizeof(par->vgastate)); - par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | - VGA_SAVE_CMAP; - save_vga(&par->vgastate); - } -} - -static void restore_vga_x86(struct nvidia_par *par) -{ - struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; - - if (res && res->flags & IORESOURCE_ROM_SHADOW) - restore_vga(&par->vgastate); -} -#else -#define save_vga_x86(x) do {} while (0) -#define restore_vga_x86(x) do {} while (0) -#endif /* X86 */ - -static int nvidiafb_open(struct fb_info *info, int user) -{ - struct nvidia_par *par = info->par; - - if (!par->open_count) { - save_vga_x86(par); - nvidia_save_vga(par, &par->initial_state); - } - - par->open_count++; - return 0; -} - -static int nvidiafb_release(struct fb_info *info, int user) -{ - struct nvidia_par *par = info->par; - int err = 0; - - if (!par->open_count) { - err = -EINVAL; - goto done; - } - - if (par->open_count == 1) { - nvidia_write_regs(par, &par->initial_state); - restore_vga_x86(par); - } - - par->open_count--; -done: - return err; -} - -static struct fb_ops nvidia_fb_ops = { - .owner = THIS_MODULE, - .fb_open = nvidiafb_open, - .fb_release = nvidiafb_release, - .fb_check_var = nvidiafb_check_var, - .fb_set_par = nvidiafb_set_par, - .fb_setcolreg = nvidiafb_setcolreg, - .fb_pan_display = nvidiafb_pan_display, - .fb_blank = nvidiafb_blank, - .fb_fillrect = nvidiafb_fillrect, - .fb_copyarea = nvidiafb_copyarea, - .fb_imageblit = nvidiafb_imageblit, - .fb_cursor = nvidiafb_cursor, - .fb_sync = nvidiafb_sync, -}; - -static int nvidiafb_suspend_late(struct device *dev, pm_message_t mesg) -{ - struct fb_info *info = dev_get_drvdata(dev); - struct nvidia_par *par = info->par; - - if (mesg.event == PM_EVENT_PRETHAW) - mesg.event = PM_EVENT_FREEZE; - console_lock(); - par->pm_state = mesg.event; - - if (mesg.event & PM_EVENT_SLEEP) { - fb_set_suspend(info, 1); - nvidiafb_blank(FB_BLANK_POWERDOWN, info); - nvidia_write_regs(par, &par->SavedReg); - } - dev->power.power_state = mesg; - - console_unlock(); - return 0; -} - -static int __maybe_unused nvidiafb_suspend(struct device *dev) -{ - return nvidiafb_suspend_late(dev, PMSG_SUSPEND); -} - -static int __maybe_unused nvidiafb_hibernate(struct device *dev) -{ - return nvidiafb_suspend_late(dev, PMSG_HIBERNATE); -} - -static int __maybe_unused nvidiafb_freeze(struct device *dev) -{ - return nvidiafb_suspend_late(dev, PMSG_FREEZE); -} - -static int __maybe_unused nvidiafb_resume(struct device *dev) -{ - struct fb_info *info = dev_get_drvdata(dev); - struct nvidia_par *par = info->par; - - console_lock(); - - par->pm_state = PM_EVENT_ON; - nvidiafb_set_par(info); - fb_set_suspend (info, 0); - nvidiafb_blank(FB_BLANK_UNBLANK, info); - - console_unlock(); - return 0; -} - -static const struct dev_pm_ops nvidiafb_pm_ops = { -#ifdef CONFIG_PM_SLEEP - .suspend = nvidiafb_suspend, - .resume = nvidiafb_resume, - .freeze = nvidiafb_freeze, - .thaw = nvidiafb_resume, - .poweroff = nvidiafb_hibernate, - .restore = nvidiafb_resume, -#endif /* CONFIG_PM_SLEEP */ -}; - -static int nvidia_set_fbinfo(struct fb_info *info) -{ - struct fb_monspecs *specs = &info->monspecs; - struct fb_videomode modedb; - struct nvidia_par *par = info->par; - int lpitch; - - NVTRACE_ENTER(); - info->flags = FBINFO_DEFAULT - | FBINFO_HWACCEL_IMAGEBLIT - | FBINFO_HWACCEL_FILLRECT - | FBINFO_HWACCEL_COPYAREA - | FBINFO_HWACCEL_YPAN; - - fb_videomode_to_modelist(info->monspecs.modedb, - info->monspecs.modedb_len, &info->modelist); - fb_var_to_videomode(&modedb, &nvidiafb_default_var); - - switch (bpp) { - case 0 ... 8: - bpp = 8; - break; - case 9 ... 16: - bpp = 16; - break; - default: - bpp = 32; - break; - } - - if (specs->modedb != NULL) { - const struct fb_videomode *mode; - - mode = fb_find_best_display(specs, &info->modelist); - fb_videomode_to_var(&nvidiafb_default_var, mode); - nvidiafb_default_var.bits_per_pixel = bpp; - } else if (par->fpWidth && par->fpHeight) { - char buf[16]; - - memset(buf, 0, 16); - snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); - fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, - specs->modedb_len, &modedb, bpp); - } - - if (mode_option) - fb_find_mode(&nvidiafb_default_var, info, mode_option, - specs->modedb, specs->modedb_len, &modedb, bpp); - - info->var = nvidiafb_default_var; - info->fix.visual = (info->var.bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - info->pseudo_palette = par->pseudo_palette; - fb_alloc_cmap(&info->cmap, 256, 0); - fb_destroy_modedb(info->monspecs.modedb); - info->monspecs.modedb = NULL; - - /* maximize virtual vertical length */ - lpitch = info->var.xres_virtual * - ((info->var.bits_per_pixel + 7) >> 3); - info->var.yres_virtual = info->screen_size / lpitch; - - info->pixmap.scan_align = 4; - info->pixmap.buf_align = 4; - info->pixmap.access_align = 32; - info->pixmap.size = 8 * 1024; - info->pixmap.flags = FB_PIXMAP_SYSTEM; - - if (!hwcur) - nvidia_fb_ops.fb_cursor = NULL; - - info->var.accel_flags = (!noaccel); - - switch (par->Architecture) { - case NV_ARCH_04: - info->fix.accel = FB_ACCEL_NV4; - break; - case NV_ARCH_10: - info->fix.accel = FB_ACCEL_NV_10; - break; - case NV_ARCH_20: - info->fix.accel = FB_ACCEL_NV_20; - break; - case NV_ARCH_30: - info->fix.accel = FB_ACCEL_NV_30; - break; - case NV_ARCH_40: - info->fix.accel = FB_ACCEL_NV_40; - break; - } - - NVTRACE_LEAVE(); - - return nvidiafb_check_var(&info->var, info); -} - -static u32 nvidia_get_chipset(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; - - printk(KERN_INFO PFX "Device ID: %x \n", id); - - if ((id & 0xfff0) == 0x00f0 || - (id & 0xfff0) == 0x02e0) { - /* pci-e */ - id = NV_RD32(par->REGS, 0x1800); - - if ((id & 0x0000ffff) == 0x000010DE) - id = 0x10DE0000 | (id >> 16); - else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ - id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | - ((id >> 8) & 0x000000ff); - printk(KERN_INFO PFX "Subsystem ID: %x \n", id); - } - - return id; -} - -static u32 nvidia_get_arch(struct fb_info *info) -{ - struct nvidia_par *par = info->par; - u32 arch = 0; - - switch (par->Chipset & 0x0ff0) { - case 0x0100: /* GeForce 256 */ - case 0x0110: /* GeForce2 MX */ - case 0x0150: /* GeForce2 */ - case 0x0170: /* GeForce4 MX */ - case 0x0180: /* GeForce4 MX (8x AGP) */ - case 0x01A0: /* nForce */ - case 0x01F0: /* nForce2 */ - arch = NV_ARCH_10; - break; - case 0x0200: /* GeForce3 */ - case 0x0250: /* GeForce4 Ti */ - case 0x0280: /* GeForce4 Ti (8x AGP) */ - arch = NV_ARCH_20; - break; - case 0x0300: /* GeForceFX 5800 */ - case 0x0310: /* GeForceFX 5600 */ - case 0x0320: /* GeForceFX 5200 */ - case 0x0330: /* GeForceFX 5900 */ - case 0x0340: /* GeForceFX 5700 */ - arch = NV_ARCH_30; - break; - case 0x0040: /* GeForce 6800 */ - case 0x00C0: /* GeForce 6800 */ - case 0x0120: /* GeForce 6800 */ - case 0x0140: /* GeForce 6600 */ - case 0x0160: /* GeForce 6200 */ - case 0x01D0: /* GeForce 7200, 7300, 7400 */ - case 0x0090: /* GeForce 7800 */ - case 0x0210: /* GeForce 6800 */ - case 0x0220: /* GeForce 6200 */ - case 0x0240: /* GeForce 6100 */ - case 0x0290: /* GeForce 7900 */ - case 0x0390: /* GeForce 7600 */ - case 0x03D0: - arch = NV_ARCH_40; - break; - case 0x0020: /* TNT, TNT2 */ - arch = NV_ARCH_04; - break; - default: /* unknown architecture */ - break; - } - - return arch; -} - -static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) -{ - struct nvidia_par *par; - struct fb_info *info; - unsigned short cmd; - - - NVTRACE_ENTER(); - assert(pd != NULL); - - info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); - - if (!info) - goto err_out; - - par = info->par; - par->pci_dev = pd; - info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); - - if (info->pixmap.addr == NULL) - goto err_out_kfree; - - if (pci_enable_device(pd)) { - printk(KERN_ERR PFX "cannot enable PCI device\n"); - goto err_out_enable; - } - - if (pci_request_regions(pd, "nvidiafb")) { - printk(KERN_ERR PFX "cannot request PCI regions\n"); - goto err_out_enable; - } - - par->FlatPanel = flatpanel; - if (flatpanel == 1) - printk(KERN_INFO PFX "flatpanel support enabled\n"); - par->FPDither = fpdither; - - par->CRTCnumber = forceCRTC; - par->FpScale = (!noscale); - par->paneltweak = paneltweak; - par->reverse_i2c = reverse_i2c; - - /* enable IO and mem if not already done */ - pci_read_config_word(pd, PCI_COMMAND, &cmd); - cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - pci_write_config_word(pd, PCI_COMMAND, cmd); - - nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); - nvidiafb_fix.smem_start = pci_resource_start(pd, 1); - nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); - - par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); - - if (!par->REGS) { - printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); - goto err_out_free_base0; - } - - par->Chipset = nvidia_get_chipset(info); - par->Architecture = nvidia_get_arch(info); - - if (par->Architecture == 0) { - printk(KERN_ERR PFX "unknown NV_ARCH\n"); - goto err_out_arch; - } - - sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); - - if (NVCommonSetup(info)) - goto err_out_arch; - - par->FbAddress = nvidiafb_fix.smem_start; - par->FbMapSize = par->RamAmountKBytes * 1024; - if (vram && vram * 1024 * 1024 < par->FbMapSize) - par->FbMapSize = vram * 1024 * 1024; - - /* Limit amount of vram to 64 MB */ - if (par->FbMapSize > 64 * 1024 * 1024) - par->FbMapSize = 64 * 1024 * 1024; - - if(par->Architecture >= NV_ARCH_40) - par->FbUsableSize = par->FbMapSize - (560 * 1024); - else - par->FbUsableSize = par->FbMapSize - (128 * 1024); - par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : - 16 * 1024; - par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; - par->CursorStart = par->FbUsableSize + (32 * 1024); - - info->screen_base = ioremap_wc(nvidiafb_fix.smem_start, - par->FbMapSize); - info->screen_size = par->FbUsableSize; - nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; - - if (!info->screen_base) { - printk(KERN_ERR PFX "cannot ioremap FB base\n"); - goto err_out_free_base1; - } - - par->FbStart = info->screen_base; - - if (!nomtrr) - par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start, - par->RamAmountKBytes * 1024); - - info->fbops = &nvidia_fb_ops; - info->fix = nvidiafb_fix; - - if (nvidia_set_fbinfo(info) < 0) { - printk(KERN_ERR PFX "error setting initial video mode\n"); - goto err_out_iounmap_fb; - } - - nvidia_save_vga(par, &par->SavedReg); - - pci_set_drvdata(pd, info); - - if (backlight) - nvidia_bl_init(par); - - if (register_framebuffer(info) < 0) { - printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); - goto err_out_iounmap_fb; - } - - - printk(KERN_INFO PFX - "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", - info->fix.id, - par->FbMapSize / (1024 * 1024), info->fix.smem_start); - - NVTRACE_LEAVE(); - return 0; - -err_out_iounmap_fb: - iounmap(info->screen_base); -err_out_free_base1: - fb_destroy_modedb(info->monspecs.modedb); - nvidia_delete_i2c_busses(par); -err_out_arch: - iounmap(par->REGS); - err_out_free_base0: - pci_release_regions(pd); -err_out_enable: - kfree(info->pixmap.addr); -err_out_kfree: - framebuffer_release(info); -err_out: - return -ENODEV; -} - -static void nvidiafb_remove(struct pci_dev *pd) -{ - struct fb_info *info = pci_get_drvdata(pd); - struct nvidia_par *par = info->par; - - NVTRACE_ENTER(); - - unregister_framebuffer(info); - - nvidia_bl_exit(par); - arch_phys_wc_del(par->wc_cookie); - iounmap(info->screen_base); - fb_destroy_modedb(info->monspecs.modedb); - nvidia_delete_i2c_busses(par); - iounmap(par->REGS); - pci_release_regions(pd); - kfree(info->pixmap.addr); - framebuffer_release(info); - NVTRACE_LEAVE(); -} - -/* ------------------------------------------------------------------------- * - * - * initialization - * - * ------------------------------------------------------------------------- */ - -#ifndef MODULE -static int nvidiafb_setup(char *options) -{ - char *this_opt; - - NVTRACE_ENTER(); - if (!options || !*options) - return 0; - - while ((this_opt = strsep(&options, ",")) != NULL) { - if (!strncmp(this_opt, "forceCRTC", 9)) { - char *p; - - p = this_opt + 9; - if (!*p || !*(++p)) - continue; - forceCRTC = *p - '0'; - if (forceCRTC < 0 || forceCRTC > 1) - forceCRTC = -1; - } else if (!strncmp(this_opt, "flatpanel", 9)) { - flatpanel = 1; - } else if (!strncmp(this_opt, "hwcur", 5)) { - hwcur = 1; - } else if (!strncmp(this_opt, "noaccel", 6)) { - noaccel = 1; - } else if (!strncmp(this_opt, "noscale", 7)) { - noscale = 1; - } else if (!strncmp(this_opt, "reverse_i2c", 11)) { - reverse_i2c = 1; - } else if (!strncmp(this_opt, "paneltweak:", 11)) { - paneltweak = simple_strtoul(this_opt+11, NULL, 0); - } else if (!strncmp(this_opt, "vram:", 5)) { - vram = simple_strtoul(this_opt+5, NULL, 0); - } else if (!strncmp(this_opt, "backlight:", 10)) { - backlight = simple_strtoul(this_opt+10, NULL, 0); - } else if (!strncmp(this_opt, "nomtrr", 6)) { - nomtrr = true; - } else if (!strncmp(this_opt, "fpdither:", 9)) { - fpdither = simple_strtol(this_opt+9, NULL, 0); - } else if (!strncmp(this_opt, "bpp:", 4)) { - bpp = simple_strtoul(this_opt+4, NULL, 0); - } else - mode_option = this_opt; - } - NVTRACE_LEAVE(); - return 0; -} -#endif /* !MODULE */ - -static struct pci_driver nvidiafb_driver = { - .name = "nvidiafb", - .id_table = nvidiafb_pci_tbl, - .probe = nvidiafb_probe, - .driver.pm = &nvidiafb_pm_ops, - .remove = nvidiafb_remove, -}; - -/* ------------------------------------------------------------------------- * - * - * modularization - * - * ------------------------------------------------------------------------- */ - -static int nvidiafb_init(void) -{ -#ifndef MODULE - char *option = NULL; - - if (fb_get_options("nvidiafb", &option)) - return -ENODEV; - nvidiafb_setup(option); -#endif - return pci_register_driver(&nvidiafb_driver); -} - -module_init(nvidiafb_init); - -static void __exit nvidiafb_exit(void) -{ - pci_unregister_driver(&nvidiafb_driver); -} - -module_exit(nvidiafb_exit); - -module_param(flatpanel, int, 0); -MODULE_PARM_DESC(flatpanel, - "Enables experimental flat panel support for some chipsets. " - "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); -module_param(fpdither, int, 0); -MODULE_PARM_DESC(fpdither, - "Enables dithering of flat panel for 6 bits panels. " - "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); -module_param(hwcur, int, 0); -MODULE_PARM_DESC(hwcur, - "Enables hardware cursor implementation. (0 or 1=enabled) " - "(default=0)"); -module_param(noaccel, int, 0); -MODULE_PARM_DESC(noaccel, - "Disables hardware acceleration. (0 or 1=disable) " - "(default=0)"); -module_param(noscale, int, 0); -MODULE_PARM_DESC(noscale, - "Disables screen scaling. (0 or 1=disable) " - "(default=0, do scaling)"); -module_param(paneltweak, int, 0); -MODULE_PARM_DESC(paneltweak, - "Tweak display settings for flatpanels. " - "(default=0, no tweaks)"); -module_param(forceCRTC, int, 0); -MODULE_PARM_DESC(forceCRTC, - "Forces usage of a particular CRTC in case autodetection " - "fails. (0 or 1) (default=autodetect)"); -module_param(vram, int, 0); -MODULE_PARM_DESC(vram, - "amount of framebuffer memory to remap in MiB" - "(default=0 - remap entire memory)"); -module_param(mode_option, charp, 0); -MODULE_PARM_DESC(mode_option, "Specify initial video mode"); -module_param(bpp, int, 0); -MODULE_PARM_DESC(bpp, "pixel width in bits" - "(default=8)"); -module_param(reverse_i2c, int, 0); -MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); -module_param(nomtrr, bool, false); -MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " - "(default=0)"); - -MODULE_AUTHOR("Antonino Daplas"); -MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/riva/Makefile b/drivers/video/fbdev/riva/Makefile deleted file mode 100644 index bdbdd6eb80ec..000000000000 --- a/drivers/video/fbdev/riva/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the Riva framebuffer driver -# - -obj-$(CONFIG_FB_RIVA) += rivafb.o - -rivafb-objs := fbdev.o riva_hw.o nv_driver.o - -ifdef CONFIG_FB_RIVA_I2C - rivafb-objs += rivafb-i2c.o -endif diff --git a/drivers/video/fbdev/riva/fbdev.c b/drivers/video/fbdev/riva/fbdev.c deleted file mode 100644 index 7dd621c7afe4..000000000000 --- a/drivers/video/fbdev/riva/fbdev.c +++ /dev/null @@ -1,2195 +0,0 @@ -/* - * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver - * - * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> - * - * Copyright 1999-2000 Jeff Garzik - * - * Contributors: - * - * Ani Joshi: Lots of debugging and cleanup work, really helped - * get the driver going - * - * Ferenc Bakonyi: Bug fixes, cleanup, modularization - * - * Jindrich Makovicka: Accel code help, hw cursor, mtrr - * - * Paul Richards: Bug fixes, updates - * - * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven - * Includes riva_hw.c from nVidia, see copyright below. - * KGI code provided the basis for state storage, init, and mode switching. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Known bugs and issues: - * restoring text mode fails - * doublescan modes are broken - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/backlight.h> -#include <linux/bitrev.h> -#ifdef CONFIG_PMAC_BACKLIGHT -#include <asm/machdep.h> -#include <asm/backlight.h> -#endif - -#include "rivafb.h" -#include "nvreg.h" - -/* version number of this driver */ -#define RIVAFB_VERSION "0.9.5b" - -/* ------------------------------------------------------------------------- * - * - * various helpful macros and constants - * - * ------------------------------------------------------------------------- */ -#ifdef CONFIG_FB_RIVA_DEBUG -#define NVTRACE printk -#else -#define NVTRACE if(0) printk -#endif - -#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) -#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) - -#ifdef CONFIG_FB_RIVA_DEBUG -#define assert(expr) \ - if(!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n",\ - #expr,__FILE__,__func__,__LINE__); \ - BUG(); \ - } -#else -#define assert(expr) -#endif - -#define PFX "rivafb: " - -/* macro that allows you to set overflow bits */ -#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) -#define SetBit(n) (1<<(n)) -#define Set8Bits(value) ((value)&0xff) - -/* HW cursor parameters */ -#define MAX_CURS 32 - -/* ------------------------------------------------------------------------- * - * - * prototypes - * - * ------------------------------------------------------------------------- */ - -static int rivafb_blank(int blank, struct fb_info *info); - -/* ------------------------------------------------------------------------- * - * - * card identification - * - * ------------------------------------------------------------------------- */ - -static const struct pci_device_id rivafb_pci_tbl[] = { - { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - // NF2/IGP version, GeForce 4 MX, NV18 - { PCI_VENDOR_ID_NVIDIA, 0x01f0, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { 0, } /* terminate list */ -}; -MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); - -/* ------------------------------------------------------------------------- * - * - * global variables - * - * ------------------------------------------------------------------------- */ - -/* command line data, set in rivafb_setup() */ -static int flatpanel = -1; /* Autodetect later */ -static int forceCRTC = -1; -static bool noaccel = 0; -static bool nomtrr = 0; -static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); - -static char *mode_option = NULL; -static bool strictmode = 0; - -static struct fb_fix_screeninfo rivafb_fix = { - .type = FB_TYPE_PACKED_PIXELS, - .xpanstep = 1, - .ypanstep = 1, -}; - -static struct fb_var_screeninfo rivafb_default_var = { - .xres = 640, - .yres = 480, - .xres_virtual = 640, - .yres_virtual = 480, - .bits_per_pixel = 8, - .red = {0, 8, 0}, - .green = {0, 8, 0}, - .blue = {0, 8, 0}, - .transp = {0, 0, 0}, - .activate = FB_ACTIVATE_NOW, - .height = -1, - .width = -1, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* from GGI */ -static const struct riva_regs reg_template = { - {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, - 0x41, 0x01, 0x0F, 0x00, 0x00}, - {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ - 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, /* 0x40 */ - }, - {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ - 0xFF}, - {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ - 0xEB /* MISC */ -}; - -/* - * Backlight control - */ -#ifdef CONFIG_FB_RIVA_BACKLIGHT -/* We do not have any information about which values are allowed, thus - * we used safe values. - */ -#define MIN_LEVEL 0x158 -#define MAX_LEVEL 0x534 -#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) - -static int riva_bl_get_level_brightness(struct riva_par *par, - int level) -{ - struct fb_info *info = pci_get_drvdata(par->pdev); - int nlevel; - - /* Get and convert the value */ - /* No locking on bl_curve since accessing a single value */ - nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; - - if (nlevel < 0) - nlevel = 0; - else if (nlevel < MIN_LEVEL) - nlevel = MIN_LEVEL; - else if (nlevel > MAX_LEVEL) - nlevel = MAX_LEVEL; - - return nlevel; -} - -static int riva_bl_update_status(struct backlight_device *bd) -{ - struct riva_par *par = bl_get_data(bd); - U032 tmp_pcrt, tmp_pmc; - int level; - - if (bd->props.power != FB_BLANK_UNBLANK || - bd->props.fb_blank != FB_BLANK_UNBLANK) - level = 0; - else - level = bd->props.brightness; - - tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; - tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; - if(level > 0) { - tmp_pcrt |= 0x1; - tmp_pmc |= (1 << 31); /* backlight bit */ - tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ - } - NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); - NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); - - return 0; -} - -static const struct backlight_ops riva_bl_ops = { - .update_status = riva_bl_update_status, -}; - -static void riva_bl_init(struct riva_par *par) -{ - struct backlight_properties props; - struct fb_info *info = pci_get_drvdata(par->pdev); - struct backlight_device *bd; - char name[12]; - - if (!par->FlatPanel) - return; - -#ifdef CONFIG_PMAC_BACKLIGHT - if (!machine_is(powermac) || - !pmac_has_backlight_type("mnca")) - return; -#endif - - snprintf(name, sizeof(name), "rivabl%d", info->node); - - memset(&props, 0, sizeof(struct backlight_properties)); - props.type = BACKLIGHT_RAW; - props.max_brightness = FB_BACKLIGHT_LEVELS - 1; - bd = backlight_device_register(name, info->dev, par, &riva_bl_ops, - &props); - if (IS_ERR(bd)) { - info->bl_dev = NULL; - printk(KERN_WARNING "riva: Backlight registration failed\n"); - goto error; - } - - info->bl_dev = bd; - fb_bl_default_curve(info, 0, - MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, - FB_BACKLIGHT_MAX); - - bd->props.brightness = bd->props.max_brightness; - bd->props.power = FB_BLANK_UNBLANK; - backlight_update_status(bd); - - printk("riva: Backlight initialized (%s)\n", name); - - return; - -error: - return; -} - -static void riva_bl_exit(struct fb_info *info) -{ - struct backlight_device *bd = info->bl_dev; - - backlight_device_unregister(bd); - printk("riva: Backlight unloaded\n"); -} -#else -static inline void riva_bl_init(struct riva_par *par) {} -static inline void riva_bl_exit(struct fb_info *info) {} -#endif /* CONFIG_FB_RIVA_BACKLIGHT */ - -/* ------------------------------------------------------------------------- * - * - * MMIO access macros - * - * ------------------------------------------------------------------------- */ - -static inline void CRTCout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PCIO, 0x3d4, index); - VGA_WR08(par->riva.PCIO, 0x3d5, val); -} - -static inline unsigned char CRTCin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PCIO, 0x3d4, index); - return (VGA_RD08(par->riva.PCIO, 0x3d5)); -} - -static inline void GRAout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PVIO, 0x3ce, index); - VGA_WR08(par->riva.PVIO, 0x3cf, val); -} - -static inline unsigned char GRAin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PVIO, 0x3ce, index); - return (VGA_RD08(par->riva.PVIO, 0x3cf)); -} - -static inline void SEQout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PVIO, 0x3c4, index); - VGA_WR08(par->riva.PVIO, 0x3c5, val); -} - -static inline unsigned char SEQin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PVIO, 0x3c4, index); - return (VGA_RD08(par->riva.PVIO, 0x3c5)); -} - -static inline void ATTRout(struct riva_par *par, unsigned char index, - unsigned char val) -{ - VGA_WR08(par->riva.PCIO, 0x3c0, index); - VGA_WR08(par->riva.PCIO, 0x3c0, val); -} - -static inline unsigned char ATTRin(struct riva_par *par, - unsigned char index) -{ - VGA_WR08(par->riva.PCIO, 0x3c0, index); - return (VGA_RD08(par->riva.PCIO, 0x3c1)); -} - -static inline void MISCout(struct riva_par *par, unsigned char val) -{ - VGA_WR08(par->riva.PVIO, 0x3c2, val); -} - -static inline unsigned char MISCin(struct riva_par *par) -{ - return (VGA_RD08(par->riva.PVIO, 0x3cc)); -} - -static inline void reverse_order(u32 *l) -{ - u8 *a = (u8 *)l; - a[0] = bitrev8(a[0]); - a[1] = bitrev8(a[1]); - a[2] = bitrev8(a[2]); - a[3] = bitrev8(a[3]); -} - -/* ------------------------------------------------------------------------- * - * - * cursor stuff - * - * ------------------------------------------------------------------------- */ - -/** - * rivafb_load_cursor_image - load cursor image to hardware - * @data: address to monochrome bitmap (1 = foreground color, 0 = background) - * @par: pointer to private data - * @w: width of cursor image in pixels - * @h: height of cursor image in scanlines - * @bg: background color (ARGB1555) - alpha bit determines opacity - * @fg: foreground color (ARGB1555) - * - * DESCRIPTiON: - * Loads cursor image based on a monochrome source and mask bitmap. The - * image bits determines the color of the pixel, 0 for background, 1 for - * foreground. Only the affected region (as determined by @w and @h - * parameters) will be updated. - * - * CALLED FROM: - * rivafb_cursor() - */ -static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, - u16 bg, u16 fg, u32 w, u32 h) -{ - int i, j, k = 0; - u32 b, tmp; - u32 *data = (u32 *)data8; - bg = le16_to_cpu(bg); - fg = le16_to_cpu(fg); - - w = (w + 1) & ~1; - - for (i = 0; i < h; i++) { - b = *data++; - reverse_order(&b); - - for (j = 0; j < w/2; j++) { - tmp = 0; -#if defined (__BIG_ENDIAN) - tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; - b <<= 1; - tmp |= (b & (1 << 31)) ? fg : bg; - b <<= 1; -#else - tmp = (b & 1) ? fg : bg; - b >>= 1; - tmp |= (b & 1) ? fg << 16 : bg << 16; - b >>= 1; -#endif - writel(tmp, &par->riva.CURSOR[k++]); - } - k += (MAX_CURS - w)/2; - } -} - -/* ------------------------------------------------------------------------- * - * - * general utility functions - * - * ------------------------------------------------------------------------- */ - -/** - * riva_wclut - set CLUT entry - * @chip: pointer to RIVA_HW_INST object - * @regnum: register number - * @red: red component - * @green: green component - * @blue: blue component - * - * DESCRIPTION: - * Sets color register @regnum. - * - * CALLED FROM: - * rivafb_setcolreg() - */ -static void riva_wclut(RIVA_HW_INST *chip, - unsigned char regnum, unsigned char red, - unsigned char green, unsigned char blue) -{ - VGA_WR08(chip->PDIO, 0x3c8, regnum); - VGA_WR08(chip->PDIO, 0x3c9, red); - VGA_WR08(chip->PDIO, 0x3c9, green); - VGA_WR08(chip->PDIO, 0x3c9, blue); -} - -/** - * riva_rclut - read fromCLUT register - * @chip: pointer to RIVA_HW_INST object - * @regnum: register number - * @red: red component - * @green: green component - * @blue: blue component - * - * DESCRIPTION: - * Reads red, green, and blue from color register @regnum. - * - * CALLED FROM: - * rivafb_setcolreg() - */ -static void riva_rclut(RIVA_HW_INST *chip, - unsigned char regnum, unsigned char *red, - unsigned char *green, unsigned char *blue) -{ - - VGA_WR08(chip->PDIO, 0x3c7, regnum); - *red = VGA_RD08(chip->PDIO, 0x3c9); - *green = VGA_RD08(chip->PDIO, 0x3c9); - *blue = VGA_RD08(chip->PDIO, 0x3c9); -} - -/** - * riva_save_state - saves current chip state - * @par: pointer to riva_par object containing info for current riva board - * @regs: pointer to riva_regs object - * - * DESCRIPTION: - * Saves current chip state to @regs. - * - * CALLED FROM: - * rivafb_probe() - */ -/* from GGI */ -static void riva_save_state(struct riva_par *par, struct riva_regs *regs) -{ - int i; - - NVTRACE_ENTER(); - par->riva.LockUnlock(&par->riva, 0); - - par->riva.UnloadStateExt(&par->riva, ®s->ext); - - regs->misc_output = MISCin(par); - - for (i = 0; i < NUM_CRT_REGS; i++) - regs->crtc[i] = CRTCin(par, i); - - for (i = 0; i < NUM_ATC_REGS; i++) - regs->attr[i] = ATTRin(par, i); - - for (i = 0; i < NUM_GRC_REGS; i++) - regs->gra[i] = GRAin(par, i); - - for (i = 0; i < NUM_SEQ_REGS; i++) - regs->seq[i] = SEQin(par, i); - NVTRACE_LEAVE(); -} - -/** - * riva_load_state - loads current chip state - * @par: pointer to riva_par object containing info for current riva board - * @regs: pointer to riva_regs object - * - * DESCRIPTION: - * Loads chip state from @regs. - * - * CALLED FROM: - * riva_load_video_mode() - * rivafb_probe() - * rivafb_remove() - */ -/* from GGI */ -static void riva_load_state(struct riva_par *par, struct riva_regs *regs) -{ - RIVA_HW_STATE *state = ®s->ext; - int i; - - NVTRACE_ENTER(); - CRTCout(par, 0x11, 0x00); - - par->riva.LockUnlock(&par->riva, 0); - - par->riva.LoadStateExt(&par->riva, state); - - MISCout(par, regs->misc_output); - - for (i = 0; i < NUM_CRT_REGS; i++) { - switch (i) { - case 0x19: - case 0x20 ... 0x40: - break; - default: - CRTCout(par, i, regs->crtc[i]); - } - } - - for (i = 0; i < NUM_ATC_REGS; i++) - ATTRout(par, i, regs->attr[i]); - - for (i = 0; i < NUM_GRC_REGS; i++) - GRAout(par, i, regs->gra[i]); - - for (i = 0; i < NUM_SEQ_REGS; i++) - SEQout(par, i, regs->seq[i]); - NVTRACE_LEAVE(); -} - -/** - * riva_load_video_mode - calculate timings - * @info: pointer to fb_info object containing info for current riva board - * - * DESCRIPTION: - * Calculate some timings and then send em off to riva_load_state(). - * - * CALLED FROM: - * rivafb_set_par() - */ -static int riva_load_video_mode(struct fb_info *info) -{ - int bpp, width, hDisplaySize, hDisplay, hStart, - hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; - int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; - int rc; - struct riva_par *par = info->par; - struct riva_regs newmode; - - NVTRACE_ENTER(); - /* time to calculate */ - rivafb_blank(FB_BLANK_NORMAL, info); - - bpp = info->var.bits_per_pixel; - if (bpp == 16 && info->var.green.length == 5) - bpp = 15; - width = info->var.xres_virtual; - hDisplaySize = info->var.xres; - hDisplay = (hDisplaySize / 8) - 1; - hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; - hEnd = (hDisplaySize + info->var.right_margin + - info->var.hsync_len) / 8 - 1; - hTotal = (hDisplaySize + info->var.right_margin + - info->var.hsync_len + info->var.left_margin) / 8 - 5; - hBlankStart = hDisplay; - hBlankEnd = hTotal + 4; - - height = info->var.yres_virtual; - vDisplay = info->var.yres - 1; - vStart = info->var.yres + info->var.lower_margin - 1; - vEnd = info->var.yres + info->var.lower_margin + - info->var.vsync_len - 1; - vTotal = info->var.yres + info->var.lower_margin + - info->var.vsync_len + info->var.upper_margin + 2; - vBlankStart = vDisplay; - vBlankEnd = vTotal + 1; - dotClock = 1000000000 / info->var.pixclock; - - memcpy(&newmode, ®_template, sizeof(struct riva_regs)); - - if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) - vTotal |= 1; - - if (par->FlatPanel) { - vStart = vTotal - 3; - vEnd = vTotal - 2; - vBlankStart = vStart; - hStart = hTotal - 3; - hEnd = hTotal - 2; - hBlankEnd = hTotal + 4; - } - - newmode.crtc[0x0] = Set8Bits (hTotal); - newmode.crtc[0x1] = Set8Bits (hDisplay); - newmode.crtc[0x2] = Set8Bits (hBlankStart); - newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); - newmode.crtc[0x4] = Set8Bits (hStart); - newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) - | SetBitField (hEnd, 4: 0, 4:0); - newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); - newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) - | SetBitField (vDisplay, 8: 8, 1:1) - | SetBitField (vStart, 8: 8, 2:2) - | SetBitField (vBlankStart, 8: 8, 3:3) - | SetBit (4) - | SetBitField (vTotal, 9: 9, 5:5) - | SetBitField (vDisplay, 9: 9, 6:6) - | SetBitField (vStart, 9: 9, 7:7); - newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) - | SetBit (6); - newmode.crtc[0x10] = Set8Bits (vStart); - newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) - | SetBit (5); - newmode.crtc[0x12] = Set8Bits (vDisplay); - newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); - newmode.crtc[0x15] = Set8Bits (vBlankStart); - newmode.crtc[0x16] = Set8Bits (vBlankEnd); - - newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) - | SetBitField(vBlankStart,10:10,3:3) - | SetBitField(vStart,10:10,2:2) - | SetBitField(vDisplay,10:10,1:1) - | SetBitField(vTotal,10:10,0:0); - newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) - | SetBitField(hDisplay,8:8,1:1) - | SetBitField(hBlankStart,8:8,2:2) - | SetBitField(hStart,8:8,3:3); - newmode.ext.extra = SetBitField(vTotal,11:11,0:0) - | SetBitField(vDisplay,11:11,2:2) - | SetBitField(vStart,11:11,4:4) - | SetBitField(vBlankStart,11:11,6:6); - - if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { - int tmp = (hTotal >> 1) & ~1; - newmode.ext.interlace = Set8Bits(tmp); - newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); - } else - newmode.ext.interlace = 0xff; /* interlace off */ - - if (par->riva.Architecture >= NV_ARCH_10) - par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); - - if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) - newmode.misc_output &= ~0x40; - else - newmode.misc_output |= 0x40; - if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) - newmode.misc_output &= ~0x80; - else - newmode.misc_output |= 0x80; - - rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width, - hDisplaySize, height, dotClock); - if (rc) - goto out; - - newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & - 0xfff000ff; - if (par->FlatPanel == 1) { - newmode.ext.pixel |= (1 << 7); - newmode.ext.scale |= (1 << 8); - } - if (par->SecondCRTC) { - newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & - ~0x00001000; - newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | - 0x00001000; - newmode.ext.crtcOwner = 3; - newmode.ext.pllsel |= 0x20000800; - newmode.ext.vpll2 = newmode.ext.vpll; - } else if (par->riva.twoHeads) { - newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | - 0x00001000; - newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & - ~0x00001000; - newmode.ext.crtcOwner = 0; - newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); - } - if (par->FlatPanel == 1) { - newmode.ext.pixel |= (1 << 7); - newmode.ext.scale |= (1 << 8); - } - newmode.ext.cursorConfig = 0x02000100; - par->current_state = newmode; - riva_load_state(par, &par->current_state); - par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ - -out: - rivafb_blank(FB_BLANK_UNBLANK, info); - NVTRACE_LEAVE(); - - return rc; -} - -static void riva_update_var(struct fb_var_screeninfo *var, - const struct fb_videomode *modedb) -{ - NVTRACE_ENTER(); - var->xres = var->xres_virtual = modedb->xres; - var->yres = modedb->yres; - if (var->yres_virtual < var->yres) - var->yres_virtual = var->yres; - var->xoffset = var->yoffset = 0; - var->pixclock = modedb->pixclock; - var->left_margin = modedb->left_margin; - var->right_margin = modedb->right_margin; - var->upper_margin = modedb->upper_margin; - var->lower_margin = modedb->lower_margin; - var->hsync_len = modedb->hsync_len; - var->vsync_len = modedb->vsync_len; - var->sync = modedb->sync; - var->vmode = modedb->vmode; - NVTRACE_LEAVE(); -} - -/** - * rivafb_do_maximize - - * @info: pointer to fb_info object containing info for current riva board - * @var: - * @nom: - * @den: - * - * DESCRIPTION: - * . - * - * RETURNS: - * -EINVAL on failure, 0 on success - * - * - * CALLED FROM: - * rivafb_check_var() - */ -static int rivafb_do_maximize(struct fb_info *info, - struct fb_var_screeninfo *var, - int nom, int den) -{ - static struct { - int xres, yres; - } modes[] = { - {1600, 1280}, - {1280, 1024}, - {1024, 768}, - {800, 600}, - {640, 480}, - {-1, -1} - }; - int i; - - NVTRACE_ENTER(); - /* use highest possible virtual resolution */ - if (var->xres_virtual == -1 && var->yres_virtual == -1) { - printk(KERN_WARNING PFX - "using maximum available virtual resolution\n"); - for (i = 0; modes[i].xres != -1; i++) { - if (modes[i].xres * nom / den * modes[i].yres < - info->fix.smem_len) - break; - } - if (modes[i].xres == -1) { - printk(KERN_ERR PFX - "could not find a virtual resolution that fits into video memory!!\n"); - NVTRACE("EXIT - EINVAL error\n"); - return -EINVAL; - } - var->xres_virtual = modes[i].xres; - var->yres_virtual = modes[i].yres; - - printk(KERN_INFO PFX - "virtual resolution set to maximum of %dx%d\n", - var->xres_virtual, var->yres_virtual); - } else if (var->xres_virtual == -1) { - var->xres_virtual = (info->fix.smem_len * den / - (nom * var->yres_virtual)) & ~15; - printk(KERN_WARNING PFX - "setting virtual X resolution to %d\n", var->xres_virtual); - } else if (var->yres_virtual == -1) { - var->xres_virtual = (var->xres_virtual + 15) & ~15; - var->yres_virtual = info->fix.smem_len * den / - (nom * var->xres_virtual); - printk(KERN_WARNING PFX - "setting virtual Y resolution to %d\n", var->yres_virtual); - } else { - var->xres_virtual = (var->xres_virtual + 15) & ~15; - if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { - printk(KERN_ERR PFX - "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", - var->xres, var->yres, var->bits_per_pixel); - NVTRACE("EXIT - EINVAL error\n"); - return -EINVAL; - } - } - - if (var->xres_virtual * nom / den >= 8192) { - printk(KERN_WARNING PFX - "virtual X resolution (%d) is too high, lowering to %d\n", - var->xres_virtual, 8192 * den / nom - 16); - var->xres_virtual = 8192 * den / nom - 16; - } - - if (var->xres_virtual < var->xres) { - printk(KERN_ERR PFX - "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); - return -EINVAL; - } - - if (var->yres_virtual < var->yres) { - printk(KERN_ERR PFX - "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); - return -EINVAL; - } - if (var->yres_virtual > 0x7fff/nom) - var->yres_virtual = 0x7fff/nom; - if (var->xres_virtual > 0x7fff/nom) - var->xres_virtual = 0x7fff/nom; - NVTRACE_LEAVE(); - return 0; -} - -static void -riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) -{ - RIVA_FIFO_FREE(par->riva, Patt, 4); - NV_WR32(&par->riva.Patt->Color0, 0, clr0); - NV_WR32(&par->riva.Patt->Color1, 0, clr1); - NV_WR32(par->riva.Patt->Monochrome, 0, pat0); - NV_WR32(par->riva.Patt->Monochrome, 4, pat1); -} - -/* acceleration routines */ -static inline void wait_for_idle(struct riva_par *par) -{ - while (par->riva.Busy(&par->riva)); -} - -/* - * Set ROP. Translate X rop into ROP3. Internal routine. - */ -static void -riva_set_rop_solid(struct riva_par *par, int rop) -{ - riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); - RIVA_FIFO_FREE(par->riva, Rop, 1); - NV_WR32(&par->riva.Rop->Rop3, 0, rop); - -} - -static void riva_setup_accel(struct fb_info *info) -{ - struct riva_par *par = info->par; - - RIVA_FIFO_FREE(par->riva, Clip, 2); - NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); - NV_WR32(&par->riva.Clip->WidthHeight, 0, - (info->var.xres_virtual & 0xffff) | - (info->var.yres_virtual << 16)); - riva_set_rop_solid(par, 0xcc); - wait_for_idle(par); -} - -/** - * riva_get_cmap_len - query current color map length - * @var: standard kernel fb changeable data - * - * DESCRIPTION: - * Get current color map length. - * - * RETURNS: - * Length of color map - * - * CALLED FROM: - * rivafb_setcolreg() - */ -static int riva_get_cmap_len(const struct fb_var_screeninfo *var) -{ - int rc = 256; /* reasonable default */ - - switch (var->green.length) { - case 8: - rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ - break; - case 5: - rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ - break; - case 6: - rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ - break; - default: - /* should not occur */ - break; - } - return rc; -} - -/* ------------------------------------------------------------------------- * - * - * framebuffer operations - * - * ------------------------------------------------------------------------- */ - -static int rivafb_open(struct fb_info *info, int user) -{ - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - mutex_lock(&par->open_lock); - if (!par->ref_count) { -#ifdef CONFIG_X86 - memset(&par->state, 0, sizeof(struct vgastate)); - par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; - /* save the DAC for Riva128 */ - if (par->riva.Architecture == NV_ARCH_03) - par->state.flags |= VGA_SAVE_CMAP; - save_vga(&par->state); -#endif - /* vgaHWunlock() + riva unlock (0x7F) */ - CRTCout(par, 0x11, 0xFF); - par->riva.LockUnlock(&par->riva, 0); - - riva_save_state(par, &par->initial_state); - } - par->ref_count++; - mutex_unlock(&par->open_lock); - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_release(struct fb_info *info, int user) -{ - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - mutex_lock(&par->open_lock); - if (!par->ref_count) { - mutex_unlock(&par->open_lock); - return -EINVAL; - } - if (par->ref_count == 1) { - par->riva.LockUnlock(&par->riva, 0); - par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); - riva_load_state(par, &par->initial_state); -#ifdef CONFIG_X86 - restore_vga(&par->state); -#endif - par->riva.LockUnlock(&par->riva, 1); - } - par->ref_count--; - mutex_unlock(&par->open_lock); - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -{ - const struct fb_videomode *mode; - struct riva_par *par = info->par; - int nom, den; /* translating from pixels->bytes */ - int mode_valid = 0; - - NVTRACE_ENTER(); - if (!var->pixclock) - return -EINVAL; - - switch (var->bits_per_pixel) { - case 1 ... 8: - var->red.offset = var->green.offset = var->blue.offset = 0; - var->red.length = var->green.length = var->blue.length = 8; - var->bits_per_pixel = 8; - nom = den = 1; - break; - case 9 ... 15: - var->green.length = 5; - fallthrough; - case 16: - var->bits_per_pixel = 16; - /* The Riva128 supports RGB555 only */ - if (par->riva.Architecture == NV_ARCH_03) - var->green.length = 5; - if (var->green.length == 5) { - /* 0rrrrrgg gggbbbbb */ - var->red.offset = 10; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 5; - var->blue.length = 5; - } else { - /* rrrrrggg gggbbbbb */ - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - } - nom = 2; - den = 1; - break; - case 17 ... 32: - var->red.length = var->green.length = var->blue.length = 8; - var->bits_per_pixel = 32; - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - nom = 4; - den = 1; - break; - default: - printk(KERN_ERR PFX - "mode %dx%dx%d rejected...color depth not supported.\n", - var->xres, var->yres, var->bits_per_pixel); - NVTRACE("EXIT, returning -EINVAL\n"); - return -EINVAL; - } - - if (!strictmode) { - if (!info->monspecs.vfmax || !info->monspecs.hfmax || - !info->monspecs.dclkmax || !fb_validate_mode(var, info)) - mode_valid = 1; - } - - /* calculate modeline if supported by monitor */ - if (!mode_valid && info->monspecs.gtf) { - if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) - mode_valid = 1; - } - - if (!mode_valid) { - mode = fb_find_best_mode(var, &info->modelist); - if (mode) { - riva_update_var(var, mode); - mode_valid = 1; - } - } - - if (!mode_valid && info->monspecs.modedb_len) - return -EINVAL; - - if (var->xres_virtual < var->xres) - var->xres_virtual = var->xres; - if (var->yres_virtual <= var->yres) - var->yres_virtual = -1; - if (rivafb_do_maximize(info, var, nom, den) < 0) - return -EINVAL; - - /* truncate xoffset and yoffset to maximum if too high */ - if (var->xoffset > var->xres_virtual - var->xres) - var->xoffset = var->xres_virtual - var->xres - 1; - - if (var->yoffset > var->yres_virtual - var->yres) - var->yoffset = var->yres_virtual - var->yres - 1; - - var->red.msb_right = - var->green.msb_right = - var->blue.msb_right = - var->transp.offset = var->transp.length = var->transp.msb_right = 0; - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_set_par(struct fb_info *info) -{ - struct riva_par *par = info->par; - int rc = 0; - - NVTRACE_ENTER(); - /* vgaHWunlock() + riva unlock (0x7F) */ - CRTCout(par, 0x11, 0xFF); - par->riva.LockUnlock(&par->riva, 0); - rc = riva_load_video_mode(info); - if (rc) - goto out; - if(!(info->flags & FBINFO_HWACCEL_DISABLED)) - riva_setup_accel(info); - - par->cursor_reset = 1; - info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); - info->fix.visual = (info->var.bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - - if (info->flags & FBINFO_HWACCEL_DISABLED) - info->pixmap.scan_align = 1; - else - info->pixmap.scan_align = 4; - -out: - NVTRACE_LEAVE(); - return rc; -} - -/** - * rivafb_pan_display - * @var: standard kernel fb changeable data - * @con: TODO - * @info: pointer to fb_info object containing info for current riva board - * - * DESCRIPTION: - * Pan (or wrap, depending on the `vmode' field) the display using the - * `xoffset' and `yoffset' fields of the `var' structure. - * If the values don't fit, return -EINVAL. - * - * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag - */ -static int rivafb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct riva_par *par = info->par; - unsigned int base; - - NVTRACE_ENTER(); - base = var->yoffset * info->fix.line_length + var->xoffset; - par->riva.SetStartAddress(&par->riva, base); - NVTRACE_LEAVE(); - return 0; -} - -static int rivafb_blank(int blank, struct fb_info *info) -{ - struct riva_par *par= info->par; - unsigned char tmp, vesa; - - tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ - vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ - - NVTRACE_ENTER(); - - if (blank) - tmp |= 0x20; - - switch (blank) { - case FB_BLANK_UNBLANK: - case FB_BLANK_NORMAL: - break; - case FB_BLANK_VSYNC_SUSPEND: - vesa |= 0x80; - break; - case FB_BLANK_HSYNC_SUSPEND: - vesa |= 0x40; - break; - case FB_BLANK_POWERDOWN: - vesa |= 0xc0; - break; - } - - SEQout(par, 0x01, tmp); - CRTCout(par, 0x1a, vesa); - - NVTRACE_LEAVE(); - - return 0; -} - -/** - * rivafb_setcolreg - * @regno: register index - * @red: red component - * @green: green component - * @blue: blue component - * @transp: transparency - * @info: pointer to fb_info object containing info for current riva board - * - * DESCRIPTION: - * Set a single color register. The values supplied have a 16 bit - * magnitude. - * - * RETURNS: - * Return != 0 for invalid regno. - * - * CALLED FROM: - * fbcmap.c:fb_set_cmap() - */ -static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct riva_par *par = info->par; - RIVA_HW_INST *chip = &par->riva; - int i; - - if (regno >= riva_get_cmap_len(&info->var)) - return -EINVAL; - - if (info->var.grayscale) { - /* gray = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = - (red * 77 + green * 151 + blue * 28) >> 8; - } - - if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { - ((u32 *) info->pseudo_palette)[regno] = - (regno << info->var.red.offset) | - (regno << info->var.green.offset) | - (regno << info->var.blue.offset); - /* - * The Riva128 2D engine requires color information in - * TrueColor format even if framebuffer is in DirectColor - */ - if (par->riva.Architecture == NV_ARCH_03) { - switch (info->var.bits_per_pixel) { - case 16: - par->palette[regno] = ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - break; - case 32: - par->palette[regno] = ((red & 0xff00) << 8) | - ((green & 0xff00)) | - ((blue & 0xff00) >> 8); - break; - } - } - } - - switch (info->var.bits_per_pixel) { - case 8: - /* "transparent" stuff is completely ignored. */ - riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); - break; - case 16: - if (info->var.green.length == 5) { - for (i = 0; i < 8; i++) { - riva_wclut(chip, regno*8+i, red >> 8, - green >> 8, blue >> 8); - } - } else { - u8 r, g, b; - - if (regno < 32) { - for (i = 0; i < 8; i++) { - riva_wclut(chip, regno*8+i, - red >> 8, green >> 8, - blue >> 8); - } - } - riva_rclut(chip, regno*4, &r, &g, &b); - for (i = 0; i < 4; i++) - riva_wclut(chip, regno*4+i, r, - green >> 8, b); - } - break; - case 32: - riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); - break; - default: - /* do nothing */ - break; - } - return 0; -} - -/** - * rivafb_fillrect - hardware accelerated color fill function - * @info: pointer to fb_info structure - * @rect: pointer to fb_fillrect structure - * - * DESCRIPTION: - * This function fills up a region of framebuffer memory with a solid - * color with a choice of two different ROP's, copy or invert. - * - * CALLED FROM: - * framebuffer hook - */ -static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) -{ - struct riva_par *par = info->par; - u_int color, rop = 0; - - if ((info->flags & FBINFO_HWACCEL_DISABLED)) { - cfb_fillrect(info, rect); - return; - } - - if (info->var.bits_per_pixel == 8) - color = rect->color; - else { - if (par->riva.Architecture != NV_ARCH_03) - color = ((u32 *)info->pseudo_palette)[rect->color]; - else - color = par->palette[rect->color]; - } - - switch (rect->rop) { - case ROP_XOR: - rop = 0x66; - break; - case ROP_COPY: - default: - rop = 0xCC; - break; - } - - riva_set_rop_solid(par, rop); - - RIVA_FIFO_FREE(par->riva, Bitmap, 1); - NV_WR32(&par->riva.Bitmap->Color1A, 0, color); - - RIVA_FIFO_FREE(par->riva, Bitmap, 2); - NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, - (rect->dx << 16) | rect->dy); - mb(); - NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, - (rect->width << 16) | rect->height); - mb(); - riva_set_rop_solid(par, 0xcc); - -} - -/** - * rivafb_copyarea - hardware accelerated blit function - * @info: pointer to fb_info structure - * @region: pointer to fb_copyarea structure - * - * DESCRIPTION: - * This copies an area of pixels from one location to another - * - * CALLED FROM: - * framebuffer hook - */ -static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) -{ - struct riva_par *par = info->par; - - if ((info->flags & FBINFO_HWACCEL_DISABLED)) { - cfb_copyarea(info, region); - return; - } - - RIVA_FIFO_FREE(par->riva, Blt, 3); - NV_WR32(&par->riva.Blt->TopLeftSrc, 0, - (region->sy << 16) | region->sx); - NV_WR32(&par->riva.Blt->TopLeftDst, 0, - (region->dy << 16) | region->dx); - mb(); - NV_WR32(&par->riva.Blt->WidthHeight, 0, - (region->height << 16) | region->width); - mb(); -} - -static inline void convert_bgcolor_16(u32 *col) -{ - *col = ((*col & 0x0000F800) << 8) - | ((*col & 0x00007E0) << 5) - | ((*col & 0x0000001F) << 3) - | 0xFF000000; - mb(); -} - -/** - * rivafb_imageblit: hardware accelerated color expand function - * @info: pointer to fb_info structure - * @image: pointer to fb_image structure - * - * DESCRIPTION: - * If the source is a monochrome bitmap, the function fills up a a region - * of framebuffer memory with pixels whose color is determined by the bit - * setting of the bitmap, 1 - foreground, 0 - background. - * - * If the source is not a monochrome bitmap, color expansion is not done. - * In this case, it is channeled to a software function. - * - * CALLED FROM: - * framebuffer hook - */ -static void rivafb_imageblit(struct fb_info *info, - const struct fb_image *image) -{ - struct riva_par *par = info->par; - u32 fgx = 0, bgx = 0, width, tmp; - u8 *cdat = (u8 *) image->data; - volatile u32 __iomem *d; - int i, size; - - if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { - cfb_imageblit(info, image); - return; - } - - switch (info->var.bits_per_pixel) { - case 8: - fgx = image->fg_color; - bgx = image->bg_color; - break; - case 16: - case 32: - if (par->riva.Architecture != NV_ARCH_03) { - fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; - bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; - } else { - fgx = par->palette[image->fg_color]; - bgx = par->palette[image->bg_color]; - } - if (info->var.green.length == 6) - convert_bgcolor_16(&bgx); - break; - } - - RIVA_FIFO_FREE(par->riva, Bitmap, 7); - NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, - (image->dy << 16) | (image->dx & 0xFFFF)); - NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, - (((image->dy + image->height) << 16) | - ((image->dx + image->width) & 0xffff))); - NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); - NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); - NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, - (image->height << 16) | ((image->width + 31) & ~31)); - NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, - (image->height << 16) | ((image->width + 31) & ~31)); - NV_WR32(&par->riva.Bitmap->PointE, 0, - (image->dy << 16) | (image->dx & 0xFFFF)); - - d = &par->riva.Bitmap->MonochromeData01E; - - width = (image->width + 31)/32; - size = width * image->height; - while (size >= 16) { - RIVA_FIFO_FREE(par->riva, Bitmap, 16); - for (i = 0; i < 16; i++) { - tmp = *((u32 *)cdat); - cdat = (u8 *)((u32 *)cdat + 1); - reverse_order(&tmp); - NV_WR32(d, i*4, tmp); - } - size -= 16; - } - if (size) { - RIVA_FIFO_FREE(par->riva, Bitmap, size); - for (i = 0; i < size; i++) { - tmp = *((u32 *) cdat); - cdat = (u8 *)((u32 *)cdat + 1); - reverse_order(&tmp); - NV_WR32(d, i*4, tmp); - } - } -} - -/** - * rivafb_cursor - hardware cursor function - * @info: pointer to info structure - * @cursor: pointer to fbcursor structure - * - * DESCRIPTION: - * A cursor function that supports displaying a cursor image via hardware. - * Within the kernel, copy and invert rops are supported. If exported - * to user space, only the copy rop will be supported. - * - * CALLED FROM - * framebuffer hook - */ -static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - struct riva_par *par = info->par; - u8 data[MAX_CURS * MAX_CURS/8]; - int i, set = cursor->set; - u16 fg, bg; - - if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) - return -ENXIO; - - par->riva.ShowHideCursor(&par->riva, 0); - - if (par->cursor_reset) { - set = FB_CUR_SETALL; - par->cursor_reset = 0; - } - - if (set & FB_CUR_SETSIZE) - memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); - - if (set & FB_CUR_SETPOS) { - u32 xx, yy, temp; - - yy = cursor->image.dy - info->var.yoffset; - xx = cursor->image.dx - info->var.xoffset; - temp = xx & 0xFFFF; - temp |= yy << 16; - - NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); - } - - - if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { - u32 bg_idx = cursor->image.bg_color; - u32 fg_idx = cursor->image.fg_color; - u32 s_pitch = (cursor->image.width+7) >> 3; - u32 d_pitch = MAX_CURS/8; - u8 *dat = (u8 *) cursor->image.data; - u8 *msk = (u8 *) cursor->mask; - u8 *src; - - src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC); - - if (src) { - switch (cursor->rop) { - case ROP_XOR: - for (i = 0; i < s_pitch * cursor->image.height; i++) - src[i] = dat[i] ^ msk[i]; - break; - case ROP_COPY: - default: - for (i = 0; i < s_pitch * cursor->image.height; i++) - src[i] = dat[i] & msk[i]; - break; - } - - fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, - cursor->image.height); - - bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | - ((info->cmap.green[bg_idx] & 0xf8) << 2) | - ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | - 1 << 15; - - fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | - ((info->cmap.green[fg_idx] & 0xf8) << 2) | - ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | - 1 << 15; - - par->riva.LockUnlock(&par->riva, 0); - - rivafb_load_cursor_image(par, data, bg, fg, - cursor->image.width, - cursor->image.height); - kfree(src); - } - } - - if (cursor->enable) - par->riva.ShowHideCursor(&par->riva, 1); - - return 0; -} - -static int rivafb_sync(struct fb_info *info) -{ - struct riva_par *par = info->par; - - wait_for_idle(par); - return 0; -} - -/* ------------------------------------------------------------------------- * - * - * initialization helper functions - * - * ------------------------------------------------------------------------- */ - -/* kernel interface */ -static const struct fb_ops riva_fb_ops = { - .owner = THIS_MODULE, - .fb_open = rivafb_open, - .fb_release = rivafb_release, - .fb_check_var = rivafb_check_var, - .fb_set_par = rivafb_set_par, - .fb_setcolreg = rivafb_setcolreg, - .fb_pan_display = rivafb_pan_display, - .fb_blank = rivafb_blank, - .fb_fillrect = rivafb_fillrect, - .fb_copyarea = rivafb_copyarea, - .fb_imageblit = rivafb_imageblit, - .fb_cursor = rivafb_cursor, - .fb_sync = rivafb_sync, -}; - -static int riva_set_fbinfo(struct fb_info *info) -{ - unsigned int cmap_len; - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - info->flags = FBINFO_DEFAULT - | FBINFO_HWACCEL_XPAN - | FBINFO_HWACCEL_YPAN - | FBINFO_HWACCEL_COPYAREA - | FBINFO_HWACCEL_FILLRECT - | FBINFO_HWACCEL_IMAGEBLIT; - - /* Accel seems to not work properly on NV30 yet...*/ - if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { - printk(KERN_DEBUG PFX "disabling acceleration\n"); - info->flags |= FBINFO_HWACCEL_DISABLED; - } - - info->var = rivafb_default_var; - info->fix.visual = (info->var.bits_per_pixel == 8) ? - FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; - - info->pseudo_palette = par->pseudo_palette; - - cmap_len = riva_get_cmap_len(&info->var); - fb_alloc_cmap(&info->cmap, cmap_len, 0); - - info->pixmap.size = 8 * 1024; - info->pixmap.buf_align = 4; - info->pixmap.access_align = 32; - info->pixmap.flags = FB_PIXMAP_SYSTEM; - info->var.yres_virtual = -1; - NVTRACE_LEAVE(); - return (rivafb_check_var(&info->var, info)); -} - -static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) -{ - struct riva_par *par = info->par; - struct device_node *dp; - const unsigned char *pedid = NULL; - const unsigned char *disptype = NULL; - static char *propnames[] = { - "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; - int i; - - NVTRACE_ENTER(); - dp = pci_device_to_OF_node(pd); - for (; dp != NULL; dp = dp->child) { - disptype = of_get_property(dp, "display-type", NULL); - if (disptype == NULL) - continue; - if (strncmp(disptype, "LCD", 3) != 0) - continue; - for (i = 0; propnames[i] != NULL; ++i) { - pedid = of_get_property(dp, propnames[i], NULL); - if (pedid != NULL) { - par->EDID = (unsigned char *)pedid; - NVTRACE("LCD found.\n"); - return 1; - } - } - } - NVTRACE_LEAVE(); - return 0; -} - -#if defined(CONFIG_FB_RIVA_I2C) -static int riva_get_EDID_i2c(struct fb_info *info) -{ - struct riva_par *par = info->par; - struct fb_var_screeninfo var; - int i; - - NVTRACE_ENTER(); - par->riva.LockUnlock(&par->riva, 0); - riva_create_i2c_busses(par); - for (i = 0; i < 3; i++) { - if (!par->chan[i].par) - continue; - riva_probe_i2c_connector(par, i, &par->EDID); - if (par->EDID && !fb_parse_edid(par->EDID, &var)) { - printk(PFX "Found EDID Block from BUS %i\n", i); - break; - } - } - - NVTRACE_LEAVE(); - return (par->EDID) ? 1 : 0; -} -#endif /* CONFIG_FB_RIVA_I2C */ - -static void riva_update_default_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct fb_monspecs *specs = &info->monspecs; - struct fb_videomode modedb; - - NVTRACE_ENTER(); - /* respect mode options */ - if (mode_option) { - fb_find_mode(var, info, mode_option, - specs->modedb, specs->modedb_len, - NULL, 8); - } else if (specs->modedb != NULL) { - /* get first mode in database as fallback */ - modedb = specs->modedb[0]; - /* get preferred timing */ - if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { - int i; - - for (i = 0; i < specs->modedb_len; i++) { - if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { - modedb = specs->modedb[i]; - break; - } - } - } - var->bits_per_pixel = 8; - riva_update_var(var, &modedb); - } - NVTRACE_LEAVE(); -} - - -static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) -{ - NVTRACE_ENTER(); - if (riva_get_EDID_OF(info, pdev)) { - NVTRACE_LEAVE(); - return; - } - if (IS_ENABLED(CONFIG_OF)) - printk(PFX "could not retrieve EDID from OF\n"); -#if defined(CONFIG_FB_RIVA_I2C) - if (!riva_get_EDID_i2c(info)) - printk(PFX "could not retrieve EDID from DDC/I2C\n"); -#endif - NVTRACE_LEAVE(); -} - - -static void riva_get_edidinfo(struct fb_info *info) -{ - struct fb_var_screeninfo *var = &rivafb_default_var; - struct riva_par *par = info->par; - - fb_edid_to_monspecs(par->EDID, &info->monspecs); - fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, - &info->modelist); - riva_update_default_var(var, info); - - /* if user specified flatpanel, we respect that */ - if (info->monspecs.input & FB_DISP_DDI) - par->FlatPanel = 1; -} - -/* ------------------------------------------------------------------------- * - * - * PCI bus - * - * ------------------------------------------------------------------------- */ - -static u32 riva_get_arch(struct pci_dev *pd) -{ - u32 arch = 0; - - switch (pd->device & 0x0ff0) { - case 0x0100: /* GeForce 256 */ - case 0x0110: /* GeForce2 MX */ - case 0x0150: /* GeForce2 */ - case 0x0170: /* GeForce4 MX */ - case 0x0180: /* GeForce4 MX (8x AGP) */ - case 0x01A0: /* nForce */ - case 0x01F0: /* nForce2 */ - arch = NV_ARCH_10; - break; - case 0x0200: /* GeForce3 */ - case 0x0250: /* GeForce4 Ti */ - case 0x0280: /* GeForce4 Ti (8x AGP) */ - arch = NV_ARCH_20; - break; - case 0x0300: /* GeForceFX 5800 */ - case 0x0310: /* GeForceFX 5600 */ - case 0x0320: /* GeForceFX 5200 */ - case 0x0330: /* GeForceFX 5900 */ - case 0x0340: /* GeForceFX 5700 */ - arch = NV_ARCH_30; - break; - case 0x0020: /* TNT, TNT2 */ - arch = NV_ARCH_04; - break; - case 0x0010: /* Riva128 */ - arch = NV_ARCH_03; - break; - default: /* unknown architecture */ - break; - } - return arch; -} - -static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) -{ - struct riva_par *default_par; - struct fb_info *info; - int ret; - - NVTRACE_ENTER(); - assert(pd != NULL); - - info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); - if (!info) { - ret = -ENOMEM; - goto err_ret; - } - default_par = info->par; - default_par->pdev = pd; - - info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); - if (info->pixmap.addr == NULL) { - ret = -ENOMEM; - goto err_framebuffer_release; - } - - ret = pci_enable_device(pd); - if (ret < 0) { - printk(KERN_ERR PFX "cannot enable PCI device\n"); - goto err_free_pixmap; - } - - ret = pci_request_regions(pd, "rivafb"); - if (ret < 0) { - printk(KERN_ERR PFX "cannot request PCI regions\n"); - goto err_disable_device; - } - - mutex_init(&default_par->open_lock); - default_par->riva.Architecture = riva_get_arch(pd); - - default_par->Chipset = (pd->vendor << 16) | pd->device; - printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); - - if(default_par->riva.Architecture == 0) { - printk(KERN_ERR PFX "unknown NV_ARCH\n"); - ret=-ENODEV; - goto err_release_region; - } - if(default_par->riva.Architecture == NV_ARCH_10 || - default_par->riva.Architecture == NV_ARCH_20 || - default_par->riva.Architecture == NV_ARCH_30) { - sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); - } else { - sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); - } - - default_par->FlatPanel = flatpanel; - if (flatpanel == 1) - printk(KERN_INFO PFX "flatpanel support enabled\n"); - default_par->forceCRTC = forceCRTC; - - rivafb_fix.mmio_len = pci_resource_len(pd, 0); - rivafb_fix.smem_len = pci_resource_len(pd, 1); - - { - /* enable IO and mem if not already done */ - unsigned short cmd; - - pci_read_config_word(pd, PCI_COMMAND, &cmd); - cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - pci_write_config_word(pd, PCI_COMMAND, cmd); - } - - rivafb_fix.mmio_start = pci_resource_start(pd, 0); - rivafb_fix.smem_start = pci_resource_start(pd, 1); - - default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, - rivafb_fix.mmio_len); - if (!default_par->ctrl_base) { - printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); - ret = -EIO; - goto err_release_region; - } - - switch (default_par->riva.Architecture) { - case NV_ARCH_03: - /* Riva128's PRAMIN is in the "framebuffer" space - * Since these cards were never made with more than 8 megabytes - * we can safely allocate this separately. - */ - default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); - if (!default_par->riva.PRAMIN) { - printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); - ret = -EIO; - goto err_iounmap_ctrl_base; - } - break; - case NV_ARCH_04: - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - default_par->riva.PCRTC0 = - (u32 __iomem *)(default_par->ctrl_base + 0x00600000); - default_par->riva.PRAMIN = - (u32 __iomem *)(default_par->ctrl_base + 0x00710000); - break; - } - riva_common_setup(default_par); - - if (default_par->riva.Architecture == NV_ARCH_03) { - default_par->riva.PCRTC = default_par->riva.PCRTC0 - = default_par->riva.PGRAPH; - } - - rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; - default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; - info->screen_base = ioremap_wc(rivafb_fix.smem_start, - rivafb_fix.smem_len); - if (!info->screen_base) { - printk(KERN_ERR PFX "cannot ioremap FB base\n"); - ret = -EIO; - goto err_iounmap_pramin; - } - - if (!nomtrr) - default_par->wc_cookie = - arch_phys_wc_add(rivafb_fix.smem_start, - rivafb_fix.smem_len); - - info->fbops = &riva_fb_ops; - info->fix = rivafb_fix; - riva_get_EDID(info, pd); - riva_get_edidinfo(info); - - ret=riva_set_fbinfo(info); - if (ret < 0) { - printk(KERN_ERR PFX "error setting initial video mode\n"); - goto err_iounmap_screen_base; - } - - fb_destroy_modedb(info->monspecs.modedb); - info->monspecs.modedb = NULL; - - pci_set_drvdata(pd, info); - - if (backlight) - riva_bl_init(info->par); - - ret = register_framebuffer(info); - if (ret < 0) { - printk(KERN_ERR PFX - "error registering riva framebuffer\n"); - goto err_iounmap_screen_base; - } - - printk(KERN_INFO PFX - "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", - info->fix.id, - RIVAFB_VERSION, - info->fix.smem_len / (1024 * 1024), - info->fix.smem_start); - - NVTRACE_LEAVE(); - return 0; - -err_iounmap_screen_base: -#ifdef CONFIG_FB_RIVA_I2C - riva_delete_i2c_busses(info->par); -#endif - iounmap(info->screen_base); -err_iounmap_pramin: - if (default_par->riva.Architecture == NV_ARCH_03) - iounmap(default_par->riva.PRAMIN); -err_iounmap_ctrl_base: - iounmap(default_par->ctrl_base); -err_release_region: - pci_release_regions(pd); -err_disable_device: -err_free_pixmap: - kfree(info->pixmap.addr); -err_framebuffer_release: - framebuffer_release(info); -err_ret: - return ret; -} - -static void rivafb_remove(struct pci_dev *pd) -{ - struct fb_info *info = pci_get_drvdata(pd); - struct riva_par *par = info->par; - - NVTRACE_ENTER(); - -#ifdef CONFIG_FB_RIVA_I2C - riva_delete_i2c_busses(par); - kfree(par->EDID); -#endif - - unregister_framebuffer(info); - - riva_bl_exit(info); - arch_phys_wc_del(par->wc_cookie); - iounmap(par->ctrl_base); - iounmap(info->screen_base); - if (par->riva.Architecture == NV_ARCH_03) - iounmap(par->riva.PRAMIN); - pci_release_regions(pd); - kfree(info->pixmap.addr); - framebuffer_release(info); - NVTRACE_LEAVE(); -} - -/* ------------------------------------------------------------------------- * - * - * initialization - * - * ------------------------------------------------------------------------- */ - -#ifndef MODULE -static int rivafb_setup(char *options) -{ - char *this_opt; - - NVTRACE_ENTER(); - if (!options || !*options) - return 0; - - while ((this_opt = strsep(&options, ",")) != NULL) { - if (!strncmp(this_opt, "forceCRTC", 9)) { - char *p; - - p = this_opt + 9; - if (!*p || !*(++p)) continue; - forceCRTC = *p - '0'; - if (forceCRTC < 0 || forceCRTC > 1) - forceCRTC = -1; - } else if (!strncmp(this_opt, "flatpanel", 9)) { - flatpanel = 1; - } else if (!strncmp(this_opt, "backlight:", 10)) { - backlight = simple_strtoul(this_opt+10, NULL, 0); - } else if (!strncmp(this_opt, "nomtrr", 6)) { - nomtrr = 1; - } else if (!strncmp(this_opt, "strictmode", 10)) { - strictmode = 1; - } else if (!strncmp(this_opt, "noaccel", 7)) { - noaccel = 1; - } else - mode_option = this_opt; - } - NVTRACE_LEAVE(); - return 0; -} -#endif /* !MODULE */ - -static struct pci_driver rivafb_driver = { - .name = "rivafb", - .id_table = rivafb_pci_tbl, - .probe = rivafb_probe, - .remove = rivafb_remove, -}; - - - -/* ------------------------------------------------------------------------- * - * - * modularization - * - * ------------------------------------------------------------------------- */ - -static int rivafb_init(void) -{ -#ifndef MODULE - char *option = NULL; - - if (fb_get_options("rivafb", &option)) - return -ENODEV; - rivafb_setup(option); -#endif - return pci_register_driver(&rivafb_driver); -} - - -module_init(rivafb_init); - -static void __exit rivafb_exit(void) -{ - pci_unregister_driver(&rivafb_driver); -} - -module_exit(rivafb_exit); - -module_param(noaccel, bool, 0); -MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); -module_param(flatpanel, int, 0); -MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); -module_param(forceCRTC, int, 0); -MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); -module_param(nomtrr, bool, 0); -MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); -module_param(strictmode, bool, 0); -MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); - -MODULE_AUTHOR("Ani Joshi, maintainer"); -MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/riva/nv_driver.c b/drivers/video/fbdev/riva/nv_driver.c deleted file mode 100644 index a3d9c66973ad..000000000000 --- a/drivers/video/fbdev/riva/nv_driver.c +++ /dev/null @@ -1,423 +0,0 @@ -/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */ -/* - * Copyright 1996-1997 David J. McKay - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen - <jpaana@s2.org> */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0 -5 20:47:06 mvojkovi Exp $ */ - -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> -#include "nv_type.h" -#include "rivafb.h" -#include "nvreg.h" - -#define PFX "rivafb: " - -static inline unsigned char MISCin(struct riva_par *par) -{ - return (VGA_RD08(par->riva.PVIO, 0x3cc)); -} - -static Bool -riva_is_connected(struct riva_par *par, Bool second) -{ - volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; - U032 reg52C, reg608; - Bool present; - - if(second) PRAMDAC += 0x800; - - reg52C = NV_RD32(PRAMDAC, 0x052C); - reg608 = NV_RD32(PRAMDAC, 0x0608); - - NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000); - - NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE); - mdelay(1); - NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); - - NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); - NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); - - mdelay(1); - - present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE; - - NV_WR32(par->riva.PRAMDAC0, 0x0608, - NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); - - NV_WR32(PRAMDAC, 0x052C, reg52C); - NV_WR32(PRAMDAC, 0x0608, reg608); - - return present; -} - -static void -riva_override_CRTC(struct riva_par *par) -{ - printk(KERN_INFO PFX - "Detected CRTC controller %i being used\n", - par->SecondCRTC ? 1 : 0); - - if(par->forceCRTC != -1) { - printk(KERN_INFO PFX - "Forcing usage of CRTC %i\n", par->forceCRTC); - par->SecondCRTC = par->forceCRTC; - } -} - -static void -riva_is_second(struct riva_par *par) -{ - if (par->FlatPanel == 1) { - switch(par->Chipset & 0xffff) { - case 0x0174: - case 0x0175: - case 0x0176: - case 0x0177: - case 0x0179: - case 0x017C: - case 0x017D: - case 0x0186: - case 0x0187: - /* this might not be a good default for the chips below */ - case 0x0286: - case 0x028C: - case 0x0316: - case 0x0317: - case 0x031A: - case 0x031B: - case 0x031C: - case 0x031D: - case 0x031E: - case 0x031F: - case 0x0324: - case 0x0325: - case 0x0328: - case 0x0329: - case 0x032C: - case 0x032D: - par->SecondCRTC = TRUE; - break; - default: - par->SecondCRTC = FALSE; - break; - } - } else { - if(riva_is_connected(par, 0)) { - - if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100) - par->SecondCRTC = TRUE; - else - par->SecondCRTC = FALSE; - } else - if (riva_is_connected(par, 1)) { - if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100) - par->SecondCRTC = TRUE; - else - par->SecondCRTC = FALSE; - } else /* default */ - par->SecondCRTC = FALSE; - } - riva_override_CRTC(par); -} - -unsigned long riva_get_memlen(struct riva_par *par) -{ - RIVA_HW_INST *chip = &par->riva; - unsigned long memlen = 0; - unsigned int chipset = par->Chipset; - struct pci_dev* dev; - u32 amt; - int domain = pci_domain_nr(par->pdev->bus); - - switch (chip->Architecture) { - case NV_ARCH_03: - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { - if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) - && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { - /* - * SDRAM 128 ZX. - */ - switch (NV_RD32(chip->PFB,0x00000000) & 0x03) { - case 2: - memlen = 1024 * 4; - break; - case 1: - memlen = 1024 * 2; - break; - default: - memlen = 1024 * 8; - break; - } - } else { - memlen = 1024 * 8; - } - } else { - /* - * SGRAM 128. - */ - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { - case 0: - memlen = 1024 * 8; - break; - case 2: - memlen = 1024 * 4; - break; - default: - memlen = 1024 * 2; - break; - } - } - break; - case NV_ARCH_04: - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) { - memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) * - 1024 * 2 + 1024 * 2; - } else { - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { - case 0: - memlen = 1024 * 32; - break; - case 1: - memlen = 1024 * 4; - break; - case 2: - memlen = 1024 * 8; - break; - case 3: - default: - memlen = 1024 * 16; - break; - } - } - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - if(chipset == NV_CHIP_IGEFORCE2) { - - dev = pci_get_domain_bus_and_slot(domain, 0, 1); - pci_read_config_dword(dev, 0x7C, &amt); - pci_dev_put(dev); - memlen = (((amt >> 6) & 31) + 1) * 1024; - } else if (chipset == NV_CHIP_0x01F0) { - dev = pci_get_domain_bus_and_slot(domain, 0, 1); - pci_read_config_dword(dev, 0x84, &amt); - pci_dev_put(dev); - memlen = (((amt >> 4) & 127) + 1) * 1024; - } else { - switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & - 0x000000FF){ - case 0x02: - memlen = 1024 * 2; - break; - case 0x04: - memlen = 1024 * 4; - break; - case 0x08: - memlen = 1024 * 8; - break; - case 0x10: - memlen = 1024 * 16; - break; - case 0x20: - memlen = 1024 * 32; - break; - case 0x40: - memlen = 1024 * 64; - break; - case 0x80: - memlen = 1024 * 128; - break; - default: - memlen = 1024 * 16; - break; - } - } - break; - } - return memlen; -} - -unsigned long riva_get_maxdclk(struct riva_par *par) -{ - RIVA_HW_INST *chip = &par->riva; - unsigned long dclk = 0; - - switch (chip->Architecture) { - case NV_ARCH_03: - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { - if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) - && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { - /* - * SDRAM 128 ZX. - */ - dclk = 800000; - } else { - dclk = 1000000; - } - } else { - /* - * SGRAM 128. - */ - dclk = 1000000; - } - break; - case NV_ARCH_04: - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) { - case 3: - dclk = 800000; - break; - default: - dclk = 1000000; - break; - } - break; - } - return dclk; -} - -void -riva_common_setup(struct riva_par *par) -{ - par->riva.EnableIRQ = 0; - par->riva.PRAMDAC0 = - (volatile U032 __iomem *)(par->ctrl_base + 0x00680000); - par->riva.PFB = - (volatile U032 __iomem *)(par->ctrl_base + 0x00100000); - par->riva.PFIFO = - (volatile U032 __iomem *)(par->ctrl_base + 0x00002000); - par->riva.PGRAPH = - (volatile U032 __iomem *)(par->ctrl_base + 0x00400000); - par->riva.PEXTDEV = - (volatile U032 __iomem *)(par->ctrl_base + 0x00101000); - par->riva.PTIMER = - (volatile U032 __iomem *)(par->ctrl_base + 0x00009000); - par->riva.PMC = - (volatile U032 __iomem *)(par->ctrl_base + 0x00000000); - par->riva.FIFO = - (volatile U032 __iomem *)(par->ctrl_base + 0x00800000); - par->riva.PCIO0 = par->ctrl_base + 0x00601000; - par->riva.PDIO0 = par->ctrl_base + 0x00681000; - par->riva.PVIO = par->ctrl_base + 0x000C0000; - - par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0; - - if (par->FlatPanel == -1) { - switch (par->Chipset & 0xffff) { - case 0x0112: /* known laptop chips */ - case 0x0174: - case 0x0175: - case 0x0176: - case 0x0177: - case 0x0179: - case 0x017C: - case 0x017D: - case 0x0186: - case 0x0187: - case 0x0286: - case 0x028C: - case 0x0316: - case 0x0317: - case 0x031A: - case 0x031B: - case 0x031C: - case 0x031D: - case 0x031E: - case 0x031F: - case 0x0324: - case 0x0325: - case 0x0328: - case 0x0329: - case 0x032C: - case 0x032D: - printk(KERN_INFO PFX - "On a laptop. Assuming Digital Flat Panel\n"); - par->FlatPanel = 1; - break; - default: - break; - } - } - - switch (par->Chipset & 0x0ff0) { - case 0x0110: - if (par->Chipset == NV_CHIP_GEFORCE2_GO) - par->SecondCRTC = TRUE; -#if defined(__powerpc__) - if (par->FlatPanel == 1) - par->SecondCRTC = TRUE; -#endif - riva_override_CRTC(par); - break; - case 0x0170: - case 0x0180: - case 0x01F0: - case 0x0250: - case 0x0280: - case 0x0300: - case 0x0310: - case 0x0320: - case 0x0330: - case 0x0340: - riva_is_second(par); - break; - default: - break; - } - - if (par->SecondCRTC) { - par->riva.PCIO = par->riva.PCIO0 + 0x2000; - par->riva.PCRTC = par->riva.PCRTC0 + 0x800; - par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800; - par->riva.PDIO = par->riva.PDIO0 + 0x2000; - } else { - par->riva.PCIO = par->riva.PCIO0; - par->riva.PCRTC = par->riva.PCRTC0; - par->riva.PRAMDAC = par->riva.PRAMDAC0; - par->riva.PDIO = par->riva.PDIO0; - } - - if (par->FlatPanel == -1) { - /* Fix me, need x86 DDC code */ - par->FlatPanel = 0; - } - par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE; - - RivaGetConfig(&par->riva, par->pdev, par->Chipset); -} - diff --git a/drivers/video/fbdev/riva/nv_type.h b/drivers/video/fbdev/riva/nv_type.h deleted file mode 100644 index 51937a0ae0a4..000000000000 --- a/drivers/video/fbdev/riva/nv_type.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */ - -#ifndef __NV_STRUCT_H__ -#define __NV_STRUCT_H__ - -#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128) -#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT) -#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2) -#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2) -#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2) -#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2) -#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2) -#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256) -#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR) -#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO) -#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX) -#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100) -#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR) -#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO) -#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS) -#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI) -#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA) -#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO) -#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460) -#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440) -#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420) -#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO) -#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO) -#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32) -#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL) -#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64) -#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200) -#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL) -#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL) -#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180) -#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181) -#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182) -#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188) -#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A) -#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B) -#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2) -#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0) -#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3) -#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200) -#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500) -#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC) -#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600) -#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400) -#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200) -#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL) -#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL) -#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL) -#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280) -#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281) -#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288) -#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289) - -#endif /* __NV_STRUCT_H__ */ diff --git a/drivers/video/fbdev/riva/nvreg.h b/drivers/video/fbdev/riva/nvreg.h deleted file mode 100644 index abfc167ae8d8..000000000000 --- a/drivers/video/fbdev/riva/nvreg.h +++ /dev/null @@ -1,188 +0,0 @@ -/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ -/* - * Copyright 1996-1997 David J. McKay - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */ - -#ifndef __NVREG_H_ -#define __NVREG_H_ - -/* Little macro to construct bitmask for contiguous ranges of bits */ -#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) -#define MASKEXPAND(mask) BITMASK(1?mask,0?mask) - -/* Macro to set specific bitfields (mask has to be a macro x:y) ! */ -#define SetBF(mask,value) ((value) << (0?mask)) -#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) - -#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ - | SetBF(mask,value))) - -#define DEVICE_BASE(device) (0?NV##_##device) -#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1) - -/* This is where we will have to have conditional compilation */ -#define DEVICE_ACCESS(device,reg) \ - nvCONTROL[(NV_##device##_##reg)/4] - -#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) -#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) -#define DEVICE_PRINT(device,reg) \ - ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) -#define DEVICE_DEF(device,mask,value) \ - SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) -#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) -#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) - -#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) -#define PDAC_Read(reg) DEVICE_READ(PDAC,reg) -#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) -#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) -#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) -#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) - -#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) -#define PFB_Read(reg) DEVICE_READ(PFB,reg) -#define PFB_Print(reg) DEVICE_PRINT(PFB,reg) -#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) -#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) -#define PFB_Mask(mask) DEVICE_MASK(PFB,mask) - -#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) -#define PRM_Read(reg) DEVICE_READ(PRM,reg) -#define PRM_Print(reg) DEVICE_PRINT(PRM,reg) -#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) -#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) -#define PRM_Mask(mask) DEVICE_MASK(PRM,mask) - -#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) -#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) -#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) -#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) -#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) -#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) - -#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) -#define PDMA_Read(reg) DEVICE_READ(PDMA,reg) -#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) -#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) -#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) -#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) - -#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value) -#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg) -#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg) -#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value) -#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value) -#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask) - -#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) -#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) -#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) -#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) -#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) -#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask) - -#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) -#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) -#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) -#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) -#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) -#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) - -#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) -#define PRAM_Read(reg) DEVICE_READ(PRAM,reg) -#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) -#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) -#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) -#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) - -#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) -#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) -#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) -#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) -#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) -#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) - -#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) -#define PMC_Read(reg) DEVICE_READ(PMC,reg) -#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) -#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) -#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) -#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) - -#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) -#define PMC_Read(reg) DEVICE_READ(PMC,reg) -#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) -#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) -#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) -#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) - - -#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) -#define PBUS_Read(reg) DEVICE_READ(PBUS,reg) -#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) -#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) -#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) -#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) - - -#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) -#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) -#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) -#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) -#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) -#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) - - -#define PDAC_ReadExt(reg) \ - ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ - (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ - (PDAC_Read(INDEX_DATA))) - -#define PDAC_WriteExt(reg,value)\ - ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ - (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ - (PDAC_Write(INDEX_DATA,(value)))) - -#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5) -#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5)) - -#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) -#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) - -#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) -#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) -#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) - -#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) -#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) - -extern volatile unsigned *nvCONTROL; - -typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType; - -NVChipType GetChipType(void); - -#endif - - diff --git a/drivers/video/fbdev/riva/riva_hw.c b/drivers/video/fbdev/riva/riva_hw.c deleted file mode 100644 index 4168ac464565..000000000000 --- a/drivers/video/fbdev/riva/riva_hw.c +++ /dev/null @@ -1,2254 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ - -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> -#include "riva_hw.h" -#include "riva_tbl.h" -#include "nv_type.h" - -/* - * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT - * operate identically (except TNT has more memory and better 3D quality. - */ -static int nv3Busy -( - RIVA_HW_INST *chip -) -{ - return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || - NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); -} -static int nv4Busy -( - RIVA_HW_INST *chip -) -{ - return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || - NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); -} -static int nv10Busy -( - RIVA_HW_INST *chip -) -{ - return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || - NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); -} - -static void vgaLockUnlock -( - RIVA_HW_INST *chip, - int Lock -) -{ - U008 cr11; - VGA_WR08(chip->PCIO, 0x3D4, 0x11); - cr11 = VGA_RD08(chip->PCIO, 0x3D5); - if(Lock) cr11 |= 0x80; - else cr11 &= ~0x80; - VGA_WR08(chip->PCIO, 0x3D5, cr11); -} -static void nv3LockUnlock -( - RIVA_HW_INST *chip, - int Lock -) -{ - VGA_WR08(chip->PVIO, 0x3C4, 0x06); - VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); - vgaLockUnlock(chip, Lock); -} -static void nv4LockUnlock -( - RIVA_HW_INST *chip, - int Lock -) -{ - VGA_WR08(chip->PCIO, 0x3D4, 0x1F); - VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); - vgaLockUnlock(chip, Lock); -} - -static int ShowHideCursor -( - RIVA_HW_INST *chip, - int ShowHide -) -{ - int cursor; - cursor = chip->CurrentState->cursor1; - chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | - (ShowHide & 0x01); - VGA_WR08(chip->PCIO, 0x3D4, 0x31); - VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); - return (cursor & 0x01); -} - -/****************************************************************************\ -* * -* The video arbitration routines calculate some "magic" numbers. Fixes * -* the snow seen when accessing the framebuffer without it. * -* It just works (I hope). * -* * -\****************************************************************************/ - -#define DEFAULT_GR_LWM 100 -#define DEFAULT_VID_LWM 100 -#define DEFAULT_GR_BURST_SIZE 256 -#define DEFAULT_VID_BURST_SIZE 128 -#define VIDEO 0 -#define GRAPHICS 1 -#define MPORT 2 -#define ENGINE 3 -#define GFIFO_SIZE 320 -#define GFIFO_SIZE_128 256 -#define MFIFO_SIZE 120 -#define VFIFO_SIZE 256 - -typedef struct { - int gdrain_rate; - int vdrain_rate; - int mdrain_rate; - int gburst_size; - int vburst_size; - char vid_en; - char gr_en; - int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; - int by_gfacc; - char vid_only_once; - char gr_only_once; - char first_vacc; - char first_gacc; - char first_macc; - int vocc; - int gocc; - int mocc; - char cur; - char engine_en; - char converged; - int priority; -} nv3_arb_info; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int graphics_hi_priority; - int media_hi_priority; - int rtl_values; - int valid; -} nv3_fifo_info; -typedef struct { - char pix_bpp; - char enable_video; - char gr_during_vid; - char enable_mp; - int memory_width; - int video_scale; - int pclk_khz; - int mclk_khz; - int mem_page_miss; - int mem_latency; - char mem_aligned; -} nv3_sim_state; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv4_fifo_info; -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv4_sim_state; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv10_fifo_info; -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - u32 memory_type; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv10_sim_state; -static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int iter = 0; - int tmp; - int vfsize, mfsize, gfsize; - int mburst_size = 32; - int mmisses, gmisses, vmisses; - int misses; - int vlwm, glwm, mlwm; - int last, next, cur; - int max_gfsize ; - long ns; - - vlwm = 0; - glwm = 0; - mlwm = 0; - vfsize = 0; - gfsize = 0; - cur = ainfo->cur; - mmisses = 2; - gmisses = 2; - vmisses = 2; - if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; - else max_gfsize = GFIFO_SIZE; - max_gfsize = GFIFO_SIZE; - while (1) - { - if (ainfo->vid_en) - { - if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; - if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; - ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; - vfsize = ns * ainfo->vdrain_rate / 1000000; - vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; - } - if (state->enable_mp) - { - if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; - } - if (ainfo->gr_en) - { - if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; - if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; - ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; - gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; - } - mfsize = 0; - if (!state->gr_during_vid && ainfo->vid_en) - if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->mocc < 0) - next = MPORT; - else if (ainfo->gocc< ainfo->by_gfacc) - next = GRAPHICS; - else return (0); - else switch (ainfo->priority) - { - case VIDEO: - if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->mocc<0) - next = MPORT; - else return (0); - break; - case GRAPHICS: - if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->mocc<0) - next = MPORT; - else return (0); - break; - default: - if (ainfo->mocc<0) - next = MPORT; - else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else return (0); - break; - } - last = cur; - cur = next; - iter++; - switch (cur) - { - case VIDEO: - if (last==cur) misses = 0; - else if (ainfo->first_vacc) misses = vmisses; - else misses = 1; - ainfo->first_vacc = 0; - if (last!=cur) - { - ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; - vlwm = ns * ainfo->vdrain_rate/ 1000000; - vlwm = ainfo->vocc - vlwm; - } - ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; - ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; - break; - case GRAPHICS: - if (last==cur) misses = 0; - else if (ainfo->first_gacc) misses = gmisses; - else misses = 1; - ainfo->first_gacc = 0; - if (last!=cur) - { - ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; - glwm = ns * ainfo->gdrain_rate/1000000; - glwm = ainfo->gocc - glwm; - } - ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; - break; - default: - if (last==cur) misses = 0; - else if (ainfo->first_macc) misses = mmisses; - else misses = 1; - ainfo->first_macc = 0; - ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; - ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; - break; - } - if (iter>100) - { - ainfo->converged = 0; - return (1); - } - ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; - tmp = ns * ainfo->gdrain_rate/1000000; - if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; - tmp = ns * ainfo->vdrain_rate/1000000; - if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(ainfo->gocc) > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - if (abs(ainfo->vocc) > VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(ainfo->mocc) > MFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(vfsize) > VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (abs(gfsize) > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - if (abs(mfsize) > MFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - } -} -static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - long ens, vns, mns, gns; - int mmisses, gmisses, vmisses, eburst_size, mburst_size; - int refresh_cycle; - - refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; - mmisses = 2; - if (state->mem_aligned) gmisses = 2; - else gmisses = 3; - vmisses = 2; - eburst_size = state->memory_width * 1; - mburst_size = 32; - gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; - ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; - ainfo->wcmocc = 0; - ainfo->wcgocc = 0; - ainfo->wcvocc = 0; - ainfo->wcvlwm = 0; - ainfo->wcglwm = 0; - ainfo->engine_en = 1; - ainfo->converged = 1; - if (ainfo->engine_en) - { - ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; - ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; - ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; - ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; - ainfo->cur = ENGINE; - ainfo->first_vacc = 1; - ainfo->first_gacc = 1; - ainfo->first_macc = 1; - nv3_iterate(res_info, state,ainfo); - } - if (state->enable_mp) - { - mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; - ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; - ainfo->cur = MPORT; - ainfo->first_vacc = 1; - ainfo->first_gacc = 1; - ainfo->first_macc = 0; - nv3_iterate(res_info, state,ainfo); - } - if (ainfo->gr_en) - { - ainfo->first_vacc = 1; - ainfo->first_gacc = 0; - ainfo->first_macc = 1; - gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; - ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; - ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; - ainfo->cur = GRAPHICS; - nv3_iterate(res_info, state,ainfo); - } - if (ainfo->vid_en) - { - ainfo->first_vacc = 0; - ainfo->first_gacc = 1; - ainfo->first_macc = 1; - vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; - ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; - ainfo->cur = VIDEO; - nv3_iterate(res_info, state, ainfo); - } - if (ainfo->converged) - { - res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; - res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; - res_info->graphics_burst_size = ainfo->gburst_size; - res_info->video_burst_size = ainfo->vburst_size; - res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); - res_info->media_hi_priority = (ainfo->priority == MPORT); - if (res_info->video_lwm > 160) - { - res_info->graphics_lwm = 256; - res_info->video_lwm = 128; - res_info->graphics_burst_size = 64; - res_info->video_burst_size = 64; - res_info->graphics_hi_priority = 0; - res_info->media_hi_priority = 0; - ainfo->converged = 0; - return (0); - } - if (res_info->video_lwm > 128) - { - res_info->video_lwm = 128; - } - return (1); - } - else - { - res_info->graphics_lwm = 256; - res_info->video_lwm = 128; - res_info->graphics_burst_size = 64; - res_info->video_burst_size = 64; - res_info->graphics_hi_priority = 0; - res_info->media_hi_priority = 0; - return (0); - } -} -static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int done, g,v, p; - - done = 0; - for (p=0; p < 2; p++) - { - for (g=128 ; g > 32; g= g>> 1) - { - for (v=128; v >=32; v = v>> 1) - { - ainfo->priority = p; - ainfo->gburst_size = g; - ainfo->vburst_size = v; - done = nv3_arb(res_info, state,ainfo); - if (done && (g==128)) - if ((res_info->graphics_lwm + g) > 256) - done = 0; - if (done) - goto Done; - } - } - } - - Done: - return done; -} -static void nv3CalcArbitration -( - nv3_fifo_info * res_info, - nv3_sim_state * state -) -{ - nv3_fifo_info save_info; - nv3_arb_info ainfo; - char res_gr, res_vid; - - ainfo.gr_en = 1; - ainfo.vid_en = state->enable_video; - ainfo.vid_only_once = 0; - ainfo.gr_only_once = 0; - ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); - ainfo.vdrain_rate = (int) state->pclk_khz * 2; - if (state->video_scale != 0) - ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; - ainfo.mdrain_rate = 33000; - res_info->rtl_values = 0; - if (!state->gr_during_vid && state->enable_video) - { - ainfo.gr_only_once = 1; - ainfo.gr_en = 1; - ainfo.gdrain_rate = 0; - res_vid = nv3_get_param(res_info, state, &ainfo); - res_vid = ainfo.converged; - save_info.video_lwm = res_info->video_lwm; - save_info.video_burst_size = res_info->video_burst_size; - ainfo.vid_en = 1; - ainfo.vid_only_once = 1; - ainfo.gr_en = 1; - ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); - ainfo.vdrain_rate = 0; - res_gr = nv3_get_param(res_info, state, &ainfo); - res_gr = ainfo.converged; - res_info->video_lwm = save_info.video_lwm; - res_info->video_burst_size = save_info.video_burst_size; - res_info->valid = res_gr & res_vid; - } - else - { - if (!ainfo.gr_en) ainfo.gdrain_rate = 0; - if (!ainfo.vid_en) ainfo.vdrain_rate = 0; - res_gr = nv3_get_param(res_info, state, &ainfo); - res_info->valid = ainfo.converged; - } -} -static void nv3UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv3_fifo_info fifo_data; - nv3_sim_state sim_data; - unsigned int M, N, P, pll, MClk; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.video_scale = 1; - sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? - 128 : 64; - sim_data.memory_width = 128; - - sim_data.mem_latency = 9; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 11; - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - nv3CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } - else - { - *lwm = 0x24; - *burst = 0x2; - } -} -static void nv4CalcArbitration -( - nv4_fifo_info *fifo, - nv4_sim_state *arb -) -{ - int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; - int found, mclk_extra, mclk_loop, cbs, m1, p1; - int mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; - int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; - int craw, vraw; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - cas = arb->mem_latency; - width = arb->memory_width >> 6; - video_enable = arb->enable_video; - color_key_enable = arb->gr_during_vid; - bpp = arb->pix_bpp; - align = arb->mem_aligned; - mp_enable = arb->enable_mp; - clwm = 0; - vlwm = 0; - cbs = 128; - pclks = 2; - nvclks = 2; - nvclks += 2; - nvclks += 1; - mclks = 5; - mclks += 3; - mclks += 1; - mclks += cas; - mclks += 1; - mclks += 1; - mclks += 1; - mclks += 1; - mclk_extra = 3; - nvclks += 2; - nvclks += 1; - nvclks += 1; - nvclks += 1; - if (mp_enable) - mclks+=4; - nvclks += 0; - pclks += 0; - found = 0; - vbs = 0; - while (found != 1) - { - fifo->valid = 1; - found = 1; - mclk_loop = mclks+mclk_extra; - us_m = mclk_loop *1000*1000 / mclk_freq; - us_n = nvclks*1000*1000 / nvclk_freq; - us_p = nvclks*1000*1000 / pclk_freq; - if (video_enable) - { - video_drain_rate = pclk_freq * 2; - crtc_drain_rate = pclk_freq * bpp/8; - vpagemiss = 2; - vpagemiss += 1; - crtpagemiss = 2; - vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; - else - video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; - us_video = vpm_us + us_m + us_n + us_p + video_fill_us; - vlwm = us_video * video_drain_rate/(1000*1000); - vlwm++; - vbs = 128; - if (vlwm > 128) vbs = 64; - if (vlwm > (256-64)) vbs = 32; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; - else - video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = - us_video - +video_fill_us - +cpm_us - +us_m + us_n +us_p - ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; - } - else - { - crtc_drain_rate = pclk_freq * bpp/8; - crtpagemiss = 2; - crtpagemiss += 1; - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; - } - m1 = clwm + cbs - 512; - p1 = m1 * pclk_freq / mclk_freq; - p1 = p1 * bpp / 8; - if ((p1 < m1) && (m1 > 0)) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - else if (video_enable) - { - if ((clwm > 511) || (vlwm > 255)) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - } - else - { - if (clwm > 519) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - } - craw = clwm; - vraw = vlwm; - if (clwm < 384) clwm = 384; - if (vlwm < 128) vlwm = 128; - data = (int)(clwm); - fifo->graphics_lwm = data; - fifo->graphics_burst_size = 128; - data = (int)((vlwm+15)); - fifo->video_lwm = data; - fifo->video_burst_size = vbs; - } -} -static void nv4UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv4_fifo_info fifo_data; - nv4_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk, cfg1; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? - 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv4CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} -static void nv10CalcArbitration -( - nv10_fifo_info *fifo, - nv10_sim_state *arb -) -{ - int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; - int nvclk_fill, us_extra; - int found, mclk_extra, mclk_loop, cbs, m1; - int mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate; - int vus_m, vus_n, vus_p; - int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm; - int clwm_rnd_down; - int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2; - int pclks_2_top_fifo, min_mclk_extra; - int us_min_mclk_extra; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; /* freq in KHz */ - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - cas = arb->mem_latency; - width = arb->memory_width/64; - video_enable = arb->enable_video; - color_key_enable = arb->gr_during_vid; - bpp = arb->pix_bpp; - align = arb->mem_aligned; - mp_enable = arb->enable_mp; - clwm = 0; - vlwm = 1024; - - cbs = 512; - vbs = 512; - - pclks = 4; /* lwm detect. */ - - nvclks = 3; /* lwm -> sync. */ - nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ - - mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ - - mclks += 1; /* arb_hp_req */ - mclks += 5; /* ap_hp_req tiling pipeline */ - - mclks += 2; /* tc_req latency fifo */ - mclks += 2; /* fb_cas_n_ memory request to fbio block */ - mclks += 7; /* sm_d_rdv data returned from fbio block */ - - /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ - if (arb->memory_type == 0) - if (arb->memory_width == 64) /* 64 bit bus */ - mclks += 4; - else - mclks += 2; - else - if (arb->memory_width == 64) /* 64 bit bus */ - mclks += 2; - else - mclks += 1; - - if ((!video_enable) && (arb->memory_width == 128)) - { - mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ - min_mclk_extra = 17; - } - else - { - mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ - /* mclk_extra = 4; */ /* Margin of error */ - min_mclk_extra = 18; - } - - nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ - nvclks += 1; /* fbi_d_rdv_n */ - nvclks += 1; /* Fbi_d_rdata */ - nvclks += 1; /* crtfifo load */ - - if(mp_enable) - mclks+=4; /* Mp can get in with a burst of 8. */ - /* Extra clocks determined by heuristics */ - - nvclks += 0; - pclks += 0; - found = 0; - while(found != 1) { - fifo->valid = 1; - found = 1; - mclk_loop = mclks+mclk_extra; - us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ - us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ - us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; - us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ - us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ - us_pipe = us_m + us_n + us_p; - us_pipe_min = us_m_min + us_n + us_p; - us_extra = 0; - - vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ - vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */ - vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ - vus_pipe = vus_m + vus_n + vus_p; - - if(video_enable) { - video_drain_rate = pclk_freq * 4; /* MB/s */ - crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ - - vpagemiss = 1; /* self generating page miss */ - vpagemiss += 1; /* One higher priority before */ - - crtpagemiss = 2; /* self generating page miss */ - if(mp_enable) - crtpagemiss += 1; /* if MA0 conflict */ - - vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; - - us_video = vpm_us + vus_m; /* Video has separate read return path */ - - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = - us_video /* Wait for video */ - +cpm_us /* CRT Page miss */ - +us_m + us_n +us_p /* other latency */ - ; - - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; /* fixed point <= float_point - 1. Fixes that */ - } else { - crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ - - crtpagemiss = 1; /* self generating page miss */ - crtpagemiss += 1; /* MA0 page miss */ - if(mp_enable) - crtpagemiss += 1; /* if MA0 conflict */ - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; /* fixed point <= float_point - 1. Fixes that */ - - /* - // - // Another concern, only for high pclks so don't do this - // with video: - // What happens if the latency to fetch the cbs is so large that - // fifo empties. In that case we need to have an alternate clwm value - // based off the total burst fetch - // - us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; - us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; - clwm_mt = us_crt * crtc_drain_rate/(1000*1000); - clwm_mt ++; - if(clwm_mt > clwm) - clwm = clwm_mt; - */ - /* Finally, a heuristic check when width == 64 bits */ - if(width == 1){ - nvclk_fill = nvclk_freq * 8; - if(crtc_drain_rate * 100 >= nvclk_fill * 102) - clwm = 0xfff; /*Large number to fail */ - - else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { - clwm = 1024; - cbs = 512; - us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; - } - } - } - - - /* - Overfill check: - - */ - - clwm_rnd_down = ((int)clwm/8)*8; - if (clwm_rnd_down < clwm) - clwm += 8; - - m1 = clwm + cbs - 1024; /* Amount of overfill */ - m2us = us_pipe_min + us_min_mclk_extra; - pclks_2_top_fifo = (1024-clwm)/(8*width); - - /* pclk cycles to drain */ - p1clk = m2us * pclk_freq/(1000*1000); - p2 = p1clk * bpp / 8; /* bytes drained. */ - - if((p2 < m1) && (m1 > 0)) { - fifo->valid = 0; - found = 0; - if(min_mclk_extra == 0) { - if(cbs <= 32) { - found = 1; /* Can't adjust anymore! */ - } else { - cbs = cbs/2; /* reduce the burst size */ - } - } else { - min_mclk_extra--; - } - } else { - if (clwm > 1023){ /* Have some margin */ - fifo->valid = 0; - found = 0; - if(min_mclk_extra == 0) - found = 1; /* Can't adjust anymore! */ - else - min_mclk_extra--; - } - } - craw = clwm; - - if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; - data = (int)(clwm); - /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ - fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; - - /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ - fifo->video_lwm = 1024; fifo->video_burst_size = 512; - } -} -static void nv10UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv10_fifo_info fifo_data; - nv10_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk, cfg1; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? - 1 : 0; - sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? - 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv10CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -static void nForceUpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip, - struct pci_dev *pdev -) -{ - nv10_fifo_info fifo_data; - nv10_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk; - unsigned int uMClkPostDiv; - struct pci_dev *dev; - int domain = pci_domain_nr(pdev->bus); - - dev = pci_get_domain_bus_and_slot(domain, 0, 3); - pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); - pci_dev_put(dev); - uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; - - if(!uMClkPostDiv) uMClkPostDiv = 4; - MClk = 400000 / uMClkPostDiv; - - pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - - dev = pci_get_domain_bus_and_slot(domain, 0, 1); - pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); - pci_dev_put(dev); - sim_data.memory_type = (sim_data.memory_type >> 12) & 1; - - sim_data.memory_width = 64; - sim_data.mem_latency = 3; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 10; - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv10CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) - (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -/****************************************************************************\ -* * -* RIVA Mode State Routines * -* * -\****************************************************************************/ - -/* - * Calculate the Video Clock parameters for the PLL. - */ -static int CalcVClock -( - int clockIn, - int *clockOut, - int *mOut, - int *nOut, - int *pOut, - RIVA_HW_INST *chip -) -{ - unsigned lowM, highM, highP; - unsigned DeltaNew, DeltaOld; - unsigned VClk, Freq; - unsigned M, N, P; - - DeltaOld = 0xFFFFFFFF; - - VClk = (unsigned)clockIn; - - if (chip->CrystalFreqKHz == 13500) - { - lowM = 7; - highM = 13 - (chip->Architecture == NV_ARCH_03); - } - else - { - lowM = 8; - highM = 14 - (chip->Architecture == NV_ARCH_03); - } - - highP = 4 - (chip->Architecture == NV_ARCH_03); - for (P = 0; P <= highP; P ++) - { - Freq = VClk << P; - if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) - { - for (M = lowM; M <= highM; M++) - { - N = (VClk << P) * M / chip->CrystalFreqKHz; - if(N <= 255) { - Freq = (chip->CrystalFreqKHz * N / M) >> P; - if (Freq > VClk) - DeltaNew = Freq - VClk; - else - DeltaNew = VClk - Freq; - if (DeltaNew < DeltaOld) - { - *mOut = M; - *nOut = N; - *pOut = P; - *clockOut = Freq; - DeltaOld = DeltaNew; - } - } - } - } - } - - /* non-zero: M/N/P/clock values assigned. zero: error (not set) */ - return (DeltaOld != 0xFFFFFFFF); -} -/* - * Calculate extended mode parameters (SVGA) and save in a - * mode state structure. - */ -int CalcStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state, - struct pci_dev *pdev, - int bpp, - int width, - int hDisplaySize, - int height, - int dotClock -) -{ - int pixelDepth; - int VClk, m, n, p; - - /* - * Save mode parameters. - */ - state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ - state->width = width; - state->height = height; - /* - * Extended RIVA registers. - */ - pixelDepth = (bpp + 1)/8; - if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) - return -EINVAL; - - switch (chip->Architecture) - { - case NV_ARCH_03: - nv3UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - state->cursor0 = 0x00; - state->cursor1 = 0x78; - state->cursor2 = 0x00000000; - state->pllsel = 0x10010100; - state->config = ((width + 31)/32) - | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) - | 0x1000; - state->general = 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; - break; - case NV_ARCH_04: - nv4UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - state->cursor0 = 0x00; - state->cursor1 = 0xFC; - state->cursor2 = 0x00000000; - state->pllsel = 0x10000700; - state->config = 0x00001114; - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - if((chip->Chipset == NV_CHIP_IGEFORCE2) || - (chip->Chipset == NV_CHIP_0x01F0)) - { - nForceUpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip, pdev); - } else { - nv10UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - } - state->cursor0 = 0x80 | (chip->CursorStart >> 17); - state->cursor1 = (chip->CursorStart >> 11) << 2; - state->cursor2 = chip->CursorStart >> 24; - state->pllsel = 0x10000700; - state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - } - - /* Paul Richards: below if block borks things in kernel for some reason */ - /* Tony: Below is needed to set hardware in DirectColor */ - if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) - state->general |= 0x00000030; - - state->vpll = (p << 16) | (n << 8) | m; - state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; - state->pixel = pixelDepth > 2 ? 3 : pixelDepth; - state->offset0 = - state->offset1 = - state->offset2 = - state->offset3 = 0; - state->pitch0 = - state->pitch1 = - state->pitch2 = - state->pitch3 = pixelDepth * width; - - return 0; -} -/* - * Load fixed function state and pre-calculated/stored state. - */ -#define LOAD_FIXED_STATE(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1]) -#define LOAD_FIXED_STATE_8BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1]) -#define LOAD_FIXED_STATE_15BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1]) -#define LOAD_FIXED_STATE_16BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1]) -#define LOAD_FIXED_STATE_32BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ - NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1]) - -static void UpdateFifoState -( - RIVA_HW_INST *chip -) -{ - int i; - - switch (chip->Architecture) - { - case NV_ARCH_04: - LOAD_FIXED_STATE(nv4,FIFO); - chip->Tri03 = NULL; - chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - /* - * Initialize state for the RivaTriangle3D05 routines. - */ - LOAD_FIXED_STATE(nv10tri05,PGRAPH); - LOAD_FIXED_STATE(nv10,FIFO); - chip->Tri03 = NULL; - chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - } -} -static void LoadStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state -) -{ - int i; - - /* - * Load HW fixed function state. - */ - LOAD_FIXED_STATE(Riva,PMC); - LOAD_FIXED_STATE(Riva,PTIMER); - switch (chip->Architecture) - { - case NV_ARCH_03: - /* - * Make sure frame buffer config gets set before loading PRAMIN. - */ - NV_WR32(chip->PFB, 0x00000200, state->config); - LOAD_FIXED_STATE(nv3,PFIFO); - LOAD_FIXED_STATE(nv3,PRAMIN); - LOAD_FIXED_STATE(nv3,PGRAPH); - switch (state->bpp) - { - case 15: - case 16: - LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); - chip->Tri03 = NULL; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); - chip->Tri03 = NULL; - break; - } - for (i = 0x00000; i < 0x00800; i++) - NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); - NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); - break; - case NV_ARCH_04: - /* - * Make sure frame buffer config gets set before loading PRAMIN. - */ - NV_WR32(chip->PFB, 0x00000200, state->config); - LOAD_FIXED_STATE(nv4,PFIFO); - LOAD_FIXED_STATE(nv4,PRAMIN); - LOAD_FIXED_STATE(nv4,PGRAPH); - switch (state->bpp) - { - case 15: - LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 16: - LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); - chip->Tri03 = NULL; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); - chip->Tri03 = NULL; - break; - } - NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - if(chip->twoHeads) { - VGA_WR08(chip->PCIO, 0x03D4, 0x44); - VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); - chip->LockUnlock(chip, 0); - } - - LOAD_FIXED_STATE(nv10,PFIFO); - LOAD_FIXED_STATE(nv10,PRAMIN); - LOAD_FIXED_STATE(nv10,PGRAPH); - switch (state->bpp) - { - case 15: - LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 16: - LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); - chip->Tri03 = NULL; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); - chip->Tri03 = NULL; - break; - } - - if(chip->Architecture == NV_ARCH_10) { - NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); - NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); - } else { - NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); - NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); - NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); - NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); - NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); - NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); - NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); - NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); - NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); - NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); - NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); - NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); - } - if(chip->twoHeads) { - NV_WR32(chip->PCRTC0, 0x00000860, state->head); - NV_WR32(chip->PCRTC0, 0x00002860, state->head2); - } - NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); - - NV_WR32(chip->PMC, 0x00008704, 1); - NV_WR32(chip->PMC, 0x00008140, 0); - NV_WR32(chip->PMC, 0x00008920, 0); - NV_WR32(chip->PMC, 0x00008924, 0); - NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); - NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); - NV_WR32(chip->PMC, 0x00001588, 0); - - NV_WR32(chip->PFB, 0x00000240, 0); - NV_WR32(chip->PFB, 0x00000250, 0); - NV_WR32(chip->PFB, 0x00000260, 0); - NV_WR32(chip->PFB, 0x00000270, 0); - NV_WR32(chip->PFB, 0x00000280, 0); - NV_WR32(chip->PFB, 0x00000290, 0); - NV_WR32(chip->PFB, 0x000002A0, 0); - NV_WR32(chip->PFB, 0x000002B0, 0); - - NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); - NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); - NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); - NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); - NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); - NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); - NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); - NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); - NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); - NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); - NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); - NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); - NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); - NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); - NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); - NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); - NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); - NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); - NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); - NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); - NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); - NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); - NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); - NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); - NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); - NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); - NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); - NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); - NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); - NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); - NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); - NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); - NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); - NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); - for (i = 0; i < (3*16); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); - for (i = 0; i < (16*16); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); - NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); - for (i = 0; i < (59*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); - for (i = 0; i < (47*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); - for (i = 0; i < (3*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); - for (i = 0; i < (19*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); - for (i = 0; i < (12*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); - for (i = 0; i < (12*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); - for (i = 0; i < (8*4); i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); - for (i = 0; i < 16; i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); - for (i = 0; i < 4; i++) - NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); - - NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); - - if(chip->flatPanel) { - if((chip->Chipset & 0x0ff0) == 0x0110) { - NV_WR32(chip->PRAMDAC, 0x0528, state->dither); - } else - if((chip->Chipset & 0x0ff0) >= 0x0170) { - NV_WR32(chip->PRAMDAC, 0x083C, state->dither); - } - - VGA_WR08(chip->PCIO, 0x03D4, 0x53); - VGA_WR08(chip->PCIO, 0x03D5, 0); - VGA_WR08(chip->PCIO, 0x03D4, 0x54); - VGA_WR08(chip->PCIO, 0x03D5, 0); - VGA_WR08(chip->PCIO, 0x03D4, 0x21); - VGA_WR08(chip->PCIO, 0x03D5, 0xfa); - } - - VGA_WR08(chip->PCIO, 0x03D4, 0x41); - VGA_WR08(chip->PCIO, 0x03D5, state->extra); - } - LOAD_FIXED_STATE(Riva,FIFO); - UpdateFifoState(chip); - /* - * Load HW mode state. - */ - VGA_WR08(chip->PCIO, 0x03D4, 0x19); - VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); - VGA_WR08(chip->PCIO, 0x03D4, 0x1A); - VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); - VGA_WR08(chip->PCIO, 0x03D4, 0x25); - VGA_WR08(chip->PCIO, 0x03D5, state->screen); - VGA_WR08(chip->PCIO, 0x03D4, 0x28); - VGA_WR08(chip->PCIO, 0x03D5, state->pixel); - VGA_WR08(chip->PCIO, 0x03D4, 0x2D); - VGA_WR08(chip->PCIO, 0x03D5, state->horiz); - VGA_WR08(chip->PCIO, 0x03D4, 0x1B); - VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); - VGA_WR08(chip->PCIO, 0x03D4, 0x20); - VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); - VGA_WR08(chip->PCIO, 0x03D4, 0x30); - VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); - VGA_WR08(chip->PCIO, 0x03D4, 0x31); - VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); - VGA_WR08(chip->PCIO, 0x03D4, 0x2F); - VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); - VGA_WR08(chip->PCIO, 0x03D4, 0x39); - VGA_WR08(chip->PCIO, 0x03D5, state->interlace); - - if(!chip->flatPanel) { - NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); - NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); - if(chip->twoHeads) - NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); - } else { - NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); - } - NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); - - /* - * Turn off VBlank enable and reset. - */ - NV_WR32(chip->PCRTC, 0x00000140, 0); - NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); - /* - * Set interrupt enable. - */ - NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); - /* - * Set current state pointer. - */ - chip->CurrentState = state; - /* - * Reset FIFO free and empty counts. - */ - chip->FifoFreeCount = 0; - /* Free count from first subchannel */ - chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); -} -static void UnloadStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state -) -{ - /* - * Save current HW state. - */ - VGA_WR08(chip->PCIO, 0x03D4, 0x19); - state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x1A); - state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x25); - state->screen = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x28); - state->pixel = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x2D); - state->horiz = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x1B); - state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x20); - state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x30); - state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x31); - state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x2F); - state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x39); - state->interlace = VGA_RD08(chip->PCIO, 0x03D5); - state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); - state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); - state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); - state->general = NV_RD32(chip->PRAMDAC, 0x00000600); - state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); - state->config = NV_RD32(chip->PFB, 0x00000200); - switch (chip->Architecture) - { - case NV_ARCH_03: - state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); - state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); - state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); - state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); - state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); - state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); - state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); - state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); - break; - case NV_ARCH_04: - state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); - state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); - state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); - state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); - state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); - state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); - state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); - state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); - state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); - state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); - state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); - state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); - state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); - state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); - state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); - if(chip->twoHeads) { - state->head = NV_RD32(chip->PCRTC0, 0x00000860); - state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); - VGA_WR08(chip->PCIO, 0x03D4, 0x44); - state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); - } - VGA_WR08(chip->PCIO, 0x03D4, 0x41); - state->extra = VGA_RD08(chip->PCIO, 0x03D5); - state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); - - if((chip->Chipset & 0x0ff0) == 0x0110) { - state->dither = NV_RD32(chip->PRAMDAC, 0x0528); - } else - if((chip->Chipset & 0x0ff0) >= 0x0170) { - state->dither = NV_RD32(chip->PRAMDAC, 0x083C); - } - break; - } -} -static void SetStartAddress -( - RIVA_HW_INST *chip, - unsigned start -) -{ - NV_WR32(chip->PCRTC, 0x800, start); -} - -static void SetStartAddress3 -( - RIVA_HW_INST *chip, - unsigned start -) -{ - int offset = start >> 2; - int pan = (start & 3) << 1; - unsigned char tmp; - - /* - * Unlock extended registers. - */ - chip->LockUnlock(chip, 0); - /* - * Set start address. - */ - VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); - offset >>= 8; - VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); - offset >>= 8; - VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); - VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); - VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); - VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); - /* - * 4 pixel pan register. - */ - offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); - VGA_WR08(chip->PCIO, 0x3C0, 0x13); - VGA_WR08(chip->PCIO, 0x3C0, pan); -} -static void nv3SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,5); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); -} -static void nv4SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} -static void nv10SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} -static void nv3SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,5); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); -} -static void nv4SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface __iomem *Surface = - (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); - - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); - NV_WR32(&Surface->Offset, 0, surf0); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); - NV_WR32(&Surface->Offset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} -static void nv10SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface3D __iomem *Surfaces3D = - (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,4); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); - NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); - NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); - NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); -} - -/****************************************************************************\ -* * -* Probe RIVA Chip Configuration * -* * -\****************************************************************************/ - -static void nv3GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) - { - if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) - && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) - { - /* - * SDRAM 128 ZX. - */ - chip->RamBandwidthKBytesPerSec = 800000; - switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) - { - case 2: - chip->RamAmountKBytes = 1024 * 4; - break; - case 1: - chip->RamAmountKBytes = 1024 * 2; - break; - default: - chip->RamAmountKBytes = 1024 * 8; - break; - } - } - else - { - chip->RamBandwidthKBytesPerSec = 1000000; - chip->RamAmountKBytes = 1024 * 8; - } - } - else - { - /* - * SGRAM 128. - */ - chip->RamBandwidthKBytesPerSec = 1000000; - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 8; - break; - case 2: - chip->RamAmountKBytes = 1024 * 4; - break; - default: - chip->RamAmountKBytes = 1024 * 2; - break; - } - } - chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); - chip->VBlankBit = 0x00000100; - chip->MaxVClockFreqKHz = 256000; - /* - * Set chip functions. - */ - chip->Busy = nv3Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress3; - chip->SetSurfaces2D = nv3SetSurfaces2D; - chip->SetSurfaces3D = nv3SetSurfaces3D; - chip->LockUnlock = nv3LockUnlock; -} -static void nv4GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) - { - chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 - + 1024 * 2; - } - else - { - switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 32; - break; - case 1: - chip->RamAmountKBytes = 1024 * 4; - break; - case 2: - chip->RamAmountKBytes = 1024 * 8; - break; - case 3: - default: - chip->RamAmountKBytes = 1024 * 16; - break; - } - } - switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) - { - case 3: - chip->RamBandwidthKBytesPerSec = 800000; - break; - default: - chip->RamBandwidthKBytesPerSec = 1000000; - break; - } - chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); - chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 350000; - /* - * Set chip functions. - */ - chip->Busy = nv4Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv4SetSurfaces2D; - chip->SetSurfaces3D = nv4SetSurfaces3D; - chip->LockUnlock = nv4LockUnlock; -} -static void nv10GetConfig -( - RIVA_HW_INST *chip, - struct pci_dev *pdev, - unsigned int chipset -) -{ - struct pci_dev* dev; - int domain = pci_domain_nr(pdev->bus); - u32 amt; - -#ifdef __BIG_ENDIAN - /* turn on big endian register access */ - if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) - NV_WR32(chip->PMC, 0x00000004, 0x01000001); -#endif - - /* - * Fill in chip configuration. - */ - if(chipset == NV_CHIP_IGEFORCE2) { - dev = pci_get_domain_bus_and_slot(domain, 0, 1); - pci_read_config_dword(dev, 0x7C, &amt); - pci_dev_put(dev); - chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; - } else if(chipset == NV_CHIP_0x01F0) { - dev = pci_get_domain_bus_and_slot(domain, 0, 1); - pci_read_config_dword(dev, 0x84, &amt); - pci_dev_put(dev); - chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; - } else { - switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) - { - case 0x02: - chip->RamAmountKBytes = 1024 * 2; - break; - case 0x04: - chip->RamAmountKBytes = 1024 * 4; - break; - case 0x08: - chip->RamAmountKBytes = 1024 * 8; - break; - case 0x10: - chip->RamAmountKBytes = 1024 * 16; - break; - case 0x20: - chip->RamAmountKBytes = 1024 * 32; - break; - case 0x40: - chip->RamAmountKBytes = 1024 * 64; - break; - case 0x80: - chip->RamAmountKBytes = 1024 * 128; - break; - default: - chip->RamAmountKBytes = 1024 * 16; - break; - } - } - switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) - { - case 3: - chip->RamBandwidthKBytesPerSec = 800000; - break; - default: - chip->RamBandwidthKBytesPerSec = 1000000; - break; - } - chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? - 14318 : 13500; - - switch (chipset & 0x0ff0) { - case 0x0170: - case 0x0180: - case 0x01F0: - case 0x0250: - case 0x0280: - case 0x0300: - case 0x0310: - case 0x0320: - case 0x0330: - case 0x0340: - if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) - chip->CrystalFreqKHz = 27000; - break; - default: - break; - } - - chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; - chip->CURSOR = NULL; /* can't set this here */ - chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 350000; - /* - * Set chip functions. - */ - chip->Busy = nv10Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv10SetSurfaces2D; - chip->SetSurfaces3D = nv10SetSurfaces3D; - chip->LockUnlock = nv4LockUnlock; - - switch(chipset & 0x0ff0) { - case 0x0110: - case 0x0170: - case 0x0180: - case 0x01F0: - case 0x0250: - case 0x0280: - case 0x0300: - case 0x0310: - case 0x0320: - case 0x0330: - case 0x0340: - chip->twoHeads = TRUE; - break; - default: - chip->twoHeads = FALSE; - break; - } -} -int RivaGetConfig -( - RIVA_HW_INST *chip, - struct pci_dev *pdev, - unsigned int chipset -) -{ - /* - * Save this so future SW know whats it's dealing with. - */ - chip->Version = RIVA_SW_VERSION; - /* - * Chip specific configuration. - */ - switch (chip->Architecture) - { - case NV_ARCH_03: - nv3GetConfig(chip); - break; - case NV_ARCH_04: - nv4GetConfig(chip); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - nv10GetConfig(chip, pdev, chipset); - break; - default: - return (-1); - } - chip->Chipset = chipset; - /* - * Fill in FIFO pointers. - */ - chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); - chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); - chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); - chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); - chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); - chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); - chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); - chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); - return (0); -} - diff --git a/drivers/video/fbdev/riva/riva_hw.h b/drivers/video/fbdev/riva/riva_hw.h deleted file mode 100644 index 5e7b35466b00..000000000000 --- a/drivers/video/fbdev/riva/riva_hw.h +++ /dev/null @@ -1,564 +0,0 @@ -/***************************************************************************\ -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| -\***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */ -#ifndef __RIVA_HW_H__ -#define __RIVA_HW_H__ -#define RIVA_SW_VERSION 0x00010003 - -#ifndef Bool -typedef int Bool; -#endif - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -#ifndef NULL -#define NULL 0 -#endif - -/* - * Typedefs to force certain sized values. - */ -typedef unsigned char U008; -typedef unsigned short U016; -typedef unsigned int U032; - -/* - * HW access macros. - */ -#include <asm/io.h> - -#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i))) -#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i))) -#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i))) -#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i))) -#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i))) -#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) - -#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i))) -#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i))) - -/* - * Define different architectures. - */ -#define NV_ARCH_03 0x03 -#define NV_ARCH_04 0x04 -#define NV_ARCH_10 0x10 -#define NV_ARCH_20 0x20 -#define NV_ARCH_30 0x30 -#define NV_ARCH_40 0x40 - -/***************************************************************************\ -* * -* FIFO registers. * -* * -\***************************************************************************/ - -/* - * Raster OPeration. Windows style ROP3. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 Rop3; -} RivaRop; -/* - * 8X8 Monochrome pattern. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BD]; - U032 Shape; - U032 reserved03[0x001]; - U032 Color0; - U032 Color1; - U032 Monochrome[2]; -} RivaPattern; -/* - * Scissor clip rectangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 TopLeft; - U032 WidthHeight; -} RivaClip; -/* - * 2D filled rectangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop[1]; -#endif - U032 reserved01[0x0BC]; - U032 Color; - U032 reserved03[0x03E]; - U032 TopLeft; - U032 WidthHeight; -} RivaRectangle; -/* - * 2D screen-screen BLT. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 TopLeftSrc; - U032 TopLeftDst; - U032 WidthHeight; -} RivaScreenBlt; -/* - * 2D pixel BLT. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop[1]; -#endif - U032 reserved01[0x0BC]; - U032 TopLeft; - U032 WidthHeight; - U032 WidthHeightIn; - U032 reserved02[0x03C]; - U032 Pixels; -} RivaPixmap; -/* - * Filled rectangle combined with monochrome expand. Useful for glyphs. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 reserved03[(0x040)-1]; - U032 Color1A; - struct - { - U032 TopLeft; - U032 WidthHeight; - } UnclippedRectangle[64]; - U032 reserved04[(0x080)-3]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipB; - U032 Color1B; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClippedRectangle[64]; - U032 reserved05[(0x080)-5]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipC; - U032 Color1C; - U032 WidthHeightC; - U032 PointC; - U032 MonochromeData1C; - U032 reserved06[(0x080)+121]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipD; - U032 Color1D; - U032 WidthHeightInD; - U032 WidthHeightOutD; - U032 PointD; - U032 MonochromeData1D; - U032 reserved07[(0x080)+120]; - struct - { - U032 TopLeft; - U032 BottomRight; - } ClipE; - U032 Color0E; - U032 Color1E; - U032 WidthHeightInE; - U032 WidthHeightOutE; - U032 PointE; - U032 MonochromeData01E; -} RivaBitmap; -/* - * 3D textured, Z buffered triangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BC]; - U032 TextureOffset; - U032 TextureFormat; - U032 TextureFilter; - U032 FogColor; -/* This is a problem on LynxOS */ -#ifdef Control -#undef Control -#endif - U032 Control; - U032 AlphaTest; - U032 reserved02[0x339]; - U032 FogAndIndex; - U032 Color; - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - float TextureS; - float TextureT; -} RivaTexturedTriangle03; -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 ColorKey; - U032 TextureOffset; - U032 TextureFormat; - U032 TextureFilter; - U032 Blend; -/* This is a problem on LynxOS */ -#ifdef Control -#undef Control -#endif - U032 Control; - U032 FogColor; - U032 reserved02[0x39]; - struct - { - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - U032 Color; - U032 Specular; - float TextureS; - float TextureT; - } Vertex[16]; - U032 DrawTriangle3D; -} RivaTexturedTriangle05; -/* - * 2D line. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop[1]; -#endif - U032 reserved01[0x0BC]; - U032 Color; /* source color 0304-0307*/ - U032 Reserved02[0x03e]; - struct { /* start aliased methods in array 0400- */ - U032 point0; /* y_x S16_S16 in pixels 0- 3*/ - U032 point1; /* y_x S16_S16 in pixels 4- 7*/ - } Lin[16]; /* end of aliased methods in array -047f*/ - struct { /* start aliased methods in array 0480- */ - U032 point0X; /* in pixels, 0 at left 0- 3*/ - U032 point0Y; /* in pixels, 0 at top 4- 7*/ - U032 point1X; /* in pixels, 0 at left 8- b*/ - U032 point1Y; /* in pixels, 0 at top c- f*/ - } Lin32[8]; /* end of aliased methods in array -04ff*/ - U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/ - struct { /* start aliased methods in array 0580- */ - U032 x; /* in pixels, 0 at left 0- 3*/ - U032 y; /* in pixels, 0 at top 4- 7*/ - } PolyLin32[16]; /* end of aliased methods in array -05ff*/ - struct { /* start aliased methods in array 0600- */ - U032 color; /* source color 0- 3*/ - U032 point; /* y_x S16_S16 in pixels 4- 7*/ - } ColorPolyLin[16]; /* end of aliased methods in array -067f*/ -} RivaLine; -/* - * 2D/3D surfaces - */ -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BE]; - U032 Offset; -} RivaSurface; -typedef volatile struct -{ - U032 reserved00[4]; -#ifdef __BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BD]; - U032 Pitch; - U032 RenderBufferOffset; - U032 ZBufferOffset; -} RivaSurface3D; - -/***************************************************************************\ -* * -* Virtualized RIVA H/W interface. * -* * -\***************************************************************************/ - -#define FP_ENABLE 1 -#define FP_DITHER 2 - -struct _riva_hw_inst; -struct _riva_hw_state; -/* - * Virtialized chip interface. Makes RIVA 128 and TNT look alike. - */ -typedef struct _riva_hw_inst -{ - /* - * Chip specific settings. - */ - U032 Architecture; - U032 Version; - U032 Chipset; - U032 CrystalFreqKHz; - U032 RamAmountKBytes; - U032 MaxVClockFreqKHz; - U032 RamBandwidthKBytesPerSec; - U032 EnableIRQ; - U032 IO; - U032 VBlankBit; - U032 FifoFreeCount; - U032 FifoEmptyCount; - U032 CursorStart; - U032 flatPanel; - Bool twoHeads; - /* - * Non-FIFO registers. - */ - volatile U032 __iomem *PCRTC0; - volatile U032 __iomem *PCRTC; - volatile U032 __iomem *PRAMDAC0; - volatile U032 __iomem *PFB; - volatile U032 __iomem *PFIFO; - volatile U032 __iomem *PGRAPH; - volatile U032 __iomem *PEXTDEV; - volatile U032 __iomem *PTIMER; - volatile U032 __iomem *PMC; - volatile U032 __iomem *PRAMIN; - volatile U032 __iomem *FIFO; - volatile U032 __iomem *CURSOR; - volatile U008 __iomem *PCIO0; - volatile U008 __iomem *PCIO; - volatile U008 __iomem *PVIO; - volatile U008 __iomem *PDIO0; - volatile U008 __iomem *PDIO; - volatile U032 __iomem *PRAMDAC; - /* - * Common chip functions. - */ - int (*Busy)(struct _riva_hw_inst *); - void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*SetStartAddress)(struct _riva_hw_inst *,U032); - void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032); - void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032); - int (*ShowHideCursor)(struct _riva_hw_inst *,int); - void (*LockUnlock)(struct _riva_hw_inst *, int); - /* - * Current extended mode settings. - */ - struct _riva_hw_state *CurrentState; - /* - * FIFO registers. - */ - RivaRop __iomem *Rop; - RivaPattern __iomem *Patt; - RivaClip __iomem *Clip; - RivaPixmap __iomem *Pixmap; - RivaScreenBlt __iomem *Blt; - RivaBitmap __iomem *Bitmap; - RivaLine __iomem *Line; - RivaTexturedTriangle03 __iomem *Tri03; - RivaTexturedTriangle05 __iomem *Tri05; -} RIVA_HW_INST; -/* - * Extended mode state information. - */ -typedef struct _riva_hw_state -{ - U032 bpp; - U032 width; - U032 height; - U032 interlace; - U032 repaint0; - U032 repaint1; - U032 screen; - U032 scale; - U032 dither; - U032 extra; - U032 pixel; - U032 horiz; - U032 arbitration0; - U032 arbitration1; - U032 vpll; - U032 vpll2; - U032 pllsel; - U032 general; - U032 crtcOwner; - U032 head; - U032 head2; - U032 config; - U032 cursorConfig; - U032 cursor0; - U032 cursor1; - U032 cursor2; - U032 offset0; - U032 offset1; - U032 offset2; - U032 offset3; - U032 pitch0; - U032 pitch1; - U032 pitch2; - U032 pitch3; -} RIVA_HW_STATE; - -/* - * function prototypes - */ - -extern int CalcStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state, - struct pci_dev *pdev, - int bpp, - int width, - int hDisplaySize, - int height, - int dotClock -); - -/* - * External routines. - */ -int RivaGetConfig(RIVA_HW_INST *chip, struct pci_dev *pdev, unsigned int c); -/* - * FIFO Free Count. Should attempt to yield processor if RIVA is busy. - */ - -#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ -{ \ - while ((hwinst).FifoFreeCount < (cnt)) { \ - mb();mb(); \ - (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \ - } \ - (hwinst).FifoFreeCount -= (cnt); \ -} -#endif /* __RIVA_HW_H__ */ - diff --git a/drivers/video/fbdev/riva/riva_tbl.h b/drivers/video/fbdev/riva/riva_tbl.h deleted file mode 100644 index 7ee7d72932d4..000000000000 --- a/drivers/video/fbdev/riva/riva_tbl.h +++ /dev/null @@ -1,1008 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */ - - -/* - * RIVA Fixed Functionality Init Tables. - */ -static unsigned RivaTablePMC[][2] = -{ - {0x00000050, 0x00000000}, - {0x00000080, 0xFFFF00FF}, - {0x00000080, 0xFFFFFFFF} -}; -static unsigned RivaTablePTIMER[][2] = -{ - {0x00000080, 0x00000008}, - {0x00000084, 0x00000003}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF} -}; -static unsigned RivaTableFIFO[][2] = -{ - {0x00000000, 0x80000000}, - {0x00000800, 0x80000001}, - {0x00001000, 0x80000002}, - {0x00001800, 0x80000010}, - {0x00002000, 0x80000011}, - {0x00002800, 0x80000012}, - {0x00003000, 0x80000016}, - {0x00003800, 0x80000013} -}; -static unsigned nv3TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000490, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x00000084, 0x00000000}, - {0x00000086, 0x00002000}, - {0x00000085, 0x00002200}, - {0x00000484, 0x00000000}, - {0x0000049C, 0x00000000}, - {0x00000104, 0x00000000}, - {0x00000108, 0x00000000}, - {0x00000100, 0x00000000}, - {0x000004A0, 0x00000000}, - {0x000004A4, 0x00000000}, - {0x000004A8, 0x00000000}, - {0x000004AC, 0x00000000}, - {0x000004B0, 0x00000000}, - {0x000004B4, 0x00000000}, - {0x000004B8, 0x00000000}, - {0x000004BC, 0x00000000}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000480, 0x00000001}, - {0x00000490, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv3TablePGRAPH[][2] = -{ - {0x00000020, 0x1230001F}, - {0x00000021, 0x10113000}, - {0x00000022, 0x1131F101}, - {0x00000023, 0x0100F531}, - {0x00000060, 0x00000000}, - {0x00000065, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000069, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x000001A8, 0x00000000}, - {0x00000440, 0xFFFFFFFF}, - {0x00000480, 0x00000001}, - {0x000001A0, 0x00000000}, - {0x000001A2, 0x00000000}, - {0x0000018A, 0xFFFFFFFF}, - {0x00000190, 0x00000000}, - {0x00000142, 0x00000000}, - {0x00000154, 0x00000000}, - {0x00000155, 0xFFFFFFFF}, - {0x00000156, 0x00000000}, - {0x00000157, 0xFFFFFFFF}, - {0x00000064, 0x10010002}, - {0x00000050, 0x00000000}, - {0x00000051, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000041, 0xFFFFFFFF}, - {0x00000440, 0xFFFFFFFF}, - {0x000001A9, 0x00000001} -}; -static unsigned nv3TablePGRAPH_8BPP[][2] = -{ - {0x000001AA, 0x00001111} -}; -static unsigned nv3TablePGRAPH_15BPP[][2] = -{ - {0x000001AA, 0x00002222} -}; -static unsigned nv3TablePGRAPH_32BPP[][2] = -{ - {0x000001AA, 0x00003333} -}; -static unsigned nv3TablePRAMIN[][2] = -{ - {0x00000500, 0x00010000}, - {0x00000501, 0x007FFFFF}, - {0x00000200, 0x80000000}, - {0x00000201, 0x00C20341}, - {0x00000204, 0x80000001}, - {0x00000205, 0x00C50342}, - {0x00000208, 0x80000002}, - {0x00000209, 0x00C60343}, - {0x0000020C, 0x80000003}, - {0x0000020D, 0x00DC0348}, - {0x00000210, 0x80000004}, - {0x00000211, 0x00DC0349}, - {0x00000214, 0x80000005}, - {0x00000215, 0x00DC034A}, - {0x00000218, 0x80000006}, - {0x00000219, 0x00DC034B}, - {0x00000240, 0x80000010}, - {0x00000241, 0x00D10344}, - {0x00000244, 0x80000011}, - {0x00000245, 0x00D00345}, - {0x00000248, 0x80000012}, - {0x00000249, 0x00CC0346}, - {0x0000024C, 0x80000013}, - {0x0000024D, 0x00D70347}, - {0x00000258, 0x80000016}, - {0x00000259, 0x00CA034C}, - {0x00000D05, 0x00000000}, - {0x00000D06, 0x00000000}, - {0x00000D07, 0x00000000}, - {0x00000D09, 0x00000000}, - {0x00000D0A, 0x00000000}, - {0x00000D0B, 0x00000000}, - {0x00000D0D, 0x00000000}, - {0x00000D0E, 0x00000000}, - {0x00000D0F, 0x00000000}, - {0x00000D11, 0x00000000}, - {0x00000D12, 0x00000000}, - {0x00000D13, 0x00000000}, - {0x00000D15, 0x00000000}, - {0x00000D16, 0x00000000}, - {0x00000D17, 0x00000000}, - {0x00000D19, 0x00000000}, - {0x00000D1A, 0x00000000}, - {0x00000D1B, 0x00000000}, - {0x00000D1D, 0x00000140}, - {0x00000D1E, 0x00000000}, - {0x00000D1F, 0x00000000}, - {0x00000D20, 0x10100200}, - {0x00000D21, 0x00000000}, - {0x00000D22, 0x00000000}, - {0x00000D23, 0x00000000}, - {0x00000D24, 0x10210200}, - {0x00000D25, 0x00000000}, - {0x00000D26, 0x00000000}, - {0x00000D27, 0x00000000}, - {0x00000D28, 0x10420200}, - {0x00000D29, 0x00000000}, - {0x00000D2A, 0x00000000}, - {0x00000D2B, 0x00000000}, - {0x00000D2C, 0x10830200}, - {0x00000D2D, 0x00000000}, - {0x00000D2E, 0x00000000}, - {0x00000D2F, 0x00000000}, - {0x00000D31, 0x00000000}, - {0x00000D32, 0x00000000}, - {0x00000D33, 0x00000000} -}; -static unsigned nv3TablePRAMIN_8BPP[][2] = -{ - /* 0xXXXXX3XX For MSB mono format */ - /* 0xXXXXX2XX For LSB mono format */ - {0x00000D04, 0x10110203}, - {0x00000D08, 0x10110203}, - {0x00000D0C, 0x1011020B}, - {0x00000D10, 0x10118203}, - {0x00000D14, 0x10110203}, - {0x00000D18, 0x10110203}, - {0x00000D1C, 0x10419208}, - {0x00000D30, 0x10118203} -}; -static unsigned nv3TablePRAMIN_15BPP[][2] = -{ - /* 0xXXXXX2XX For MSB mono format */ - /* 0xXXXXX3XX For LSB mono format */ - {0x00000D04, 0x10110200}, - {0x00000D08, 0x10110200}, - {0x00000D0C, 0x10110208}, - {0x00000D10, 0x10118200}, - {0x00000D14, 0x10110200}, - {0x00000D18, 0x10110200}, - {0x00000D1C, 0x10419208}, - {0x00000D30, 0x10118200} -}; -static unsigned nv3TablePRAMIN_32BPP[][2] = -{ - /* 0xXXXXX3XX For MSB mono format */ - /* 0xXXXXX2XX For LSB mono format */ - {0x00000D04, 0x10110201}, - {0x00000D08, 0x10110201}, - {0x00000D0C, 0x10110209}, - {0x00000D10, 0x10118201}, - {0x00000D14, 0x10110201}, - {0x00000D18, 0x10110201}, - {0x00000D1C, 0x10419208}, - {0x00000D30, 0x10118201} -}; -static unsigned nv4TableFIFO[][2] = -{ - {0x00003800, 0x80000014} -}; -static unsigned nv4TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x0000048B, 0x00000000}, - {0x00000400, 0x00000000}, - {0x00000414, 0x00000000}, - {0x00000084, 0x03000100}, - {0x00000085, 0x00000110}, - {0x00000086, 0x00000112}, - {0x00000143, 0x0000FFFF}, - {0x00000496, 0x0000FFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000415, 0x00000001}, - {0x00000480, 0x00000001}, - {0x00000494, 0x00000001}, - {0x00000495, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv4TablePGRAPH[][2] = -{ - {0x00000020, 0x1231C001}, - {0x00000021, 0x72111101}, - {0x00000022, 0x11D5F071}, - {0x00000023, 0x10D4FF31}, - {0x00000060, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000070, 0x00000000}, - {0x00000078, 0x00000000}, - {0x00000061, 0x00000000}, - {0x00000069, 0x00000000}, - {0x00000071, 0x00000000}, - {0x00000079, 0x00000000}, - {0x00000062, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x00000072, 0x00000000}, - {0x0000007A, 0x00000000}, - {0x00000063, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x00000073, 0x00000000}, - {0x0000007B, 0x00000000}, - {0x00000064, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x00000074, 0x00000000}, - {0x0000007C, 0x00000000}, - {0x00000065, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x00000075, 0x00000000}, - {0x0000007D, 0x00000000}, - {0x00000066, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x00000076, 0x00000000}, - {0x0000007E, 0x00000000}, - {0x00000067, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x00000077, 0x00000000}, - {0x0000007F, 0x00000000}, - {0x00000058, 0x00000000}, - {0x00000059, 0x00000000}, - {0x0000005A, 0x00000000}, - {0x0000005B, 0x00000000}, - {0x00000196, 0x00000000}, - {0x000001A1, 0x01FFFFFF}, - {0x00000197, 0x00000000}, - {0x000001A2, 0x01FFFFFF}, - {0x00000198, 0x00000000}, - {0x000001A3, 0x01FFFFFF}, - {0x00000199, 0x00000000}, - {0x000001A4, 0x01FFFFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x0000005C, 0x10010100}, - {0x000001C4, 0xFFFFFFFF}, - {0x000001C8, 0x00000001}, - {0x00000204, 0x00000000}, - {0x000001C3, 0x00000001} -}; -static unsigned nv4TablePGRAPH_8BPP[][2] = -{ - {0x000001C9, 0x00111111}, - {0x00000186, 0x00001010}, - {0x0000020C, 0x03020202} -}; -static unsigned nv4TablePGRAPH_15BPP[][2] = -{ - {0x000001C9, 0x00226222}, - {0x00000186, 0x00002071}, - {0x0000020C, 0x09080808} -}; -static unsigned nv4TablePGRAPH_16BPP[][2] = -{ - {0x000001C9, 0x00556555}, - {0x00000186, 0x000050C2}, - {0x0000020C, 0x0C0B0B0B} -}; -static unsigned nv4TablePGRAPH_32BPP[][2] = -{ - {0x000001C9, 0x0077D777}, - {0x00000186, 0x000070E5}, - {0x0000020C, 0x0E0D0D0D} -}; -static unsigned nv4TablePRAMIN[][2] = -{ - {0x00000000, 0x80000010}, - {0x00000001, 0x80011145}, - {0x00000002, 0x80000011}, - {0x00000003, 0x80011146}, - {0x00000004, 0x80000012}, - {0x00000005, 0x80011147}, - {0x00000006, 0x80000013}, - {0x00000007, 0x80011148}, - {0x00000008, 0x80000014}, - {0x00000009, 0x80011149}, - {0x0000000A, 0x80000015}, - {0x0000000B, 0x8001114A}, - {0x0000000C, 0x80000016}, - {0x0000000D, 0x8001114F}, - {0x00000020, 0x80000000}, - {0x00000021, 0x80011142}, - {0x00000022, 0x80000001}, - {0x00000023, 0x80011143}, - {0x00000024, 0x80000002}, - {0x00000025, 0x80011144}, - {0x00000026, 0x80000003}, - {0x00000027, 0x8001114B}, - {0x00000028, 0x80000004}, - {0x00000029, 0x8001114C}, - {0x0000002A, 0x80000005}, - {0x0000002B, 0x8001114D}, - {0x0000002C, 0x80000006}, - {0x0000002D, 0x8001114E}, - {0x00000500, 0x00003000}, - {0x00000501, 0x01FFFFFF}, - {0x00000502, 0x00000002}, - {0x00000503, 0x00000002}, - {0x00000508, 0x01008043}, - {0x0000050A, 0x00000000}, - {0x0000050B, 0x00000000}, - {0x0000050C, 0x01008019}, - {0x0000050E, 0x00000000}, - {0x0000050F, 0x00000000}, -#if 1 - {0x00000510, 0x01008018}, -#else - {0x00000510, 0x01008044}, -#endif - {0x00000512, 0x00000000}, - {0x00000513, 0x00000000}, - {0x00000514, 0x01008021}, - {0x00000516, 0x00000000}, - {0x00000517, 0x00000000}, - {0x00000518, 0x0100805F}, - {0x0000051A, 0x00000000}, - {0x0000051B, 0x00000000}, -#if 1 - {0x0000051C, 0x0100804B}, -#else - {0x0000051C, 0x0100804A}, -#endif - {0x0000051E, 0x00000000}, - {0x0000051F, 0x00000000}, - {0x00000520, 0x0100A048}, - {0x00000521, 0x00000D01}, - {0x00000522, 0x11401140}, - {0x00000523, 0x00000000}, - {0x00000524, 0x0300A054}, - {0x00000525, 0x00000D01}, - {0x00000526, 0x11401140}, - {0x00000527, 0x00000000}, - {0x00000528, 0x0300A055}, - {0x00000529, 0x00000D01}, - {0x0000052A, 0x11401140}, - {0x0000052B, 0x00000000}, - {0x0000052C, 0x00000058}, - {0x0000052E, 0x11401140}, - {0x0000052F, 0x00000000}, - {0x00000530, 0x00000059}, - {0x00000532, 0x11401140}, - {0x00000533, 0x00000000}, - {0x00000534, 0x0000005A}, - {0x00000536, 0x11401140}, - {0x00000537, 0x00000000}, - {0x00000538, 0x0000005B}, - {0x0000053A, 0x11401140}, - {0x0000053B, 0x00000000}, - {0x0000053C, 0x0300A01C}, - {0x0000053E, 0x11401140}, - {0x0000053F, 0x00000000} -}; -static unsigned nv4TablePRAMIN_8BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000302}, - {0x0000050D, 0x00000302}, - {0x00000511, 0x00000202}, - {0x00000515, 0x00000302}, - {0x00000519, 0x00000302}, - {0x0000051D, 0x00000302}, - {0x0000052D, 0x00000302}, - {0x0000052E, 0x00000302}, - {0x00000535, 0x00000000}, - {0x00000539, 0x00000000}, - {0x0000053D, 0x00000302} -}; -static unsigned nv4TablePRAMIN_15BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000902}, - {0x0000050D, 0x00000902}, - {0x00000511, 0x00000802}, - {0x00000515, 0x00000902}, - {0x00000519, 0x00000902}, - {0x0000051D, 0x00000902}, - {0x0000052D, 0x00000902}, - {0x0000052E, 0x00000902}, - {0x00000535, 0x00000702}, - {0x00000539, 0x00000702}, - {0x0000053D, 0x00000902} -}; -static unsigned nv4TablePRAMIN_16BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000C02}, - {0x0000050D, 0x00000C02}, - {0x00000511, 0x00000B02}, - {0x00000515, 0x00000C02}, - {0x00000519, 0x00000C02}, - {0x0000051D, 0x00000C02}, - {0x0000052D, 0x00000C02}, - {0x0000052E, 0x00000C02}, - {0x00000535, 0x00000702}, - {0x00000539, 0x00000702}, - {0x0000053D, 0x00000C02} -}; -static unsigned nv4TablePRAMIN_32BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000E02}, - {0x0000050D, 0x00000E02}, - {0x00000511, 0x00000D02}, - {0x00000515, 0x00000E02}, - {0x00000519, 0x00000E02}, - {0x0000051D, 0x00000E02}, - {0x0000052D, 0x00000E02}, - {0x0000052E, 0x00000E02}, - {0x00000535, 0x00000E02}, - {0x00000539, 0x00000E02}, - {0x0000053D, 0x00000E02} -}; -static unsigned nv10TableFIFO[][2] = -{ - {0x00003800, 0x80000014} -}; -static unsigned nv10TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x0000048B, 0x00000000}, - {0x00000400, 0x00000000}, - {0x00000414, 0x00000000}, - {0x00000084, 0x03000100}, - {0x00000085, 0x00000110}, - {0x00000086, 0x00000112}, - {0x00000143, 0x0000FFFF}, - {0x00000496, 0x0000FFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000415, 0x00000001}, - {0x00000480, 0x00000001}, - {0x00000494, 0x00000001}, - {0x00000495, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv10TablePGRAPH[][2] = -{ - {0x00000020, 0x0003FFFF}, - {0x00000021, 0x00118701}, - {0x00000022, 0x24F82AD9}, - {0x00000023, 0x55DE0030}, - {0x00000020, 0x00000000}, - {0x00000024, 0x00000000}, - {0x00000058, 0x00000000}, - {0x00000060, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000070, 0x00000000}, - {0x00000078, 0x00000000}, - {0x00000059, 0x00000000}, - {0x00000061, 0x00000000}, - {0x00000069, 0x00000000}, - {0x00000071, 0x00000000}, - {0x00000079, 0x00000000}, - {0x0000005A, 0x00000000}, - {0x00000062, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x00000072, 0x00000000}, - {0x0000007A, 0x00000000}, - {0x0000005B, 0x00000000}, - {0x00000063, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x00000073, 0x00000000}, - {0x0000007B, 0x00000000}, - {0x0000005C, 0x00000000}, - {0x00000064, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x00000074, 0x00000000}, - {0x0000007C, 0x00000000}, - {0x0000005D, 0x00000000}, - {0x00000065, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x00000075, 0x00000000}, - {0x0000007D, 0x00000000}, - {0x0000005E, 0x00000000}, - {0x00000066, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x00000076, 0x00000000}, - {0x0000007E, 0x00000000}, - {0x0000005F, 0x00000000}, - {0x00000067, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x00000077, 0x00000000}, - {0x0000007F, 0x00000000}, - {0x00000053, 0x00000000}, - {0x00000054, 0x00000000}, - {0x00000055, 0x00000000}, - {0x00000056, 0x00000000}, - {0x00000057, 0x00000000}, - {0x00000196, 0x00000000}, - {0x000001A1, 0x01FFFFFF}, - {0x00000197, 0x00000000}, - {0x000001A2, 0x01FFFFFF}, - {0x00000198, 0x00000000}, - {0x000001A3, 0x01FFFFFF}, - {0x00000199, 0x00000000}, - {0x000001A4, 0x01FFFFFF}, - {0x0000019A, 0x00000000}, - {0x000001A5, 0x01FFFFFF}, - {0x0000019B, 0x00000000}, - {0x000001A6, 0x01FFFFFF}, - {0x00000050, 0x01111111}, - {0x00000040, 0xFFFFFFFF}, - {0x00000051, 0x10010100}, - {0x000001C5, 0xFFFFFFFF}, - {0x000001C8, 0x00000001}, - {0x00000204, 0x00000000}, - {0x000001C4, 0x00000001} -}; -static unsigned nv10TablePGRAPH_8BPP[][2] = -{ - {0x000001C9, 0x00111111}, - {0x00000186, 0x00001010}, - {0x0000020C, 0x03020202} -}; -static unsigned nv10TablePGRAPH_15BPP[][2] = -{ - {0x000001C9, 0x00226222}, - {0x00000186, 0x00002071}, - {0x0000020C, 0x09080808} -}; -static unsigned nv10TablePGRAPH_16BPP[][2] = -{ - {0x000001C9, 0x00556555}, - {0x00000186, 0x000050C2}, - {0x0000020C, 0x000B0B0C} -}; -static unsigned nv10TablePGRAPH_32BPP[][2] = -{ - {0x000001C9, 0x0077D777}, - {0x00000186, 0x000070E5}, - {0x0000020C, 0x0E0D0D0D} -}; -static unsigned nv10tri05TablePGRAPH[][2] = -{ - {(0x00000E00/4), 0x00000000}, - {(0x00000E04/4), 0x00000000}, - {(0x00000E08/4), 0x00000000}, - {(0x00000E0C/4), 0x00000000}, - {(0x00000E10/4), 0x00001000}, - {(0x00000E14/4), 0x00001000}, - {(0x00000E18/4), 0x4003ff80}, - {(0x00000E1C/4), 0x00000000}, - {(0x00000E20/4), 0x00000000}, - {(0x00000E24/4), 0x00000000}, - {(0x00000E28/4), 0x00000000}, - {(0x00000E2C/4), 0x00000000}, - {(0x00000E30/4), 0x00080008}, - {(0x00000E34/4), 0x00080008}, - {(0x00000E38/4), 0x00000000}, - {(0x00000E3C/4), 0x00000000}, - {(0x00000E40/4), 0x00000000}, - {(0x00000E44/4), 0x00000000}, - {(0x00000E48/4), 0x00000000}, - {(0x00000E4C/4), 0x00000000}, - {(0x00000E50/4), 0x00000000}, - {(0x00000E54/4), 0x00000000}, - {(0x00000E58/4), 0x00000000}, - {(0x00000E5C/4), 0x00000000}, - {(0x00000E60/4), 0x00000000}, - {(0x00000E64/4), 0x10000000}, - {(0x00000E68/4), 0x00000000}, - {(0x00000E6C/4), 0x00000000}, - {(0x00000E70/4), 0x00000000}, - {(0x00000E74/4), 0x00000000}, - {(0x00000E78/4), 0x00000000}, - {(0x00000E7C/4), 0x00000000}, - {(0x00000E80/4), 0x00000000}, - {(0x00000E84/4), 0x00000000}, - {(0x00000E88/4), 0x08000000}, - {(0x00000E8C/4), 0x00000000}, - {(0x00000E90/4), 0x00000000}, - {(0x00000E94/4), 0x00000000}, - {(0x00000E98/4), 0x00000000}, - {(0x00000E9C/4), 0x4B7FFFFF}, - {(0x00000EA0/4), 0x00000000}, - {(0x00000EA4/4), 0x00000000}, - {(0x00000EA8/4), 0x00000000}, - {(0x00000F00/4), 0x07FF0800}, - {(0x00000F04/4), 0x07FF0800}, - {(0x00000F08/4), 0x07FF0800}, - {(0x00000F0C/4), 0x07FF0800}, - {(0x00000F10/4), 0x07FF0800}, - {(0x00000F14/4), 0x07FF0800}, - {(0x00000F18/4), 0x07FF0800}, - {(0x00000F1C/4), 0x07FF0800}, - {(0x00000F20/4), 0x07FF0800}, - {(0x00000F24/4), 0x07FF0800}, - {(0x00000F28/4), 0x07FF0800}, - {(0x00000F2C/4), 0x07FF0800}, - {(0x00000F30/4), 0x07FF0800}, - {(0x00000F34/4), 0x07FF0800}, - {(0x00000F38/4), 0x07FF0800}, - {(0x00000F3C/4), 0x07FF0800}, - {(0x00000F40/4), 0x10000000}, - {(0x00000F44/4), 0x00000000}, - {(0x00000F50/4), 0x00006740}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006750}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F50/4), 0x00006760}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006770}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006780}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000067A0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AB0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AC0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006C10}, - {(0x00000F54/4), 0xBF800000}, - {(0x00000F50/4), 0x00007030}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007040}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007050}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007060}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007070}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007080}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007090}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x000070A0}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00006A80}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AA0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00000040}, - {(0x00000F54/4), 0x00000005}, - {(0x00000F50/4), 0x00006400}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x4B7FFFFF}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006410}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006420}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006430}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064C0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x477FFFFF}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x000064D0}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064E0}, - {(0x00000F54/4), 0xC4FFF000}, - {(0x00000F54/4), 0xC4FFF000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064F0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F40/4), 0x30000000}, - {(0x00000F44/4), 0x00000004}, - {(0x00000F48/4), 0x10000000}, - {(0x00000F4C/4), 0x00000000} -}; -static unsigned nv10TablePRAMIN[][2] = -{ - {0x00000000, 0x80000010}, - {0x00000001, 0x80011145}, - {0x00000002, 0x80000011}, - {0x00000003, 0x80011146}, - {0x00000004, 0x80000012}, - {0x00000005, 0x80011147}, - {0x00000006, 0x80000013}, - {0x00000007, 0x80011148}, - {0x00000008, 0x80000014}, - {0x00000009, 0x80011149}, - {0x0000000A, 0x80000015}, - {0x0000000B, 0x8001114A}, - {0x0000000C, 0x80000016}, - {0x0000000D, 0x80011150}, - {0x00000020, 0x80000000}, - {0x00000021, 0x80011142}, - {0x00000022, 0x80000001}, - {0x00000023, 0x80011143}, - {0x00000024, 0x80000002}, - {0x00000025, 0x80011144}, - {0x00000026, 0x80000003}, - {0x00000027, 0x8001114B}, - {0x00000028, 0x80000004}, - {0x00000029, 0x8001114C}, - {0x0000002A, 0x80000005}, - {0x0000002B, 0x8001114D}, - {0x0000002C, 0x80000006}, - {0x0000002D, 0x8001114E}, - {0x0000002E, 0x80000007}, - {0x0000002F, 0x8001114F}, - {0x00000500, 0x00003000}, - {0x00000501, 0x01FFFFFF}, - {0x00000502, 0x00000002}, - {0x00000503, 0x00000002}, -#ifdef __BIG_ENDIAN - {0x00000508, 0x01088043}, -#else - {0x00000508, 0x01008043}, -#endif - {0x0000050A, 0x00000000}, - {0x0000050B, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x0000050C, 0x01088019}, -#else - {0x0000050C, 0x01008019}, -#endif - {0x0000050E, 0x00000000}, - {0x0000050F, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000510, 0x01088018}, -#else - {0x00000510, 0x01008018}, -#endif - {0x00000512, 0x00000000}, - {0x00000513, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000514, 0x01088021}, -#else - {0x00000514, 0x01008021}, -#endif - {0x00000516, 0x00000000}, - {0x00000517, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000518, 0x0108805F}, -#else - {0x00000518, 0x0100805F}, -#endif - {0x0000051A, 0x00000000}, - {0x0000051B, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x0000051C, 0x0108804B}, -#else - {0x0000051C, 0x0100804B}, -#endif - {0x0000051E, 0x00000000}, - {0x0000051F, 0x00000000}, - {0x00000520, 0x0100A048}, - {0x00000521, 0x00000D01}, - {0x00000522, 0x11401140}, - {0x00000523, 0x00000000}, - {0x00000524, 0x0300A094}, - {0x00000525, 0x00000D01}, - {0x00000526, 0x11401140}, - {0x00000527, 0x00000000}, - {0x00000528, 0x0300A095}, - {0x00000529, 0x00000D01}, - {0x0000052A, 0x11401140}, - {0x0000052B, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x0000052C, 0x00080058}, -#else - {0x0000052C, 0x00000058}, -#endif - {0x0000052E, 0x11401140}, - {0x0000052F, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000530, 0x00080059}, -#else - {0x00000530, 0x00000059}, -#endif - {0x00000532, 0x11401140}, - {0x00000533, 0x00000000}, - {0x00000534, 0x0000005A}, - {0x00000536, 0x11401140}, - {0x00000537, 0x00000000}, - {0x00000538, 0x0000005B}, - {0x0000053A, 0x11401140}, - {0x0000053B, 0x00000000}, - {0x0000053C, 0x00000093}, - {0x0000053E, 0x11401140}, - {0x0000053F, 0x00000000}, -#ifdef __BIG_ENDIAN - {0x00000540, 0x0308A01C}, -#else - {0x00000540, 0x0300A01C}, -#endif - {0x00000542, 0x11401140}, - {0x00000543, 0x00000000} -}; -static unsigned nv10TablePRAMIN_8BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000302}, - {0x0000050D, 0x00000302}, - {0x00000511, 0x00000202}, - {0x00000515, 0x00000302}, - {0x00000519, 0x00000302}, - {0x0000051D, 0x00000302}, - {0x0000052D, 0x00000302}, - {0x0000052E, 0x00000302}, - {0x00000535, 0x00000000}, - {0x00000539, 0x00000000}, - {0x0000053D, 0x00000000}, - {0x00000541, 0x00000302} -}; -static unsigned nv10TablePRAMIN_15BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000902}, - {0x0000050D, 0x00000902}, - {0x00000511, 0x00000802}, - {0x00000515, 0x00000902}, - {0x00000519, 0x00000902}, - {0x0000051D, 0x00000902}, - {0x0000052D, 0x00000902}, - {0x0000052E, 0x00000902}, - {0x00000535, 0x00000902}, - {0x00000539, 0x00000902}, - {0x0000053D, 0x00000902}, - {0x00000541, 0x00000902} -}; -static unsigned nv10TablePRAMIN_16BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000C02}, - {0x0000050D, 0x00000C02}, - {0x00000511, 0x00000B02}, - {0x00000515, 0x00000C02}, - {0x00000519, 0x00000C02}, - {0x0000051D, 0x00000C02}, - {0x0000052D, 0x00000C02}, - {0x0000052E, 0x00000C02}, - {0x00000535, 0x00000C02}, - {0x00000539, 0x00000C02}, - {0x0000053D, 0x00000C02}, - {0x00000541, 0x00000C02} -}; -static unsigned nv10TablePRAMIN_32BPP[][2] = -{ - /* 0xXXXXXX01 For MSB mono format */ - /* 0xXXXXXX02 For LSB mono format */ - {0x00000509, 0x00000E02}, - {0x0000050D, 0x00000E02}, - {0x00000511, 0x00000D02}, - {0x00000515, 0x00000E02}, - {0x00000519, 0x00000E02}, - {0x0000051D, 0x00000E02}, - {0x0000052D, 0x00000E02}, - {0x0000052E, 0x00000E02}, - {0x00000535, 0x00000E02}, - {0x00000539, 0x00000E02}, - {0x0000053D, 0x00000E02}, - {0x00000541, 0x00000E02} -}; - diff --git a/drivers/video/fbdev/riva/rivafb-i2c.c b/drivers/video/fbdev/riva/rivafb-i2c.c deleted file mode 100644 index 6a183375ced1..000000000000 --- a/drivers/video/fbdev/riva/rivafb-i2c.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c - * - * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> - * - * Copyright 2004 Antonino A. Daplas <adaplas @pol.net> - * - * Based on radeonfb-i2c.c - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/pci.h> -#include <linux/fb.h> -#include <linux/jiffies.h> - -#include <asm/io.h> - -#include "rivafb.h" -#include "../edid.h" - -static void riva_gpio_setscl(void* data, int state) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; - - if (state) - val |= 0x20; - else - val &= ~0x20; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); -} - -static void riva_gpio_setsda(void* data, int state) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; - - if (state) - val |= 0x10; - else - val &= ~0x10; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); - VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); -} - -static int riva_gpio_getscl(void* data) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val = 0; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); - if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04) - val = 1; - - return val; -} - -static int riva_gpio_getsda(void* data) -{ - struct riva_i2c_chan *chan = data; - struct riva_par *par = chan->par; - u32 val = 0; - - VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); - if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08) - val = 1; - - return val; -} - -static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name, - unsigned int i2c_class) -{ - int rc; - - strcpy(chan->adapter.name, name); - chan->adapter.owner = THIS_MODULE; - chan->adapter.class = i2c_class; - chan->adapter.algo_data = &chan->algo; - chan->adapter.dev.parent = &chan->par->pdev->dev; - chan->algo.setsda = riva_gpio_setsda; - chan->algo.setscl = riva_gpio_setscl; - chan->algo.getsda = riva_gpio_getsda; - chan->algo.getscl = riva_gpio_getscl; - chan->algo.udelay = 40; - chan->algo.timeout = msecs_to_jiffies(2); - chan->algo.data = chan; - - i2c_set_adapdata(&chan->adapter, chan); - - /* Raise SCL and SDA */ - riva_gpio_setsda(chan, 1); - riva_gpio_setscl(chan, 1); - udelay(20); - - rc = i2c_bit_add_bus(&chan->adapter); - if (rc == 0) - dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name); - else { - dev_warn(&chan->par->pdev->dev, - "Failed to register I2C bus %s.\n", name); - chan->par = NULL; - } - - return rc; -} - -void riva_create_i2c_busses(struct riva_par *par) -{ - par->chan[0].par = par; - par->chan[1].par = par; - par->chan[2].par = par; - - par->chan[0].ddc_base = 0x36; - par->chan[1].ddc_base = 0x3e; - par->chan[2].ddc_base = 0x50; - riva_setup_i2c_bus(&par->chan[0], "BUS1", I2C_CLASS_HWMON); - riva_setup_i2c_bus(&par->chan[1], "BUS2", 0); - riva_setup_i2c_bus(&par->chan[2], "BUS3", 0); -} - -void riva_delete_i2c_busses(struct riva_par *par) -{ - int i; - - for (i = 0; i < 3; i++) { - if (!par->chan[i].par) - continue; - i2c_del_adapter(&par->chan[i].adapter); - par->chan[i].par = NULL; - } -} - -int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid) -{ - u8 *edid = NULL; - - if (par->chan[conn].par) - edid = fb_ddc_read(&par->chan[conn].adapter); - - if (out_edid) - *out_edid = edid; - if (!edid) - return 1; - - return 0; -} - diff --git a/drivers/video/fbdev/riva/rivafb.h b/drivers/video/fbdev/riva/rivafb.h deleted file mode 100644 index 593297ca2b20..000000000000 --- a/drivers/video/fbdev/riva/rivafb.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __RIVAFB_H -#define __RIVAFB_H - -#include <linux/fb.h> -#include <video/vga.h> -#include <linux/i2c.h> -#include <linux/i2c-algo-bit.h> - -#include "riva_hw.h" - -/* GGI compatibility macros */ -#define NUM_SEQ_REGS 0x05 -#define NUM_CRT_REGS 0x41 -#define NUM_GRC_REGS 0x09 -#define NUM_ATC_REGS 0x15 - -/* I2C */ -#define DDC_SCL_READ_MASK (1 << 2) -#define DDC_SCL_WRITE_MASK (1 << 5) -#define DDC_SDA_READ_MASK (1 << 3) -#define DDC_SDA_WRITE_MASK (1 << 4) - -/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. - * From KGI originally. */ -struct riva_regs { - u8 attr[NUM_ATC_REGS]; - u8 crtc[NUM_CRT_REGS]; - u8 gra[NUM_GRC_REGS]; - u8 seq[NUM_SEQ_REGS]; - u8 misc_output; - RIVA_HW_STATE ext; -}; - -struct riva_par; - -struct riva_i2c_chan { - struct riva_par *par; - unsigned long ddc_base; - struct i2c_adapter adapter; - struct i2c_algo_bit_data algo; -}; - -struct riva_par { - RIVA_HW_INST riva; /* interface to riva_hw.c */ - u32 pseudo_palette[16]; /* default palette */ - u32 palette[16]; /* for Riva128 */ - u8 __iomem *ctrl_base; /* virtual control register base addr */ - unsigned dclk_max; /* max DCLK */ - - struct riva_regs initial_state; /* initial startup video mode */ - struct riva_regs current_state; -#ifdef CONFIG_X86 - struct vgastate state; -#endif - struct mutex open_lock; - unsigned int ref_count; - unsigned char *EDID; - unsigned int Chipset; - int forceCRTC; - Bool SecondCRTC; - int FlatPanel; - struct pci_dev *pdev; - int cursor_reset; - int wc_cookie; - struct riva_i2c_chan chan[3]; -}; - -void riva_common_setup(struct riva_par *); -unsigned long riva_get_memlen(struct riva_par *); -unsigned long riva_get_maxdclk(struct riva_par *); -void riva_delete_i2c_busses(struct riva_par *par); -void riva_create_i2c_busses(struct riva_par *par); -int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid); - -#endif /* __RIVAFB_H */ |