cpu/arm1136: Remove arm1136 support

After clearing the support for omap2420h4 and omap2430sdp the files in
cpu/arm1136 and include/asm/arch-arm1136 directories are not being
used so we can remove it.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>

14 files changed, 1 insertions, 1894 deletions

diff --git a/README b/README
index d7b16dd..2ca51eb 100644
--- a/README
+++ b/README
@@ -36,10 +36,6 @@ Nand booting.
 Status:
 =======
 
-The support for Texas Instruments H4 board (OMAP2420) has been implemented
-and tested. (Nov 2004)
-The support for Texas Instruments 2430SDP board (OMAP2430) has been implemented
-and tested. (Jul 2006)
 The support for Texas Instruments 3430SDP board (OMAP3430) has been implemented
 and tested. (Dec 2006)
 
@@ -55,15 +51,10 @@ Directory Hierarchy:
 - drivers	Commonly used device drivers
 - lib		Libraries
  
-- cpu/arm926ejs Files specific to ARM 926 CPUs
 - cpu/arm1136 Files specific to ARM 1136 CPUs
 - cpu/omap3 Files specific to ARM CortexA8 CPU
 
  
-- board/omap2420h4
-		Files specific to OMAP 2420 H4 boards
-- board/omap2430sdp
-		Files specific to OMAP 2430 2430sdp boards
 - board/omap3430sdp
 		Files specific to OMAP 3420sdp boards
 
@@ -116,8 +107,7 @@ You can't use FlashWriterNand because it uses ROM code ECC style.
 
 Implemenation notes:
 ====================
-H4 support NAND flash booting
-2430sdp & 3430sdp support OneNAND booting
+3430sdp support OneNAND booting
 
 
 
diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile
deleted file mode 100644
index b556419..0000000
--- a/cpu/arm1136/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).a
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) crv $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk
deleted file mode 100644
index 3106824..0000000
--- a/cpu/arm1136/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8
-
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-#
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
deleted file mode 100644
index 1168fb9..0000000
--- a/cpu/arm1136/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * udelay() is CPU specific code
- */
-
-#include <common.h>
-
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-#define C1_WB		(1<<3)		/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
-int cpu_init (void)
-{
-	int i;
-
-	/* turn off I/D-cache */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-	/* flush I/D-cache */
-	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  // invalidate both caches and flush btb
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); // mem barrier to sync things
-
-	return 0;
-}
-
-
-
-
-
-
-
-
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
deleted file mode 100644
index 16108d0..0000000
--- a/cpu/arm1136/start.S
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- *  Copyright (c) 2004  Texas Instruments
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- *  Copyright (c) 2004	Jian Zhang <jzhang@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-.globl _start
-_start:	
-	b	reset
- 	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-
-_hang:
- 	.word do_hang
-	
-	.word 0x12345678
-	.word 0x12345678
-	.word 0x12345678
-	.word 0x12345678
-	.word 0x12345678
-	.word 0x12345678
-	.word 0x12345678 /* now 16*4=64 */
-
-.global _end_vect
-_end_vect:
-
-	.balignl 16,0xdeadbeef
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
-
-.globl _bss_end
-_bss_end:
-	.word _end
-
-/*
- * the actual reset code
- */
-
-reset: 
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/* Copy vectors to mask ROM indirect addr */ 
-	adr     r0, _start              /* r0 <- current position of code   */
-	add     r0, r0, #4				/* skip reset vector			*/
-	mov     r2, #64                 /* r2 <- size to copy  */
-	add     r2, r0, r2              /* r2 <- source end address         */
-	mov     r1, #0x40000000         /* build vect addr */
-	mov     r3, #0x00200000
-	add     r1, r1, r3
-	mov     r3, #0xf800
-	add     r1, r1, r3
-next:
-	ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-	stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-	cmp     r0, r2                  /* until source end address [r2]    */
-	bne     next                    /* loop until equal */
-
-	bl	cpy_clk_code            /* put dpll adjust code behind vectors */
- 
-	/* the mask ROM code should have PLL and others stable */
-	bl  cpu_init_crit
-
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp r0, r1                  /* don't reloc during debug         */
-	/* beq stack_setup */
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	sp, r0, #128		/* leave 32 words for abort-stack    */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
-
-//clbss_l:str	r2, [r0]		/* clear loop...                    */
-//	add	r0, r0, #4
-//	cmp	r0, r1
-//	bne	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:	.word start_armboot
-
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-#ifndef CONFIG_ICACHE_OFF
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-#endif
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-         * Jump to board specific initialization... The Mask ROM will have already initialized
-         * basic memory.  Go here to bump up clock rate and handle wake up conditions.
-	 */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* pass on info about skipping some init portions */
-	moveq   r0,#0x1                 /* flag to skip prcm and sdrc setup */
-	movne   r0,#0x0
-
-//mov r0, #1    /* this skip memory init */
-
-	mov	ip, lr          /* persevere link reg across call */
-	bl	platformsetup   /* go setup pll,mux,memory */
-
-	mov	lr, ip          /* restore link */
-	mov	pc, lr          /* back to my caller */
-
-
-/*
- * exception handler
- */
- 	.align  5
-do_hang:
-	ldr	sp, _TEXT_BASE		/* use 32 words abort stack */
-   	bl	hang				/* hang and never return */
-
diff --git a/include/asm/arch-arm1136/bits.h b/include/asm/arch-arm1136/bits.h
deleted file mode 100644
index dc3273e..0000000
--- a/include/asm/arch-arm1136/bits.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software;  you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0  (1<<0)
-#define BIT1  (1<<1)
-#define BIT2  (1<<2)
-#define BIT3  (1<<3)
-#define BIT4  (1<<4)
-#define BIT5  (1<<5)
-#define BIT6  (1<<6)
-#define BIT7  (1<<7)
-#define BIT8  (1<<8)
-#define BIT9  (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
-
diff --git a/include/asm/arch-arm1136/clocks.h b/include/asm/arch-arm1136/clocks.h
deleted file mode 100644
index 8e00d2e..0000000
--- a/include/asm/arch-arm1136/clocks.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS  0x1
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK        0xc
-#define DPLL_LOCK        0x3   /* DPLL lock */
-#define LDELAY           12000000
-
-#if defined(CONFIG_OMAP242X)
-#include <asm/arch/clocks242x.h>
-#elif defined(CONFIG_OMAP243X)
-#include <asm/arch/clocks243x.h>
-#endif
-
-#define S12M		12000000
-#define S13M		13000000
-#define S19_2M		19200000
-#define S24M		24000000
-#define S26M		26000000
-#define S38_4M		38400000
-
-#endif
-
-
-
-
-
-
-
-
diff --git a/include/asm/arch-arm1136/clocks242x.h b/include/asm/arch-arm1136/clocks242x.h
deleted file mode 100644
index 0ae1c4e..0000000
--- a/include/asm/arch-arm1136/clocks242x.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP242X_CLOCKS_H_
-#define _OMAP242X_CLOCKS_H_
-
-/****************************************************************************;
-; PRCM Scheme I
-;
-; Enable clocks and DPLL for:
-;  DPLL=330, 	DPLLout=660   	M=1,N=55   CM_CLKSEL1_PLL[21:8]  12/2*55
-;  Core=660  	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
-;  MPUF=330   	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
-;  DSPF=220     (dsp domain)    3          CM_CLKSEL_DSP[4:0]
-;  DSPI=110                     6          CM_CLKSEL_DSP[6:5]
-;  DSP_S        activated	               CM_CLKSEL_DSP[7]
-;  IVAF=165     (dsp domain)    4          CM_CLKSEL_DSP[12:8]
-;  IVAF=82.5       auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S          bypass                   CM_CLKSEL_DSP[13]
-;  GFXF=82.5    (gfx domain)	8          CM_CLKSEL_FGX[2:0]
-;  SSI_SSRF=220                 3          CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=110    auto
-;  L3=165Mhz    (sdram)         4          CM_CLKSEL1_CORE[4:0]
-;  L4=82.5Mhz                   8          
-;  C_L4_USB=41.25               16         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define I_DPLL_OUT_X2   0x2    /* x2 core out */
-#define I_MPU_DIV       0x2    /* mpu = core/2 */
-#define I_DSP_DIV       0x3c3  /* dsp & iva divider */
-#define I_GFX_DIV       0x2
-#define I_BUS_DIV       0x04601044
-#ifdef INPUT_CLK_13MHZ
-#define I_DPLL_330      0x0114AC00  /* 13MHz */
-#else
-#define I_DPLL_330      0x01837100  /* 12MHz */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II   <tested>
-;
-; Enable clocks and DPLL for:
-;  DPLL=300, 	DPLLout=600   	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
-;  Core=600  	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
-;  MPUF=300   	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
-;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
-;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
-;  DSP_S          bypass	               CM_CLKSEL_DSP[7]
-;  IVAF=200    (dsp domain)    3          CM_CLKSEL_DSP[12:8]
-;  IVAF=100        auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S          bypass                  CM_CLKSEL_DSP[13]
-;  GFXF=50      (gfx domain)	12         CM_CLKSEL_FGX[2:0]
-;  SSI_SSRF=200                 3         CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=100     auto
-;  L3=100Mhz (sdram)            6         CM_CLKSEL1_CORE[4:0]
-;  L4=100Mhz                    6
-;  C_L4_USB=50                 12         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2   0x2    /* x2 core out */
-#define II_MPU_DIV       0x2    /* mpu = core/2 */
-#define II_DSP_DIV       0x343  /* dsp & iva divider */
-#define II_GFX_DIV       0x2
-#define II_BUS_DIV       0x04601026
-#ifdef INPUT_CLK_13MHZ
-#define II_DPLL_300      0x0112CC00  /* 13MHz */
-#else
-#define II_DPLL_300      0x01832100  /* 12MHz */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme III  <tested>
-;
-; Enable clocks and DPLL for:
-;  DPLL=266, 	DPLLout=532   	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
-;  Core=532  	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
-;  MPUF=266   	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
-;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
-;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
-;  DSP_S         ACTIVATED	            CM_CLKSEL_DSP[7]
-;  IVAF=88.67    (dsp domain)   /3          CM_CLKSEL_DSP[12:8]
-;  IVAF=88.67        auto
-;  IVAI            auto
-;  IVA_MPU         auto
-;  IVA_S         ACTIVATED                  CM_CLKSEL_DSP[13]
-;  GFXF=66.5      (gfx domain)	/8          CM_CLKSEL_FGX[2:0]:
-;  SSI_SSRF=177.3               /3          CM_CLKSEL1_CORE[24:20]
-;  SSI_SSTF=88.67     auto
-;  L3=133Mhz (sdram)            /4          CM_CLKSEL1_CORE[4:0]
-;  L4=66.5Mhz                   /8
-;  C_L4_USB=33.25               /16         CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2   0x2    /* x2 core out */
-#define III_MPU_DIV       0x2    /* mpu = core/2 */
-#define III_DSP_DIV       0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV       0x2
-#define III_BUS_DIV       0x08301044
-#ifdef INPUT_CLK_13MHZ
-#define III_DPLL_266      0x0110AC00   /* 13MHz */
-#else
-#define III_DPLL_266      0x01885500   /* 12MHz */
-#endif
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_I
-# define DPLL_OUT         I_DPLL_OUT_X2
-# define MPU_DIV          I_MPU_DIV
-# define DSP_DIV          I_DSP_DIV
-# define GFX_DIV          I_GFX_DIV
-# define BUS_DIV          I_BUS_DIV
-# define DPLL_VAL         I_DPLL_266
-#elif PRCM_CONFIG_II
-# define DPLL_OUT         II_DPLL_OUT_X2
-# define MPU_DIV          II_MPU_DIV
-# define DSP_DIV          II_DSP_DIV
-# define GFX_DIV          II_GFX_DIV
-# define BUS_DIV          II_BUS_DIV
-# define DPLL_VAL         II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT         III_DPLL_OUT_X2
-# define MPU_DIV          III_MPU_DIV
-# define DSP_DIV          III_DSP_DIV
-# define GFX_DIV          III_GFX_DIV
-# define BUS_DIV          III_BUS_DIV
-# define DPLL_VAL         III_DPLL_266
-#endif
-
-#endif
diff --git a/include/asm/arch-arm1136/clocks243x.h b/include/asm/arch-arm1136/clocks243x.h
deleted file mode 100644
index 18d2e46..0000000
--- a/include/asm/arch-arm1136/clocks243x.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
-  */
-#ifndef _OMAP243X_CLOCKS_H_
-#define _OMAP243X_CLOCKS_H_
-
-/* cm_clksel core fields not ratio governed */
-#define RX_CLKSEL_DSS1		(0x10 << 8)
-#define RX_CLKSEL_DSS2		(0x0 << 13)
-#define RX_CLKSEL_SSI		(0x5 << 20)
-
-/* 2430 Ratio's */
-/* 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3		(4 << 0)
-#define R1_CLKSEL_L4		(2 << 5)
-#define R1_CLKSEL_USB		(4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL	R1_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \
-                                | RX_CLKSEL_DSS1 | R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU		(2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL	R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP		(2 << 0)
-#define R1_CLKSEL_DSP_IF	(2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL	R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX		(2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL	R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM		(4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL	R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3		(6 << 0)
-#define R2_CLKSEL_L4		(2 << 5)
-#define R2_CLKSEL_USB		(2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL	R2_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \
-                                | RX_CLKSEL_DSS1 | R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU		(2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL	R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP		(2 << 0)
-#define R2_CLKSEL_DSP_IF	(3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL	R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX		(2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL    R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM		(6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL	R2_CLKSEL_MDM
-
-/* 2430-Ratio Boot */
-#define RB_CLKSEL_L3		(1 << 0)
-#define RB_CLKSEL_L4		(1 << 5)
-#define RB_CLKSEL_USB		(1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL	RB_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \
-                                | RX_CLKSEL_DSS1 | RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU		(1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL	RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP		(1 << 0)
-#define RB_CLKSEL_DSP_IF	(1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL	RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX		(1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL	RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM		(1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL	RB_CLKSEL_MDM
-
-/* 2430 Target modes: Along with each configuration the CPU has several modes
- * which goes along with them. Modes mainly are the addition of descrite DPLL
- * combinations to go along with a ratio.
- */
-/* hardware goverend */
-#define MX_48M_SRC		(0 << 3)
-#define MX_54M_SRC		(0 << 5)
-#define MX_APLLS_CLIKIN_12	(3 << 23)
-#define MX_APLLS_CLIKIN_13	(2 << 23)
-#define MX_APLLS_CLIKIN_19_2	(0 << 23)
-
-/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */
-
-/* boot (boot) */
-#define MB_DPLL_MULT				(1 << 12)
-#define MB_DPLL_DIV					(0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL     MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \
-                                    | MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL    MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \
-                                    | MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL    MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \
-                                    | MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/* #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */
-
-#define M2_DPLL_MULT_12		        (55 << 12)
-#define M2_DPLL_DIV_12		        (1 << 8)
-#define M2_CM_CLKSEL1_PLL_12_VAL	MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_12 \
-                                    | M2_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */
-#define M2_DPLL_MULT_13		        (330 << 12)
-#define M2_DPLL_DIV_13		        (12 << 8)
-#define M2_CM_CLKSEL1_PLL_13_VAL	MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_13 \
-                                    | M2_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M2_DPLL_MULT_19		        (275 << 12)
-#define M2_DPLL_DIV_19		        (15 << 8)
-#define M2_CM_CLKSEL1_PLL_19_VAL	MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_19 \
-                                    | M2_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #3   (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */
-#define M3_DPLL_MULT_12		        (55 << 12)
-#define M3_DPLL_DIV_12		        (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL	MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_12 \
-                                    | M3_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13		        (330 << 12)
-#define M3_DPLL_DIV_13		        (12 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL	MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_13 \
-                                    | M3_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19		        (275 << 12)
-#define M3_DPLL_DIV_19		        (15 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL	MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_19 \
-                                    | M3_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz*/
-#define M4_DPLL_MULT_12		        (133 << 12)
-#define M4_DPLL_DIV_12		        (3 << 8)
-#define M4_CM_CLKSEL1_PLL_12_VAL	MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_12 \
-                                    | M4_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M4_DPLL_MULT_13		        (399 << 12)
-#define M4_DPLL_DIV_13		        (12 << 8)
-#define M4_CM_CLKSEL1_PLL_13_VAL	MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_13 \
-                                    | M4_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M4_DPLL_MULT_19		        (145 << 12)
-#define M4_DPLL_DIV_19		        (6 << 8)
-#define M4_CM_CLKSEL1_PLL_19_VAL	MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_19 \
-                                    | M4_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz, L3=133MHz */
-#define M5A_DPLL_MULT_12	        (133 << 12)
-#define M5A_DPLL_DIV_12		        (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL	MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_12 \
-                                    | M5A_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13	        (266 << 12)
-#define M5A_DPLL_DIV_13		        (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL	MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_13 \
-                                    | M5A_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19	        (180 << 12)
-#define M5A_DPLL_DIV_19		        (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL	MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_19 \
-                                    | M5A_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #5b  (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */
-#define M5B_DPLL_MULT_12	        (50 << 12)
-#define M5B_DPLL_DIV_12		        (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL	MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_12 \
-                                    | M5B_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13	        (200 << 12)
-#define M5B_DPLL_DIV_13		        (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL	MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_13 \
-                                    | M5B_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19	        (125 << 12)
-#define M5B_DPLL_DIV_19		        (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL	MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_19 \
-                                    | M5B_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* 2430 - chassis (sedna) */
-	/* 165 (ratio1) same as above #2 */
-	/* 150 (ratio1)*/
-	/* 133 (ratio2) same as above #4 */
-	/* 110 (ratio2) same as above #3*/
-	/* 104 (ratio2)*/
-	/* boot (boot) */
-
-/* high and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL   (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL   (1 << 0)
-
-/* set defaults for boot up */
-#if defined(PRCM_CONFIG_2)     /* ARM-330MHz IVA2-330MHz L3-165MHz */
-# define DPLL_OUT	MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV	R1_CLKSEL_MPU
-# define DSP_DIV	R1_CM_CLKSEL_DSP_VAL
-# define GFX_DIV	R1_CM_CLKSEL_GFX_VAL
-# define BUS_DIV	R1_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL	M2_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV	R2_CM_CLKSEL_MDM_VAL
-#elif defined(PRCM_CONFIG_3)     /* ARM-330MHz IVA2-330MHz L3-110MHz */
-# define DPLL_OUT	MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV	R2_CLKSEL_MPU
-# define DSP_DIV	R2_CM_CLKSEL_DSP_VAL
-# define GFX_DIV	R2_CM_CLKSEL_GFX_VAL
-# define BUS_DIV	R2_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL	M3_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV	R2_CM_CLKSEL_MDM_VAL
-#elif defined(PRCM_CONFIG_5A)  /* ARM-266MHz IVA2-266MHz L3-133MHz */
-# define DPLL_OUT	MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV	R1_CLKSEL_MPU
-# define DSP_DIV	R1_CM_CLKSEL_DSP_VAL
-# define GFX_DIV	R1_CM_CLKSEL_GFX_VAL
-# define BUS_DIV	R1_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL	M5A_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV	R2_CM_CLKSEL_MDM_VAL
-#elif defined(PRCM_CONFIG_5B)  /* ARM-200MHz IVA2-200MHz L3-100MHz */
-# define DPLL_OUT	MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV	R1_CLKSEL_MPU
-# define DSP_DIV	R1_CM_CLKSEL_DSP_VAL
-# define GFX_DIV	R1_CM_CLKSEL_GFX_VAL
-# define BUS_DIV	R1_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL	M5B_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV	R1_CM_CLKSEL_MDM_VAL
-#endif
-
-#endif
diff --git a/include/asm/arch-arm1136/mem.h b/include/asm/arch-arm1136/mem.h
deleted file mode 100644
index 2a3da73..0000000
--- a/include/asm/arch-arm1136/mem.h
+++ /dev/null
@@ -1,383 +0,0 @@
-
-/*
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_MEM_H_
-#define _OMAP24XX_MEM_H_
-
-#define SDRC_CS0_OSET    0x0
-#define SDRC_CS1_OSET    0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-/* struct's for holding data tables for current boards, they are getting used
-   early in init when NO global access are there */
-struct sdrc_data_s {
-	u32    sdrc_sharing;
-	u32    sdrc_mdcfg_0_ddr;
-	u32    sdrc_mdcfg_0_sdr;
-	u32    sdrc_actim_ctrla_0;
-	u32    sdrc_actim_ctrlb_0;
-	u32    sdrc_rfr_ctrl;
-	u32    sdrc_mr_0_ddr;
-	u32    sdrc_mr_0_sdr;
-	u32    sdrc_dllab_ctrl;
-} /*__attribute__ ((packed))*/;
-typedef struct sdrc_data_s sdrc_data_t;
-
-typedef enum {
-	STACKED		= 0,
-	IP_DDR		= 1,
-	COMBO_DDR	= 2,
-	IP_SDR	 	= 3,
-} mem_t;
-
-#endif
-
-/* set the 243x-SDRC incoming address convention */
-#if defined(SDRC_B_R_C)
-#define B_ALL	(0 << 6)	/* bank-row-column */
-#elif defined(SDRC_B1_R_B0_C)
-#define B_ALL	(1 << 6)	/* bank1-row-bank0-column */
-#elif defined(SDRC_R_B_C)
-#define B_ALL	(2 << 6)	/* row-bank-column */
-#endif
-
-/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING		0x00000100
-#define H4_2420_SDRC_MDCFG_0_SDR	0x00D04010 /* discrete sdr module */
-#define H4_2420_SDRC_MR_0_SDR		0x00000031
-#define H4_2420_SDRC_MDCFG_0_DDR	0x01702011 /* descrite ddr module */
-#define SDP_2430_SDRC_MDCFG_0_DDR	(0x02584019|B_ALL) /* Infin ddr module */
-#define H4_2420_COMBO_MDCFG_0_DDR	0x00801011 /* combo module */
-#define H4_2420_SDRC_MR_0_DDR		0x00000032
-
-#define H4_2422_SDRC_SHARING		0x00004b00
-#define H4_2422_SDRC_MDCFG_MONO_DDR	0x01A02011 /* stacked mono die ddr on 2422 */
-#define H4_2422_SDRC_MDCFG_0_DDR	0x00801011 /* stacked dual die ddr on 2422 */
-#define H4_2422_SDRC_MR_0_DDR		0x00000032
-
-#define H4_2423_SDRC_SHARING		0x00004900 /* 2420POP board cke1 not connected */
-#define H4_2423_SDRC_MDCFG_0_DDR	0x01A02011 /* stacked dual die ddr on 2423 */
-#define H4_2423_SDRC_MDCFG_1_DDR	0x00801011 /* stacked dual die ddr on 2423 */
-
-/* ES1 work around timings */
-#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1	0x9bead909  /* 165Mhz for use with 100/133 */
-#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1  0x00000020
-#define H4_242x_SDRC_RFR_CTRL_ES1	0x00002401  /* use over refresh for ES1 */
-
-/* optimized timings good for current shipping parts */
-#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz   0x5A59B485
-#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz   0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz   0x8BA6E6C8 /* temp warn 0 settings */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz   0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz	    0x0002da01
-#define H4_242X_SDRC_RFR_CTRL_133MHz	    0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */
-#define SDP_24XX_SDRC_RFR_CTRL_165MHz	    0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */
-#define H4_242X_SDRC_DLLAB_CTRL_100MHz      0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/
-#define H4_242X_SDRC_DLLAB_CTRL_133MHz      0x0000690E /* 90deg, for ES2 */
-#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz     0x0000170C /* 72deg, code will recalc dll load */
-
-/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns
- *	TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
- *	TDPL = 15/7.5	= 2
- *	TRRD = 15/2.5	= 2
- *	TRCD = 22.5/7.5	= 3
- *	TRP = 22.5/7.5	= 3
- *	TRAS = 45/7.5	= 6
- *	TRC = 65/7.5	= 8.6->9
- *	TRFC = 75/7.5	= 10
- *   ACTIMB
- *	TCKE = 2	<new in 2430>
- *	XSR = 120/7.5 = 16
- */
-#define TDAL_133   5
-#define TDPL_133   2
-#define TRRD_133   2
-#define TRCD_133   3
-#define TRP_133    3
-#define TRAS_133   6
-#define TRC_133    9
-#define TRFC_133  10
-#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \
-		(TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133))
-
-#define TCKE_133   2
-#define XSR_133   16
-#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0))
-
-/* Infineon part of 2430SDP (165MHz optimized) 6.06ns
- *   ACTIMA
- *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- *	TDPL (Twr) = 15/6	= 2.5 -> 3
- *	TRRD = 12/6	= 2
- *	TRCD = 18/6	= 3
- *	TRP = 18/6	= 3
- *	TRAS = 42/6	= 7
- *	TRC = 60/6	= 10
- *	TRFC = 72/6	= 12
- *   ACTIMB
- *	TCKE = 2	<new in 2430>
- *	XSR = 120/6 = 20
- */
-#define TDAL_165   6
-#define TDPL_165   3
-#define TRRD_165   2
-#define TRCD_165   3
-#define TRP_165    3
-#define TRAS_165   7
-#define TRC_165   10
-#define TRFC_165  12
-#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \
-		(TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165))
-
-#define TCKE_165   2
-#define XSR_165   20
-#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0))
-
-#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
-# define H4_2420_SDRC_ACTIM_CTRLA_0  H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133
-# define H4_2420_SDRC_ACTIM_CTRLB_0  H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL       H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_DLLAB_CTRL     H4_242X_SDRC_DLLAB_CTRL_100MHz
-# define SDP_2430_SDRC_DLLAB_CTRL    0x0000730E
-# define H4_2422_SDRC_ACTIM_CTRLA_0  H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0  H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL       H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL     H4_242X_SDRC_DLLAB_CTRL_100MHz
-#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3)
-# define H4_2420_SDRC_ACTIM_CTRLA_0  H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133
-# define H4_2420_SDRC_ACTIM_CTRLB_0  H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL       H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_DLLAB_CTRL     H4_242X_SDRC_DLLAB_CTRL_133MHz
-# define SDP_2430_SDRC_DLLAB_CTRL    0x0000730E
-# define H4_2422_SDRC_ACTIM_CTRLA_0  H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0  H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2422_SDRC_RFR_CTRL       H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2422_SDRC_DLLAB_CTRL     H4_242X_SDRC_DLLAB_CTRL_133MHz
-#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2)
-# define H4_2420_SDRC_ACTIM_CTRLA_0  V_ACTIMA_165 
-# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-# define H4_2420_SDRC_ACTIM_CTRLB_0  V_ACTIMB_165 
-# define H4_2420_SDRC_RFR_CTRL       SDP_24XX_SDRC_RFR_CTRL_165MHz
-# define H4_2420_SDRC_DLLAB_CTRL     SDP_24XX_SDRC_DLLAB_CTRL_165MHz
-# define SDP_2430_SDRC_DLLAB_CTRL    SDP_24XX_SDRC_DLLAB_CTRL_165MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0  V_ACTIMA_165 
-# define H4_2422_SDRC_ACTIM_CTRLB_0  V_ACTIMB_165 
-# define H4_2422_SDRC_RFR_CTRL       SDP_24XX_SDRC_RFR_CTRL_165MHz
-# define H4_2422_SDRC_DLLAB_CTRL     SDP_24XX_SDRC_DLLAB_CTRL_165MHz
-#endif
-
-/*
- * GPMC settings -
- * Definitions is as per the following format
- * # define <PART>_GPMC_CONFIG<x> <value>
- * Where:
- * PART is the part name e.g. STNOR - Intel Strata Flash
- * x is GPMC config registers from 1 to 6 (there will be 6 macros)
- * Value is corresponding value
- *
- * For every valid PRCM configuration there should be only one definition of the same.
- * if values are independent of the board, this definition will be present in this file
- * if values are dependent on the board, then this should go into corresponding mem-boardName.h file
- *
- * Currently valid part Names are (PART):
- * STNOR - Intel Strata Flash
- * SMNAND - Samsung NAND
- * MPDB - H4 MPDB board
- * SBNOR - Sibley NOR
- * ONNAND - Samsung One NAND
- *
- * include/configs/file.h contains the following defn - for all CS we are interested
- * #define OMAP24XX_GPMC_CSx PART
- * #define OMAP24XX_GPMC_CSx_SIZE Size
- * #define OMAP24XX_GPMC_CSx_MAP Map
- * Where:
- * x - CS number
- * PART - Part Name as defined above
- * SIZE - how big is the mapping to be
- *   GPMC_SIZE_128M - 0x8
- *   GPMC_SIZE_64M  - 0xC
- *   GPMC_SIZE_32M  - 0xE
- *   GPMC_SIZE_16M  - 0xF
- * MAP  - Map this CS to which address(GPMC address space)- Absolute address
- *   >>24 before being used.
- */
-
-#define GPMC_SIZE_256M  0x0
-#define GPMC_SIZE_128M  0x8
-#define GPMC_SIZE_64M   0xC
-#define GPMC_SIZE_32M   0xE
-#define GPMC_SIZE_16M   0xF
-
-#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */
-# define SMNAND_GPMC_CONFIG1 0x0
-# define SMNAND_GPMC_CONFIG2 0x00141400
-# define SMNAND_GPMC_CONFIG3 0x00141400
-# define SMNAND_GPMC_CONFIG4 0x0F010F01
-# define SMNAND_GPMC_CONFIG5 0x010C1414
-# define SMNAND_GPMC_CONFIG6 0x00000A80
-# define STNOR_GPMC_CONFIG1  0x3
-# define STNOR_GPMC_CONFIG2  0x000f0f01
-# define STNOR_GPMC_CONFIG3  0x00050502
-# define STNOR_GPMC_CONFIG4  0x0C060C06
-# define STNOR_GPMC_CONFIG5  0x01131F1F
-# define STNOR_GPMC_CONFIG6  0x0  /* 0? Not defined so far... this value is reset val as per gpmc doc */
-# define MPDB_GPMC_CONFIG1   0x00011000
-# define MPDB_GPMC_CONFIG2   0x001F1F00
-# define MPDB_GPMC_CONFIG3   0x00080802
-# define MPDB_GPMC_CONFIG4   0x1C091C09
-# define MPDB_GPMC_CONFIG5   0x031A1F1F
-# define MPDB_GPMC_CONFIG6   0x000003C2
-#endif
-
-#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */
-# define SMNAND_GPMC_CONFIG1 0x00001800
-# define SMNAND_GPMC_CONFIG2 0x00141400
-# define SMNAND_GPMC_CONFIG3 0x00141400
-# define SMNAND_GPMC_CONFIG4 0x0F010F01
-# define SMNAND_GPMC_CONFIG5 0x010C1414
-# define SMNAND_GPMC_CONFIG6 0x00000A80
-# define SMNAND_GPMC_CONFIG7 0x00000C44
-
-# define STNOR_GPMC_CONFIG1  0x3
-# define STNOR_GPMC_CONFIG2  0x00151501
-# define STNOR_GPMC_CONFIG3  0x00060602
-# define STNOR_GPMC_CONFIG4  0x10081008
-# define STNOR_GPMC_CONFIG5  0x01131F1F
-# define STNOR_GPMC_CONFIG6  0x000004c4
-
-# define MPDB_GPMC_CONFIG1  0x00011000
-# define MPDB_GPMC_CONFIG2  0x001f1f01
-# define MPDB_GPMC_CONFIG3  0x00080803
-# define MPDB_GPMC_CONFIG4  0x1C091C09
-# define MPDB_GPMC_CONFIG5  0x041f1F1F
-# define MPDB_GPMC_CONFIG6  0x000004C4
-
-# define SIBNOR_GPMC_CONFIG1  0x3
-# define SIBNOR_GPMC_CONFIG2  0x00151501
-# define SIBNOR_GPMC_CONFIG3  0x00060602
-# define SIBNOR_GPMC_CONFIG4  0x10081008
-# define SIBNOR_GPMC_CONFIG5  0x01131F1F
-# define SIBNOR_GPMC_CONFIG6  0x00000000
-
-# define ONENAND_GPMC_CONFIG1 0x00001200
-# define ONENAND_GPMC_CONFIG2 0x000c0c01
-# define ONENAND_GPMC_CONFIG3 0x00030301
-# define ONENAND_GPMC_CONFIG4 0x0c040c04
-# define ONENAND_GPMC_CONFIG5 0x010C1010
-# define ONENAND_GPMC_CONFIG6 0x00000000
-
-# define PCMCIA_GPMC_CONFIG1 0x01E91200
-# define PCMCIA_GPMC_CONFIG2 0x001E1E01
-# define PCMCIA_GPMC_CONFIG3 0x00020203
-# define PCMCIA_GPMC_CONFIG4 0x1D041D04
-# define PCMCIA_GPMC_CONFIG5 0x031D1F1F
-# define PCMCIA_GPMC_CONFIG6 0x000004C4
-#endif /* endif CFG_PRCM_III */
-
-#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */
-# define SMNAND_GPMC_CONFIG1 0x00001800
-# define SMNAND_GPMC_CONFIG2 0x00141400
-# define SMNAND_GPMC_CONFIG3 0x00141400
-# define SMNAND_GPMC_CONFIG4 0x0F010F01
-# define SMNAND_GPMC_CONFIG5 0x010C1414
-# define SMNAND_GPMC_CONFIG6 0x00000A80
-# define SMNAND_GPMC_CONFIG7 0x00000C44
-
-# define STNOR_GPMC_CONFIG1  0x3
-# define STNOR_GPMC_CONFIG2  0x00151501
-# define STNOR_GPMC_CONFIG3  0x00060602
-# define STNOR_GPMC_CONFIG4  0x11091109
-# define STNOR_GPMC_CONFIG5  0x01141F1F
-# define STNOR_GPMC_CONFIG6  0x000004c4
-
-# define MPDB_GPMC_CONFIG1  0x00011000
-# define MPDB_GPMC_CONFIG2  0x001f1f01
-# define MPDB_GPMC_CONFIG3  0x00080803
-# define MPDB_GPMC_CONFIG4  0x1c0b1c0a
-# define MPDB_GPMC_CONFIG5  0x041f1F1F
-# define MPDB_GPMC_CONFIG6  0x000004C4
-
-# define SIBNOR_GPMC_CONFIG1  0x3
-# define SIBNOR_GPMC_CONFIG2  0x00151501
-# define SIBNOR_GPMC_CONFIG3  0x00060602
-# define SIBNOR_GPMC_CONFIG4  0x11091109
-# define SIBNOR_GPMC_CONFIG5  0x01141F1F
-# define SIBNOR_GPMC_CONFIG6  0x00000000
-
-# define ONENAND_GPMC_CONFIG1 0x00001200
-# define ONENAND_GPMC_CONFIG2 0x000F0F01
-# define ONENAND_GPMC_CONFIG3 0x00030301
-# define ONENAND_GPMC_CONFIG4 0x0F040F04
-# define ONENAND_GPMC_CONFIG5 0x010F1010
-# define ONENAND_GPMC_CONFIG6 0x00000000
-
-# define PCMCIA_GPMC_CONFIG1 0x01E91200
-# define PCMCIA_GPMC_CONFIG2 0x001E1E01
-# define PCMCIA_GPMC_CONFIG3 0x00020203
-# define PCMCIA_GPMC_CONFIG4 0x1D041D04
-# define PCMCIA_GPMC_CONFIG5 0x031D1F1F
-# define PCMCIA_GPMC_CONFIG6 0x000004C4
-
-#endif
-
-#if 0
-/* Board Specific Settings for each of the configurations for chips
- * whose values change as per platform. - None currently
- */
-#if CONFIG_OMAP24XXH4
-#include <asm/arch/mem-h4.h>
-#endif
-
-#if CONFIG_2430SDP
-#include <asm/arch/mem-sdp2430.h>
-#endif
-
-#endif /* if 0 */
-
-/* max number of GPMC Chip Selects */
-#define GPMC_MAX_CS    8
-/* max number of GPMC regs */
-#define GPMC_MAX_REG   7
-
-#define PROC_NOR       1
-#define PROC_NAND      2
-#define PISMO_SIBLEY0  3
-#define PISMO_SIBLEY1  4
-#define PISMO_ONENAND  5
-#define DBG_MPDB       6
-#define PISMO_PCMCIA   7
-
-/* make it readable for the gpmc_init */
-#define PROC_NOR_BASE   	FLASH_BASE
-#define PROC_NAND_BASE  	NAND_BASE
-#define PISMO_SIB0_BASE 	SIBLEY_MAP1
-#define PISMO_SIB1_BASE 	SIBLEY_MAP2
-#define PISMO_ONEN_BASE 	ONENAND_MAP
-#define DBG_MPDB_BASE   	DEBUG_BASE
-#define PISMO_PCMCIA_BASE  	PCMCIA_BASE
-
-#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/include/asm/arch-arm1136/omap2420.h b/include/asm/arch-arm1136/omap2420.h
deleted file mode 100644
index 2164b68..0000000
--- a/include/asm/arch-arm1136/omap2420.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2005 Texas Instruments, <www.ti.com>
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2420_SYS_H_
-#define _OMAP2420_SYS_H_
-
-#include <asm/arch/sizes.h>
-
-
-#define __raw_writeb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __raw_writew(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a)		(*(volatile unsigned int *)(a) = (v))
-
-#define __raw_readb(a)			(*(volatile unsigned char *)(a))
-#define __raw_readw(a)			(*(volatile unsigned short *)(a))
-#define __raw_readl(a)			(*(volatile unsigned int *)(a)) 
-
-
-/*
- * 2420 specific Section
- */
-
-/* CONTROL */
-#define OMAP2420_CTRL_BASE    (0x48000000)
-#define CONTROL_STATUS        (OMAP2420_CTRL_BASE + 0x2F8)
-
-/* TAP information */
-#define OMAP2420_TAP_BASE     (0x48014000)
-#define TAP_IDCODE_REG        (OMAP2420_TAP_BASE+0x204)
-
-/* GPMC */
-#define OMAP2420_GPMC_BASE    (0x6800A000)
-#define GPMC_SYSCONFIG        (OMAP2420_GPMC_BASE+0x10)
-#define GPMC_SYSSTATUS	      (OMAP2420_GPMC_BASE+0x14)
-#define GPMC_IRQENABLE        (OMAP2420_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL  (OMAP2420_GPMC_BASE+0x40)
-#define GPMC_CONFIG           (OMAP2420_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0        (OMAP2420_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0        (OMAP2420_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0        (OMAP2420_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0        (OMAP2420_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0        (OMAP2420_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0        (OMAP2420_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0	      (OMAP2420_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1        (OMAP2420_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1        (OMAP2420_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1        (OMAP2420_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1        (OMAP2420_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1        (OMAP2420_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1        (OMAP2420_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1	      (OMAP2420_GPMC_BASE+0xA8)
-
-/* SMS */
-#define OMAP2420_SMS_BASE 0x68008000
-#define SMS_SYSCONFIG     (OMAP2420_SMS_BASE+0x10)
-
-/* SDRC */
-#define OMAP2420_SDRC_BASE 0x68009000
-#define SDRC_SYSCONFIG     (OMAP2420_SDRC_BASE+0x10)
-#define SDRC_STATUS        (OMAP2420_SDRC_BASE+0x14)
-#define SDRC_SHARING       (OMAP2420_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL     (OMAP2420_SDRC_BASE+0x60)
-#define SDRC_DLLA_STATUS   (OMAP2420_SDRC_BASE+0x64)
-#define SDRC_DLLB_CTRL     (OMAP2420_SDRC_BASE+0x68)
-#define SDRC_POWER         (OMAP2420_SDRC_BASE+0x70)
-#define SDRC_MCFG_0        (OMAP2420_SDRC_BASE+0x80)
-#define SDRC_MR_0          (OMAP2420_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
-#define SDRC_MCFG_1        (OMAP2420_SDRC_BASE+0xB0)
-#define SDRC_MR_1	   (OMAP2420_SDRC_BASE+0xB4)
-#define SDRC_EMR2_1	   (OMAP2420_SDRC_BASE+0xBC)
-#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL      (OMAP2420_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0      (OMAP2420_SDRC_BASE+0xA8)
-#define SDRC_RFR_CTRL1	   (OMAP2420_SDRC_BASE+0xD4)
-#define SDRC_MANUAL_1	   (OMAP2420_SDRC_BASE+0xD8)
-
-#define OMAP2420_SDRC_CS0  0x80000000
-#define OMAP2420_SDRC_CS1  0xA0000000
-
-#define LOADDLL            BIT2
-#define CMD_NOP            0x0
-#define CMD_PRECHARGE      0x1
-#define CMD_AUTOREFRESH    0x2
-#define CMD_ENTR_PWRDOWN   0x3
-#define CMD_EXIT_PWRDOWN   0x4
-#define CMD_ENTR_SRFRSH    0x5
-#define CMD_CKE_HIGH       0x6
-#define CMD_CKE_LOW        0x7
-#define SOFTRESET          BIT1
-#define SMART_IDLE         (0x2 << 3)
-#define REF_ON_IDLE        (0x1 << 6)
-
-
-/* UART */
-#define OMAP2420_UART1	      0x4806A000
-#define OMAP2420_UART2	      0x4806C000
-#define OMAP2420_UART3        0x4806E000
-
-/* General Purpose Timers */
-#define OMAP2420_GPT1         0x48028000
-#define OMAP2420_GPT2         0x4802A000
-#define OMAP2420_GPT3         0x48078000
-#define OMAP2420_GPT4         0x4807A000
-#define OMAP2420_GPT5         0x4807C000
-#define OMAP2420_GPT6         0x4807E000
-#define OMAP2420_GPT7         0x48080000
-#define OMAP2420_GPT8         0x48082000
-#define OMAP2420_GPT9         0x48084000
-#define OMAP2420_GPT10        0x48086000
-#define OMAP2420_GPT11        0x48088000
-#define OMAP2420_GPT12        0x4808A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR       0x0      /* r */
-#define TIOCP_CFG  0x10     /* rw */
-#define TISTAT     0x14     /* r */
-#define TISR       0x18     /* rw */
-#define TIER       0x1C     /* rw */
-#define TWER       0x20     /* rw */
-#define TCLR       0x24     /* rw */
-#define TCRR       0x28     /* rw */
-#define TLDR       0x2C     /* rw */
-#define TTGR       0x30     /* rw */
-#define TWPS       0x34     /* r */
-#define TMAR       0x38     /* rw */
-#define TCAR1      0x3c     /* r */
-#define TSICR      0x40     /* rw */
-#define TCAR2      0x44     /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE              0x48020000
-#define WD2_BASE              0x48022000
-#define WD3_BASE              0x48024000
-#define WD4_BASE              0x48026000
-#define WWPS       0x34     /* r */
-#define WSPR       0x48     /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP2420_CM_BASE 0x48008000
-#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
-#define CM_CLKSEL_MPU    (OMAP2420_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE  (OMAP2420_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE  (OMAP2420_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE  (OMAP2420_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE  (OMAP2420_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE  (OMAP2420_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP   (OMAP2420_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE  (OMAP2420_CM_BASE+0x244)
-#define CM_CLKSEL_GFX    (OMAP2420_CM_BASE+0x340)
-#define PM_RSTCTRL_WKUP  (OMAP2420_CM_BASE+0x450)
-#define CM_CLKEN_PLL     (OMAP2420_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN  (OMAP2420_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL   (OMAP2420_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL   (OMAP2420_CM_BASE+0x544)
-#define CM_CLKSEL_DSP    (OMAP2420_CM_BASE+0x840)
-
-/*
- * H4 specific Section
- */
-
-/*
- *  The 2420's chip selects are programmable.  The mask ROM
- *  does configure CS0 to 0x08000000 before dispatch.  So, if
- *  you want your code to live below that address, you have to
- *  be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP2420H4)
-/* GPMC */
-#ifdef CONFIG_VIRTIO_A        /* Pre version B */
-# define H4_CS0_BASE           0x08000000  /* flash (64 Meg aligned) */
-# define H4_CS1_BASE           0x04000000  /* debug board */
-# define H4_CS2_BASE           0x0A000000  /* wifi board */
-#else
-# define H4_CS0_BASE           0x04000000  /* flash (64 Meg aligned) */
-# define H4_CS1_BASE           0x08000000  /* debug board */
-# define H4_CS2_BASE           0x0A000000  /* wifi board */
-#endif
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0          0x40000000
-#define SRAM_OFFSET1          0x00200000
-#define SRAM_OFFSET2          0x0000F800
-#define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
-
-#define PERIFERAL_PORT_BASE   0x480FE003
-
-/* FPGA on Debug board.*/
-#define ETH_CONTROL_REG       (H4_CS1_BASE+0x30b)
-#define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
-#endif  /* endif CONFIG_2420H4 */
-
-#endif
-
diff --git a/include/asm/arch-arm1136/omap2430.h b/include/asm/arch-arm1136/omap2430.h
deleted file mode 100644
index cf2b0f9..0000000
--- a/include/asm/arch-arm1136/omap2430.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* 
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2430_SYS_H_
-#define _OMAP2430_SYS_H_
-
-#include <asm/arch/sizes.h>
-
-
-#define __raw_writeb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __raw_writew(v,a)		(*(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a)		(*(volatile unsigned int *)(a) = (v))
-
-#define __raw_readb(a)			(*(volatile unsigned char *)(a))
-#define __raw_readw(a)			(*(volatile unsigned short *)(a))
-#define __raw_readl(a)			(*(volatile unsigned int *)(a)) 
-
-/* device type */
-#define DEVICE_MASK          (BIT8|BIT9|BIT10)
-#define TST_DEVICE           0x0
-#define EMU_DEVICE           0x1
-#define HS_DEVICE            0x2
-#define GP_DEVICE            0x3
-
-/*
- * 2430 specific Section
- */
-#define OMAP243X_CORE_L4_IO_BASE        0x48000000
-#define OMAP243X_WAKEUP_L4_IO_BASE      0x49000000
-#define OMAP24XX_L4_IO_BASE     OMAP243X_CORE_L4_IO_BASE
-
-
-/* CONTROL */
-#define OMAP24XX_CTRL_BASE    (OMAP243X_WAKEUP_L4_IO_BASE+0x2000)
-#define CONTROL_STATUS        (OMAP24XX_CTRL_BASE + 0x2F8)
-
-/* TAP information */
-#define OMAP24XX_TAP_BASE     (OMAP243X_WAKEUP_L4_IO_BASE+0xA000)
-#define TAP_IDCODE_REG        (OMAP24XX_TAP_BASE+0x204)
-
-/* 
-	GPMC : In 2430 NOR and NAND can coexist.
-	During NAND booting , NAND is at CS0 and NOR at CS1
-	and Debug FPGA is GPMC_CS5 
-*/
-#define OMAP24XX_GPMC_BASE    (0x6E000000)
-
-#define GPMC_SYSCONFIG        (OMAP24XX_GPMC_BASE+0x10)
-#define GPMC_SYSSTATUS	      (OMAP24XX_GPMC_BASE+0x14)
-#define GPMC_IRQENABLE        (OMAP24XX_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL  (OMAP24XX_GPMC_BASE+0x40)
-#define GPMC_CONFIG           (OMAP24XX_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0        (OMAP24XX_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0        (OMAP24XX_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0        (OMAP24XX_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0        (OMAP24XX_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0        (OMAP24XX_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0        (OMAP24XX_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0	      (OMAP24XX_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1        (OMAP24XX_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1        (OMAP24XX_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1        (OMAP24XX_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1        (OMAP24XX_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1        (OMAP24XX_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1        (OMAP24XX_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1	      (OMAP24XX_GPMC_BASE+0xA8)
-#define GPMC_CONFIG1_5        (OMAP24XX_GPMC_BASE+0x150)
-#define GPMC_CONFIG2_5        (OMAP24XX_GPMC_BASE+0x154)
-#define GPMC_CONFIG3_5        (OMAP24XX_GPMC_BASE+0x158)
-#define GPMC_CONFIG4_5        (OMAP24XX_GPMC_BASE+0x15C)
-#define GPMC_CONFIG5_5        (OMAP24XX_GPMC_BASE+0x160)
-#define GPMC_CONFIG6_5        (OMAP24XX_GPMC_BASE+0x164)
-#define GPMC_CONFIG7_5        (OMAP24XX_GPMC_BASE+0x168)
-
-
-/* SMS */
-#define OMAP24XX_SMS_BASE 0x6C000000
-#define SMS_SYSCONFIG     (OMAP24XX_SMS_BASE+0x10)
-
-/* SDRC */
-#define OMAP24XX_SDRC_BASE 0x6D000000
-#define OMAP24XX_SDRC_CS0  0x80000000
-#define OMAP24XX_SDRC_CS1  0xA0000000
-#define SDRC_SYSCONFIG     (OMAP24XX_SDRC_BASE+0x10)
-#define SDRC_STATUS        (OMAP24XX_SDRC_BASE+0x14)
-#define SDRC_SHARING       (OMAP24XX_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL     (OMAP24XX_SDRC_BASE+0x60)
-#define SDRC_DLLA_STATUS   (OMAP24XX_SDRC_BASE+0x64)
-#define SDRC_DLLB_CTRL     (OMAP24XX_SDRC_BASE+0x68)
-#define SDRC_POWER         (OMAP24XX_SDRC_BASE+0x70)
-#define SDRC_MCFG_0        (OMAP24XX_SDRC_BASE+0x80)
-#define SDRC_MR_0          (OMAP24XX_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0)
-#define SDRC_MCFG_1        (OMAP24XX_SDRC_BASE+0xB0)
-#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL      (OMAP24XX_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0      (OMAP24XX_SDRC_BASE+0xA8)
-#define SDRC_RFR_CTRL1	   (OMAP24XX_SDRC_BASE+0xD4)
-
-#define LOADDLL            BIT2
-#define CMD_NOP            0x0
-#define CMD_PRECHARGE      0x1
-#define CMD_AUTOREFRESH    0x2
-#define CMD_ENTR_PWRDOWN   0x3
-#define CMD_EXIT_PWRDOWN   0x4
-#define CMD_ENTR_SRFRSH    0x5
-#define CMD_CKE_HIGH       0x6
-#define CMD_CKE_LOW        0x7
-#define SOFTRESET          BIT1
-#define SMART_IDLE         (0x2 << 3)
-#define REF_ON_IDLE        (0x1 << 6)
-
-
-/* UART */
-#define OMAP2430_UART1	      0x4806A000
-#define OMAP2430_UART2	      0x4806C000
-#define OMAP2430_UART3        0x4806E000
-
-/* General Purpose Timers */
-#define OMAP24XX_GPT1         (OMAP243X_WAKEUP_L4_IO_BASE+0x18000)
-#define OMAP24XX_GPT2         (OMAP24XX_L4_IO_BASE+0x2A000)
-#define OMAP24XX_GPT3         (OMAP24XX_L4_IO_BASE+0x78000)
-#define OMAP24XX_GPT4         (OMAP24XX_L4_IO_BASE+0x7A000)
-#define OMAP24XX_GPT5         (OMAP24XX_L4_IO_BASE+0x7C000)
-#define OMAP24XX_GPT6         (OMAP24XX_L4_IO_BASE+0x7E000)
-#define OMAP24XX_GPT7         (OMAP24XX_L4_IO_BASE+0x80000)
-#define OMAP24XX_GPT8         (OMAP24XX_L4_IO_BASE+0x82000)
-#define OMAP24XX_GPT9         (OMAP24XX_L4_IO_BASE+0x84000)
-#define OMAP24XX_GPT10        (OMAP24XX_L4_IO_BASE+0x86000)
-#define OMAP24XX_GPT11        (OMAP24XX_L4_IO_BASE+0x88000)
-#define OMAP24XX_GPT12        (OMAP24XX_L4_IO_BASE+0x8A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR       0x0      /* r */
-#define TIOCP_CFG  0x10     /* rw */
-#define TISTAT     0x14     /* r */
-#define TISR       0x18     /* rw */
-#define TIER       0x1C     /* rw */
-#define TWER       0x20     /* rw */
-#define TCLR       0x24     /* rw */
-#define TCRR       0x28     /* rw */
-#define TLDR       0x2C     /* rw */
-#define TTGR       0x30     /* rw */
-#define TWPS       0x34     /* r */
-#define TMAR       0x38     /* rw */
-#define TCAR1      0x3c     /* r */
-#define TSICR      0x40     /* rw */
-#define TCAR2      0x44     /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE              (OMAP243X_WAKEUP_L4_IO_BASE+0x14000)
-#define WD2_BASE              (OMAP243X_WAKEUP_L4_IO_BASE+0x16000)
-#define WD3_BASE              (OMAP24XX_L4_IO_BASE+0x24000) /* not present */
-#define WD4_BASE              (OMAP24XX_L4_IO_BASE+0x26000)
-
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE    (OMAP243X_WAKEUP_L4_IO_BASE+0x20000)
-#define S32K_CR               (SYNC_32KTIMER_BASE+0x10)
-
-#define WWPS       0x34     /* r */
-#define WSPR       0x48     /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000)
-
-#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060)
-#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070)
-#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078)
-#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080)
-#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084)
-#define CM_CLKSEL_MPU    (OMAP24XX_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE  (OMAP24XX_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE  (OMAP24XX_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE  (OMAP24XX_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE  (OMAP24XX_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE  (OMAP24XX_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP   (OMAP24XX_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE  (OMAP24XX_CM_BASE+0x244)
-#define CM_FCLKEN_GFX    (OMAP24XX_CM_BASE+0x300)
-#define CM_ICLKEN_GFX    (OMAP24XX_CM_BASE+0x310)
-#define CM_CLKSEL_GFX    (OMAP24XX_CM_BASE+0x340)
-#define RM_RSTCTRL_GFX    (OMAP24XX_CM_BASE+0x350)
-#define CM_FCLKEN_WKUP    (OMAP24XX_CM_BASE+0x400)
-#define CM_ICLKEN_WKUP    (OMAP24XX_CM_BASE+0x410)
-#define PM_RSTCTRL_WKUP  (OMAP24XX_CM_BASE+0x450)
-#define CM_CLKEN_PLL     (OMAP24XX_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN  (OMAP24XX_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL   (OMAP24XX_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL   (OMAP24XX_CM_BASE+0x544)
-#define CM_CLKSEL_DSP    (OMAP24XX_CM_BASE+0x840)
-#define CM_CLKSEL_MDM    (OMAP24XX_CM_BASE+0xC40)
-
-/* SMX-APE */
-#define SMX_APE_BASE 0x68000000
-#define PM_RT_APE_BASE_ADDR_ARM  (SMX_APE_BASE + 0x10000)
-#define PM_GPMC_BASE_ADDR_ARM    (SMX_APE_BASE + 0x12400)
-#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
-#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00)
-
-/* IVA2 */
-#define PM_IVA2_BASE_ADDR_ARM    (SMX_APE_BASE + 0x14000)
-
-/*
- *  The 2430's chip selects are programmable.  The mask ROM
- *  does configure CS0 to 0x08000000 before dispatch.  So, if
- *  you want your code to live below that address, you have to
- *  be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP243X)
-
-/* GPMC */
-/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */
-# define H4_CS1_BASE           0x09000000  /* flash (64 Meg aligned) */
-#define CFG_FLASH_BASE H4_CS1_BASE
-#define DEBUG_BASE	0x08000000
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0          0x40000000
-#define SRAM_OFFSET1          0x00200000
-#define SRAM_OFFSET2          0x0000F800
-#define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
-
-#define PERIFERAL_PORT_BASE   0x480FE003
-
-#endif  /* endif CONFIG_2430SDP */
-
-#endif
-
diff --git a/include/asm/arch-arm1136/sizes.h b/include/asm/arch-arm1136/sizes.h
deleted file mode 100644
index 3dddd8e..0000000
--- a/include/asm/arch-arm1136/sizes.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h			1
-
-/* handy sizes */
-#define SZ_1K				0x00000400
-#define SZ_4K				0x00001000
-#define SZ_8K				0x00002000
-#define SZ_16K				0x00004000
-#define SZ_32K				0x00008000
-#define SZ_64K				0x00010000
-#define SZ_128K				0x00020000
-#define SZ_256K				0x00040000
-#define SZ_512K				0x00080000
-
-#define SZ_1M				0x00100000
-#define SZ_2M				0x00200000
-#define SZ_4M				0x00400000
-#define SZ_8M				0x00800000
-#define SZ_16M				0x01000000
-#define SZ_31M				0x01F00000
-#define SZ_32M				0x02000000
-#define SZ_64M				0x04000000
-#define SZ_128M				0x08000000
-#define SZ_256M				0x10000000
-#define SZ_512M				0x20000000
-
-#define SZ_1G				0x40000000
-#define SZ_2G				0x80000000
-
-#endif	/* __sizes_h */
-
diff --git a/include/asm/arch-arm1136/sys_info.h b/include/asm/arch-arm1136/sys_info.h
deleted file mode 100644
index 94a09cd..0000000
--- a/include/asm/arch-arm1136/sys_info.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright 2005 (C) Texas Instruments, <www.ti.com>
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_SYS_INFO_H_
-#define _OMAP24XX_SYS_INFO_H_
-
-#if 0
-typedef struct  h4_system_data {
-	/* base board info */
-	u32 base_b_rev;		/* rev from base board i2c */
-	/* cpu board info */
-	u32 cpu_b_rev;		/* rev from cpu board i2c */
-	u32 cpu_b_mux;		/* mux type on daughter board */
-	u32 cpu_b_ddr_type;	/* mem type */
-	u32 cpu_b_ddr_speed;	/* ddr speed rating */
-	u32 cpu_b_switches;	/* boot ctrl switch settings */
-	/* cpu info */
-	u32 cpu_type;		/* type of cpu; 2420, 2422, 2430,...*/
-	u32 cpu_rev;		/* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#endif
-
-#define XDR_POP           5      /* package on package part */
-#define SDR_DISCRETE      4      /* 128M memory SDR module*/
-#define DDR_STACKED       3      /* stacked part on 2422 */
-#define DDR_COMBO         2      /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE      1      /* 2x16 parts on daughter card */
-
-#define DDR_100           100    /* type found on most mem d-boards */
-#define DDR_111           111    /* some combo parts */
-#define DDR_133           133    /* most combo, some mem d-boards */
-#define DDR_165           165    /* future parts */
-
-#define CPU_2420          0x2420
-#define CPU_2422          0x2422 /* 2420 + 64M stacked */
-#define CPU_2423          0x2423 /* 2420 + 96M stacked */
-#define CPU_2430          0x2430
-
-/* 242x real hardware:
- *  ES1     = rev 0
- *  ES2     = rev 1
- *  ES2.05  = rev 2
- *  ES2.1   = rev 3
- *  ES2.1.1 = rev 4
- */
-
-/* 242x code defines:
- * ES1     = 0+1 = 1
- * ES2     = 1+1 = 2
- * ES2.05  = 2+1 = 3
- * ES2.1   = 3+1 = 4
- * Es2.1.1 = 4+1 = 5
- */
-#define CPU_2422_ES1      1
-#define CPU_2422_ES2      2
-#define CPU_2422_ES2_05   3
-#define CPU_2422_ES2_1    4
-#define CPU_2422_ES2_1_1  5
-
-#define CPU_2420_ES1      1
-#define CPU_2420_ES2      2
-#define CPU_2420_ES2_05   3
-#define CPU_2420_ES2_1    4
-#define CPU_2420_ES2_1_1  5
-
-#define CPU_242X_ES1      1
-#define CPU_242X_ES2      2
-#define CPU_242X_ES2_05   3
-#define CPU_242X_ES2_1    4
-#define CPU_242X_ES2_1_1  5
-
-#define CPU_2420_2422_ES1 1
-#define CPU_2420_2422_ES2_1 4
-
-/* 243x real hardware:
- *  ES1     = rev 0
- *  ES2     = rev 1
- *
- * 243x code defines:
- * ES1     = 0+1 = 1
- * ES2     = 1+1 = 2
- */
-#define CPU_2430_ES1     1
-#define CPU_2430_ES2     2
-
-#ifdef VPOM2430
-# define CPU_2430_VIRTIO   3
-#else
-# define CPU_2430_VIRTIO   1
-#endif
-#define CPU_2430_ZEBU     0xD
-
-#define CPU_2420_CHIPID   0x0B5D9000
-#define CPU_2430_CHIPID   0x0B68A000
-#define CPU_24XX_ID_MASK  0x0FFFF000
-#define CPU_242X_REV_MASK 0xF0000000
-#define CPU_242X_PID_MASK 0x000F0000
-
-#define BOARD_H4_MENELAUS     1
-#define BOARD_H4_SDP          2
-#define BOARD_H4_MENELAUS_HRP 3
-#define BOARD_SDP_2430        4
-
-#define GPMC_MUXED        1
-#define GPMC_NONMUXED     0
-
-#define TYPE_NAND         0x800   /* bit pos for nand in gpmc reg */
-#define TYPE_NOR          0x000
-#define TYPE_ONENAND      0x800
-
-#define WIDTH_8BIT        0x0000
-#define WIDTH_16BIT       0x1000  /* bit pos for 16 bit in gpmc */
-
-#define I2C_MENELAUS 0x72	/* i2c id for companion chip */
-
-#endif