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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-02-07 22:46:43 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-03-05 15:13:05 -0800 |
| commit | 7b12381723021fd5fbcf761e6832dd16a14f52d4 (patch) | |
| tree | 49d420e937ca3f089dcf93677b53c0be393c7e37 /intel | |
| parent | 85ae22af0f209e73c954d8867d9189ab2cfeb3e1 (diff) | |
| download | libdrm-sun4i-7b12381723021fd5fbcf761e6832dd16a14f52d4.tar.gz libdrm-sun4i-7b12381723021fd5fbcf761e6832dd16a14f52d4.tar.bz2 libdrm-sun4i-7b12381723021fd5fbcf761e6832dd16a14f52d4.zip | |
intel/intel_chipset.h: Sync Cannonlake IDs.
Let's sync CNL ids with Spec and kernel.
Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
Add Cannonlake PCI IDs for another SKU.")' and
commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Diffstat (limited to 'intel')
| -rw-r--r-- | intel/intel_chipset.h | 52 |
1 files changed, 28 insertions, 24 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3818e71e..01d250e8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -241,16 +241,20 @@ #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 -#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 -#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A -#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 -#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A -#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 -#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 -#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 -#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 -#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 -#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 +#define PCI_CHIP_CANNONLAKE_0 0x5A51 +#define PCI_CHIP_CANNONLAKE_1 0x5A59 +#define PCI_CHIP_CANNONLAKE_2 0x5A41 +#define PCI_CHIP_CANNONLAKE_3 0x5A49 +#define PCI_CHIP_CANNONLAKE_4 0x5A52 +#define PCI_CHIP_CANNONLAKE_5 0x5A5A +#define PCI_CHIP_CANNONLAKE_6 0x5A42 +#define PCI_CHIP_CANNONLAKE_7 0x5A4A +#define PCI_CHIP_CANNONLAKE_8 0x5A50 +#define PCI_CHIP_CANNONLAKE_9 0x5A40 +#define PCI_CHIP_CANNONLAKE_10 0x5A54 +#define PCI_CHIP_CANNONLAKE_11 0x5A5C +#define PCI_CHIP_CANNONLAKE_12 0x5A44 +#define PCI_CHIP_CANNONLAKE_13 0x5A4C #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -515,20 +519,20 @@ IS_GEMINILAKE(devid) || \ IS_COFFEELAKE(devid)) -#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ - (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) - -#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) - -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ - IS_CNL_Y(devid)) +#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ + (devid) == PCI_CHIP_CANNONLAKE_1 || \ + (devid) == PCI_CHIP_CANNONLAKE_2 || \ + (devid) == PCI_CHIP_CANNONLAKE_3 || \ + (devid) == PCI_CHIP_CANNONLAKE_4 || \ + (devid) == PCI_CHIP_CANNONLAKE_5 || \ + (devid) == PCI_CHIP_CANNONLAKE_6 || \ + (devid) == PCI_CHIP_CANNONLAKE_7 || \ + (devid) == PCI_CHIP_CANNONLAKE_8 || \ + (devid) == PCI_CHIP_CANNONLAKE_9 || \ + (devid) == PCI_CHIP_CANNONLAKE_10 || \ + (devid) == PCI_CHIP_CANNONLAKE_11 || \ + (devid) == PCI_CHIP_CANNONLAKE_12 || \ + (devid) == PCI_CHIP_CANNONLAKE_13) #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) |