android_hardware_intel_common_omx-components/videocodec, branch stable/cm-13.0-ZNH2KB Unnamed repository; edit this file 'description' to name the repository. intel: omx: Unbreak SetConfigVideoBitrate 2016-01-13T23:08:26+00:00 Christopher R. Palmer crpalmer@gmail.com 2016-01-13T19:57:45+00:00 43ccd58c53e951e3a5ec283711266e5aa9a2ebcc Prior to this change the code used uninitialized memory to for the majority of the config. The commit message which added this code suggests that they might not have been using this function other than to pass a test suite? Either way, it can't be a bad change to get the old config as default values rather than using uninitialized memory when calling set config. Change-Id: I1ccec4a4f206f81af3127f442fdb8b0cfdcab1ad 
Prior to this change the code used uninitialized memory to for the
majority of the config.  The commit message which added this code
suggests that they might not have been using this function other
than to pass a test suite?

Either way, it can't be a bad change to get the old config as default
values rather than using uninitialized memory when calling set config.

Change-Id: I1ccec4a4f206f81af3127f442fdb8b0cfdcab1ad
intel: omx: Zenfone2 blobs cannot handle metadata mode 2016-01-13T23:06:18+00:00 Christopher R. Palmer crpalmer@gmail.com 2016-01-09T11:11:45+00:00 1338ce03fd97a876ce66fcf5670aa4a8a0f18654 Change-Id: I07dfb4511c8fdd4f80569cf24cb8847963982170 
Change-Id: I07dfb4511c8fdd4f80569cf24cb8847963982170
intel: omx: LP blob compatibility 2016-01-13T23:06:04+00:00 Christopher R. Palmer crpalmer@gmail.com 2015-12-27T15:16:44+00:00 eef0672a39e63cbd2dc252111b8d9b4a77779b58 Change-Id: Idd32704c8eb2eb3f78f619c6dace0fb124b0db82 
Change-Id: Idd32704c8eb2eb3f78f619c6dace0fb124b0db82
fix random SEGV issue which is caused by wild pointer in libmix 2015-11-10T01:00:57+00:00 mahongpe hongpeng.ma@intel.com 2015-11-05T16:44:27+00:00 a2f2b42ced7efa9231d05389d56268e857f906d9 When resolution changes, we should flush video video pipeline at first, then free surface buffers. Bug: 23160948 Change-Id: I84782d886d8a484c2131d0b3f529f82b9c6fd8c9 Signed-off-by: mahongpe <hongpeng.ma@intel.com> 
When resolution changes, we should flush video video pipeline at
first, then free surface buffers.

Bug: 23160948

Change-Id: I84782d886d8a484c2131d0b3f529f82b9c6fd8c9
Signed-off-by: mahongpe <hongpeng.ma@intel.com>
Enlarge the size of OMX Output Buffer for fixing CTS issues. 2015-08-06T04:43:46+00:00 hding3 haitao.ding@intel.com 2015-07-30T08:54:39+00:00 3aa46b0bcd69b855f775a8b1f928776ca0fb35f6 Bug: 22602467 fix 2 CTS issues: testOtherH264FlexMaxMax/testOtherH264FlexNearMaxMax Change-Id: Iab33ce40d506a7c7b1773913cc8a07cb02040fbf Signed-off-by: hding3 <haitao.ding@intel.com> 
Bug: 22602467

fix 2 CTS issues: testOtherH264FlexMaxMax/testOtherH264FlexNearMaxMax

Change-Id: Iab33ce40d506a7c7b1773913cc8a07cb02040fbf
Signed-off-by: hding3 <haitao.ding@intel.com>
align the yv12 stride to 128bit for vp9 hybrid 2015-07-17T19:54:02+00:00 Gu, Wangyi wangyi.gu@intel.com 2015-07-16T06:10:33+00:00 68942cfbb4d52185ea162f336a94d8bab263d366 Bug: 19197299 need align with gralloc change Change-Id: Ief1c2e960b0e2d3c8566bf32032e7050ed0a6e5c Signed-off-by: Gu, Wangyi <wangyi.gu@intel.com> 
Bug: 19197299

need align with gralloc change

Change-Id: Ief1c2e960b0e2d3c8566bf32032e7050ed0a6e5c
Signed-off-by: Gu, Wangyi <wangyi.gu@intel.com>
correctly set SW_USAGE for HW codecs 2015-07-16T04:55:05+00:00 Tianmi Chen tianmi.chen@intel.com 2015-07-10T00:38:07+00:00 baa033a1fcf511bd575c94cbd8a839c4c87a699e this is to explicitly declare the capability to allow apps to read/write the video buffer. gralloc module will manage the cache flushing better when usage flags align between alloc() and lock(). Bug: 22183821 Change-Id: I185b14a2f97598f68a1c278309ecbffaf6e5c113 Signed-off-by: Tianmi Chen <tianmi.chen@intel.com> 
this is to explicitly declare the capability to allow apps
to read/write the video buffer. gralloc module will manage
the cache flushing better when usage flags align between
alloc() and lock().

Bug: 22183821

Change-Id: I185b14a2f97598f68a1c278309ecbffaf6e5c113
Signed-off-by: Tianmi Chen <tianmi.chen@intel.com>
align the yv12 stride to 64bit for vp9 hybrid 2015-07-10T15:16:46+00:00 Gu, Wangyi wangyi.gu@intel.com 2015-07-07T04:32:24+00:00 d22539f0a4952ec4a631d603a6e737d98ea16ea0 Bug: 19197299 Change-Id: Iebe2487bb2b2f761b7412d6b802ff545961551b1 Signed-off-by: Gu, Wangyi <wangyi.gu@intel.com> 
Bug: 19197299

Change-Id: Iebe2487bb2b2f761b7412d6b802ff545961551b1
Signed-off-by: Gu, Wangyi <wangyi.gu@intel.com>
omx-component: fix video corruption 2015-07-10T15:16:07+00:00 Yuanjun Huang yuanjun.huang@intel.com 2015-07-07T20:02:47+00:00 4671addc0e10b5d30163630d6fd8eaf3a84b7779 a. if out port frame width parsed from extractor is not as same as parsed from SPS/PPS nalu decoding, align it to the result from decoder. b. when resolution changes in adaptive playback, make sure out port frame height is 32-align again so that graphic buffer is allocated as 32-align. BUG: 22184303 Change-Id: Id070b2d51fcda899e70b5b12fc9ec841bb9fd44a Signed-off-by: Yuanjun Huang <yuanjun.huang@intel.com> 
a. if out port frame width parsed from extractor is
not as same as parsed from SPS/PPS nalu decoding, align it to the
result from decoder.

b. when resolution changes in adaptive playback, make sure out port
frame height is 32-align again so that graphic buffer is allocated
as 32-align.

BUG: 22184303

Change-Id: Id070b2d51fcda899e70b5b12fc9ec841bb9fd44a
Signed-off-by: Yuanjun Huang <yuanjun.huang@intel.com>
Remove unused argument to suppress compilation error 2015-07-01T15:35:19+00:00 Tianmi Chen tianmi.chen@intel.com 2015-06-16T06:33:48+00:00 82563df6bcb3f2a982b6c28b38147edba5cde22c BUG: 21777583 Change-Id: I7f8ed7463bbf85418aa09a1f15a326e4a68f4a10 Signed-off-by: Tianmi Chen <tianmi.chen@intel.com> 
BUG: 21777583

Change-Id: I7f8ed7463bbf85418aa09a1f15a326e4a68f4a10
Signed-off-by: Tianmi Chen <tianmi.chen@intel.com>