From 5d4cdbf7a67d3662fa0bee4efdb7edd8daec9b0b Mon Sep 17 00:00:00 2001 From: Ben Murdoch Date: Wed, 11 Apr 2012 10:23:59 +0100 Subject: Merge V8 3.9 at 3.9.24.9 http://v8.googlecode.com/svn/branches/3.9@11260 Bug: 5688872 Change-Id: Iddd944e82189d92df3fc427dc5f0d3f1b2f0c6c8 --- src/arm/assembler-arm.cc | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) (limited to 'src/arm/assembler-arm.cc') diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc index 25922361..ec28da40 100644 --- a/src/arm/assembler-arm.cc +++ b/src/arm/assembler-arm.cc @@ -66,11 +66,13 @@ static uint64_t CpuFeaturesImpliedByCompiler() { #ifdef __arm__ // If the compiler is allowed to use VFP then we can use VFP too in our code - // generation even when generating snapshots. This won't work for cross - // compilation. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6. -#if defined(__VFP_FP__) && !defined(__SOFTFP__) + // generation even when generating snapshots. ARMv7 and hardware floating + // point support implies VFPv3, see ARM DDI 0406B, page A1-6. +#if defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(__VFP_FP__) \ + && !defined(__SOFTFP__) answer |= 1u << VFP3 | 1u << ARMv7; -#endif // defined(__VFP_FP__) && !defined(__SOFTFP__) +#endif // defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(__VFP_FP__) + // && !defined(__SOFTFP__) #endif // def __arm__ return answer; @@ -137,7 +139,6 @@ bool RelocInfo::IsCodedSpecially() { } - void RelocInfo::PatchCode(byte* instructions, int instruction_count) { // Patch the code at the current address with the supplied instructions. Instr* pc = reinterpret_cast(pc_); @@ -236,25 +237,27 @@ MemOperand::MemOperand(Register rn, Register rm, // add(sp, sp, 4) instruction (aka Pop()) const Instr kPopInstruction = - al | PostIndex | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12; + al | PostIndex | 4 | LeaveCC | I | kRegister_sp_Code * B16 | + kRegister_sp_Code * B12; // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) // register r is not encoded. const Instr kPushRegPattern = - al | B26 | 4 | NegPreIndex | sp.code() * B16; + al | B26 | 4 | NegPreIndex | kRegister_sp_Code * B16; // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) // register r is not encoded. const Instr kPopRegPattern = - al | B26 | L | 4 | PostIndex | sp.code() * B16; + al | B26 | L | 4 | PostIndex | kRegister_sp_Code * B16; // mov lr, pc -const Instr kMovLrPc = al | MOV | pc.code() | lr.code() * B12; +const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12; // ldr rd, [pc, #offset] const Instr kLdrPCMask = kCondMask | 15 * B24 | 7 * B20 | 15 * B16; -const Instr kLdrPCPattern = al | 5 * B24 | L | pc.code() * B16; +const Instr kLdrPCPattern = al | 5 * B24 | L | kRegister_pc_Code * B16; // blxcc rm const Instr kBlxRegMask = 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4; const Instr kBlxRegPattern = B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX; +const Instr kBlxIp = al | kBlxRegPattern | ip.code(); const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16; const Instr kMovMvnPattern = 0xd * B21; const Instr kMovMvnFlip = B22; @@ -271,13 +274,13 @@ const Instr kAndBicFlip = 0xe * B21; // A mask for the Rd register for push, pop, ldr, str instructions. const Instr kLdrRegFpOffsetPattern = - al | B26 | L | Offset | fp.code() * B16; + al | B26 | L | Offset | kRegister_fp_Code * B16; const Instr kStrRegFpOffsetPattern = - al | B26 | Offset | fp.code() * B16; + al | B26 | Offset | kRegister_fp_Code * B16; const Instr kLdrRegFpNegOffsetPattern = - al | B26 | L | NegOffset | fp.code() * B16; + al | B26 | L | NegOffset | kRegister_fp_Code * B16; const Instr kStrRegFpNegOffsetPattern = - al | B26 | NegOffset | fp.code() * B16; + al | B26 | NegOffset | kRegister_fp_Code * B16; const Instr kLdrStrInstrTypeMask = 0xffff0000; const Instr kLdrStrInstrArgumentMask = 0x0000ffff; const Instr kLdrStrOffsetMask = 0x00000fff; -- cgit v1.2.3