diff options
Diffstat (limited to 'src/arm/assembler-arm.cc')
-rw-r--r-- | src/arm/assembler-arm.cc | 244 |
1 files changed, 146 insertions, 98 deletions
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc index be34df9c..fd8e8b5d 100644 --- a/src/arm/assembler-arm.cc +++ b/src/arm/assembler-arm.cc @@ -32,7 +32,7 @@ // The original source code covered by the above license above has been // modified significantly by Google Inc. -// Copyright 2010 the V8 project authors. All rights reserved. +// Copyright 2011 the V8 project authors. All rights reserved. #include "v8.h" @@ -44,11 +44,12 @@ namespace v8 { namespace internal { -CpuFeatures::CpuFeatures() - : supported_(0), - enabled_(0), - found_by_runtime_probing_(0) { -} +#ifdef DEBUG +bool CpuFeatures::initialized_ = false; +#endif +unsigned CpuFeatures::supported_ = 0; +unsigned CpuFeatures::found_by_runtime_probing_ = 0; + #ifdef __arm__ static uint64_t CpuFeaturesImpliedByCompiler() { @@ -58,48 +59,52 @@ static uint64_t CpuFeaturesImpliedByCompiler() { #endif // def CAN_USE_ARMV7_INSTRUCTIONS // If the compiler is allowed to use VFP then we can use VFP too in our code // generation even when generating snapshots. This won't work for cross - // compilation. + // compilation. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6. #if defined(__VFP_FP__) && !defined(__SOFTFP__) - answer |= 1u << VFP3; + answer |= 1u << VFP3 | 1u << ARMv7; #endif // defined(__VFP_FP__) && !defined(__SOFTFP__) #ifdef CAN_USE_VFP_INSTRUCTIONS - answer |= 1u << VFP3; + answer |= 1u << VFP3 | 1u << ARMv7; #endif // def CAN_USE_VFP_INSTRUCTIONS return answer; } #endif // def __arm__ -void CpuFeatures::Probe(bool portable) { +void CpuFeatures::Probe() { + ASSERT(!initialized_); +#ifdef DEBUG + initialized_ = true; +#endif #ifndef __arm__ - // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is enabled. + // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is + // enabled. VFPv3 implies ARMv7, see ARM DDI 0406B, page A1-6. if (FLAG_enable_vfp3) { - supported_ |= 1u << VFP3; + supported_ |= 1u << VFP3 | 1u << ARMv7; } // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled if (FLAG_enable_armv7) { supported_ |= 1u << ARMv7; } #else // def __arm__ - if (portable && Serializer::enabled()) { + if (Serializer::enabled()) { supported_ |= OS::CpuFeaturesImpliedByPlatform(); supported_ |= CpuFeaturesImpliedByCompiler(); return; // No features if we might serialize. } if (OS::ArmCpuHasFeature(VFP3)) { - // This implementation also sets the VFP flags if - // runtime detection of VFP returns true. - supported_ |= 1u << VFP3; - found_by_runtime_probing_ |= 1u << VFP3; + // This implementation also sets the VFP flags if runtime + // detection of VFP returns true. VFPv3 implies ARMv7, see ARM DDI + // 0406B, page A1-6. + supported_ |= 1u << VFP3 | 1u << ARMv7; + found_by_runtime_probing_ |= 1u << VFP3 | 1u << ARMv7; } if (OS::ArmCpuHasFeature(ARMv7)) { supported_ |= 1u << ARMv7; found_by_runtime_probing_ |= 1u << ARMv7; } - - if (!portable) found_by_runtime_probing_ = 0; #endif } @@ -268,8 +273,8 @@ const Instr kLdrStrOffsetMask = 0x00000fff; static const int kMinimalBufferSize = 4*KB; -Assembler::Assembler(void* buffer, int buffer_size) - : AssemblerBase(Isolate::Current()), +Assembler::Assembler(Isolate* arg_isolate, void* buffer, int buffer_size) + : AssemblerBase(arg_isolate), positions_recorder_(this), allow_peephole_optimization_(false), emit_debug_code_(FLAG_debug_code) { @@ -715,7 +720,7 @@ static bool fits_shifter(uint32_t imm32, *instr ^= kMovMvnFlip; return true; } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) { - if (Isolate::Current()->cpu_features()->IsSupported(ARMv7)) { + if (CpuFeatures::IsSupported(ARMv7)) { if (imm32 < 0x10000) { *instr ^= kMovwLeaveCCFlip; *instr |= EncodeMovwImmediate(imm32); @@ -779,7 +784,7 @@ bool Operand::is_single_instruction(Instr instr) const { // condition code additional instruction conventions can be used. if ((instr & ~kCondMask) == 13*B21) { // mov, S not set if (must_use_constant_pool() || - !Isolate::Current()->cpu_features()->IsSupported(ARMv7)) { + !CpuFeatures::IsSupported(ARMv7)) { // mov instruction will be an ldr from constant pool (one instruction). return true; } else { @@ -822,7 +827,7 @@ void Assembler::addrmod1(Instr instr, Condition cond = Instruction::ConditionField(instr); if ((instr & ~kCondMask) == 13*B21) { // mov, S not set if (x.must_use_constant_pool() || - !isolate()->cpu_features()->IsSupported(ARMv7)) { + !CpuFeatures::IsSupported(ARMv7)) { RecordRelocInfo(x.rmode_, x.imm32_); ldr(rd, MemOperand(pc, 0), cond); } else { @@ -1265,7 +1270,7 @@ void Assembler::usat(Register dst, const Operand& src, Condition cond) { // v6 and above. - ASSERT(isolate()->cpu_features()->IsSupported(ARMv7)); + ASSERT(CpuFeatures::IsSupported(ARMv7)); ASSERT(!dst.is(pc) && !src.rm_.is(pc)); ASSERT((satpos >= 0) && (satpos <= 31)); ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL)); @@ -1293,7 +1298,7 @@ void Assembler::ubfx(Register dst, int width, Condition cond) { // v7 and above. - ASSERT(isolate()->cpu_features()->IsSupported(ARMv7)); + ASSERT(CpuFeatures::IsSupported(ARMv7)); ASSERT(!dst.is(pc) && !src.is(pc)); ASSERT((lsb >= 0) && (lsb <= 31)); ASSERT((width >= 1) && (width <= (32 - lsb))); @@ -1313,7 +1318,7 @@ void Assembler::sbfx(Register dst, int width, Condition cond) { // v7 and above. - ASSERT(isolate()->cpu_features()->IsSupported(ARMv7)); + ASSERT(CpuFeatures::IsSupported(ARMv7)); ASSERT(!dst.is(pc) && !src.is(pc)); ASSERT((lsb >= 0) && (lsb <= 31)); ASSERT((width >= 1) && (width <= (32 - lsb))); @@ -1328,7 +1333,7 @@ void Assembler::sbfx(Register dst, // bfc dst, #lsb, #width void Assembler::bfc(Register dst, int lsb, int width, Condition cond) { // v7 and above. - ASSERT(isolate()->cpu_features()->IsSupported(ARMv7)); + ASSERT(CpuFeatures::IsSupported(ARMv7)); ASSERT(!dst.is(pc)); ASSERT((lsb >= 0) && (lsb <= 31)); ASSERT((width >= 1) && (width <= (32 - lsb))); @@ -1347,7 +1352,7 @@ void Assembler::bfi(Register dst, int width, Condition cond) { // v7 and above. - ASSERT(isolate()->cpu_features()->IsSupported(ARMv7)); + ASSERT(CpuFeatures::IsSupported(ARMv7)); ASSERT(!dst.is(pc) && !src.is(pc)); ASSERT((lsb >= 0) && (lsb <= 31)); ASSERT((width >= 1) && (width <= (32 - lsb))); @@ -1619,7 +1624,7 @@ void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { void Assembler::ldrd(Register dst1, Register dst2, const MemOperand& src, Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(ARMv7)); + ASSERT(CpuFeatures::IsEnabled(ARMv7)); ASSERT(src.rm().is(no_reg)); ASSERT(!dst1.is(lr)); // r14. ASSERT_EQ(0, dst1.code() % 2); @@ -1634,7 +1639,7 @@ void Assembler::strd(Register src1, Register src2, ASSERT(!src1.is(lr)); // r14. ASSERT_EQ(0, src1.code() % 2); ASSERT_EQ(src1.code() + 1, src2.code()); - ASSERT(isolate()->cpu_features()->IsEnabled(ARMv7)); + ASSERT(CpuFeatures::IsEnabled(ARMv7)); addrmod3(cond | B7 | B6 | B5 | B4, src1, dst); } @@ -1821,45 +1826,6 @@ void Assembler::ldc2(Coprocessor coproc, } -void Assembler::stc(Coprocessor coproc, - CRegister crd, - const MemOperand& dst, - LFlag l, - Condition cond) { - addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst); -} - - -void Assembler::stc(Coprocessor coproc, - CRegister crd, - Register rn, - int option, - LFlag l, - Condition cond) { - // Unindexed addressing. - ASSERT(is_uint8(option)); - emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 | - coproc*B8 | (option & 255)); -} - - -void Assembler::stc2(Coprocessor - coproc, CRegister crd, - const MemOperand& dst, - LFlag l) { // v5 and above - stc(coproc, crd, dst, l, kSpecialCondition); -} - - -void Assembler::stc2(Coprocessor coproc, - CRegister crd, - Register rn, - int option, - LFlag l) { // v5 and above - stc(coproc, crd, rn, option, l, kSpecialCondition); -} - - // Support for VFP. void Assembler::vldr(const DwVfpRegister dst, @@ -1870,7 +1836,7 @@ void Assembler::vldr(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-628. // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | // Vdst(15-12) | 1011(11-8) | offset - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); int u = 1; if (offset < 0) { offset = -offset; @@ -1912,7 +1878,7 @@ void Assembler::vldr(const SwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-628. // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) | // Vdst(15-12) | 1010(11-8) | offset - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); int u = 1; if (offset < 0) { offset = -offset; @@ -1956,7 +1922,7 @@ void Assembler::vstr(const DwVfpRegister src, // Instruction details available in ARM DDI 0406A, A8-786. // cond(31-28) | 1101(27-24)| U000(23-20) | | Rbase(19-16) | // Vsrc(15-12) | 1011(11-8) | (offset/4) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); int u = 1; if (offset < 0) { offset = -offset; @@ -1997,7 +1963,7 @@ void Assembler::vstr(const SwVfpRegister src, // Instruction details available in ARM DDI 0406A, A8-786. // cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) | // Vdst(15-12) | 1010(11-8) | (offset/4) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); int u = 1; if (offset < 0) { offset = -offset; @@ -2032,6 +1998,88 @@ void Assembler::vstr(const SwVfpRegister src, } +void Assembler::vldm(BlockAddrMode am, + Register base, + DwVfpRegister first, + DwVfpRegister last, + Condition cond) { + // Instruction details available in ARM DDI 0406A, A8-626. + // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | + // first(15-12) | 1010(11-8) | (count * 2) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT_LE(first.code(), last.code()); + ASSERT(am == ia || am == ia_w || am == db_w); + ASSERT(!base.is(pc)); + + int sd, d; + first.split_code(&sd, &d); + int count = last.code() - first.code() + 1; + emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | + 0xB*B8 | count*2); +} + + +void Assembler::vstm(BlockAddrMode am, + Register base, + DwVfpRegister first, + DwVfpRegister last, + Condition cond) { + // Instruction details available in ARM DDI 0406A, A8-784. + // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | + // first(15-12) | 1011(11-8) | (count * 2) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT_LE(first.code(), last.code()); + ASSERT(am == ia || am == ia_w || am == db_w); + ASSERT(!base.is(pc)); + + int sd, d; + first.split_code(&sd, &d); + int count = last.code() - first.code() + 1; + emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | + 0xB*B8 | count*2); +} + +void Assembler::vldm(BlockAddrMode am, + Register base, + SwVfpRegister first, + SwVfpRegister last, + Condition cond) { + // Instruction details available in ARM DDI 0406A, A8-626. + // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) | + // first(15-12) | 1010(11-8) | (count/2) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT_LE(first.code(), last.code()); + ASSERT(am == ia || am == ia_w || am == db_w); + ASSERT(!base.is(pc)); + + int sd, d; + first.split_code(&sd, &d); + int count = last.code() - first.code() + 1; + emit(cond | B27 | B26 | am | d*B22 | B20 | base.code()*B16 | sd*B12 | + 0xA*B8 | count); +} + + +void Assembler::vstm(BlockAddrMode am, + Register base, + SwVfpRegister first, + SwVfpRegister last, + Condition cond) { + // Instruction details available in ARM DDI 0406A, A8-784. + // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) | + // first(15-12) | 1011(11-8) | (count/2) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT_LE(first.code(), last.code()); + ASSERT(am == ia || am == ia_w || am == db_w); + ASSERT(!base.is(pc)); + + int sd, d; + first.split_code(&sd, &d); + int count = last.code() - first.code() + 1; + emit(cond | B27 | B26 | am | d*B22 | base.code()*B16 | sd*B12 | + 0xA*B8 | count); +} + static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { uint64_t i; memcpy(&i, &d, 8); @@ -2043,7 +2091,7 @@ static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { // Only works for little endian floating point formats. // We don't support VFP on the mixed endian floating point platform. static bool FitsVMOVDoubleImmediate(double d, uint32_t *encoding) { - ASSERT(Isolate::Current()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); // VMOV can accept an immediate of the form: // @@ -2096,7 +2144,7 @@ void Assembler::vmov(const DwVfpRegister dst, const Condition cond) { // Dd = immediate // Instruction details available in ARM DDI 0406B, A8-640. - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); uint32_t enc; if (FitsVMOVDoubleImmediate(imm, &enc)) { @@ -2133,7 +2181,7 @@ void Assembler::vmov(const SwVfpRegister dst, const Condition cond) { // Sd = Sm // Instruction details available in ARM DDI 0406B, A8-642. - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); int sd, d, sm, m; dst.split_code(&sd, &d); src.split_code(&sm, &m); @@ -2146,7 +2194,7 @@ void Assembler::vmov(const DwVfpRegister dst, const Condition cond) { // Dd = Dm // Instruction details available in ARM DDI 0406B, A8-642. - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code()); } @@ -2160,7 +2208,7 @@ void Assembler::vmov(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-646. // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(!src1.is(pc) && !src2.is(pc)); emit(cond | 0xC*B24 | B22 | src2.code()*B16 | src1.code()*B12 | 0xB*B8 | B4 | dst.code()); @@ -2175,7 +2223,7 @@ void Assembler::vmov(const Register dst1, // Instruction details available in ARM DDI 0406A, A8-646. // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(!dst1.is(pc) && !dst2.is(pc)); emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 | dst1.code()*B12 | 0xB*B8 | B4 | src.code()); @@ -2189,7 +2237,7 @@ void Assembler::vmov(const SwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-642. // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(!src.is(pc)); int sn, n; dst.split_code(&sn, &n); @@ -2204,7 +2252,7 @@ void Assembler::vmov(const Register dst, // Instruction details available in ARM DDI 0406A, A8-642. // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(!dst.is(pc)); int sn, n; src.split_code(&sn, &n); @@ -2329,7 +2377,7 @@ void Assembler::vcvt_f64_s32(const DwVfpRegister dst, const SwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond)); } @@ -2338,7 +2386,7 @@ void Assembler::vcvt_f32_s32(const SwVfpRegister dst, const SwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond)); } @@ -2347,7 +2395,7 @@ void Assembler::vcvt_f64_u32(const DwVfpRegister dst, const SwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); } @@ -2356,7 +2404,7 @@ void Assembler::vcvt_s32_f64(const SwVfpRegister dst, const DwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); } @@ -2365,7 +2413,7 @@ void Assembler::vcvt_u32_f64(const SwVfpRegister dst, const DwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond)); } @@ -2374,7 +2422,7 @@ void Assembler::vcvt_f64_f32(const DwVfpRegister dst, const SwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond)); } @@ -2383,7 +2431,7 @@ void Assembler::vcvt_f32_f64(const SwVfpRegister dst, const DwVfpRegister src, VFPConversionMode mode, const Condition cond) { - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); } @@ -2413,7 +2461,7 @@ void Assembler::vadd(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-536. // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); } @@ -2428,7 +2476,7 @@ void Assembler::vsub(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-784. // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 | dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); } @@ -2443,7 +2491,7 @@ void Assembler::vmul(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-784. // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); } @@ -2458,7 +2506,7 @@ void Assembler::vdiv(const DwVfpRegister dst, // Instruction details available in ARM DDI 0406A, A8-584. // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | B23 | src1.code()*B16 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); } @@ -2471,7 +2519,7 @@ void Assembler::vcmp(const DwVfpRegister src1, // Instruction details available in ARM DDI 0406A, A8-570. // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | Vm(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); } @@ -2484,7 +2532,7 @@ void Assembler::vcmp(const DwVfpRegister src1, // Instruction details available in ARM DDI 0406A, A8-570. // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=0 | 1(6) | M(5)=? | 0(4) | 0000(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(src2 == 0.0); emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 | src1.code()*B12 | 0x5*B9 | B8 | B6); @@ -2495,7 +2543,7 @@ void Assembler::vmsr(Register dst, Condition cond) { // Instruction details available in ARM DDI 0406A, A8-652. // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | 0xE*B20 | B16 | dst.code()*B12 | 0xA*B8 | B4); } @@ -2505,7 +2553,7 @@ void Assembler::vmrs(Register dst, Condition cond) { // Instruction details available in ARM DDI 0406A, A8-652. // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | 0xF*B20 | B16 | dst.code()*B12 | 0xA*B8 | B4); } @@ -2516,7 +2564,7 @@ void Assembler::vsqrt(const DwVfpRegister dst, const Condition cond) { // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) | // Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0) - ASSERT(isolate()->cpu_features()->IsEnabled(VFP3)); + ASSERT(CpuFeatures::IsEnabled(VFP3)); emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 | dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code()); } |