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author | Leon Clarke <leonclarke@google.com> | 2010-01-27 15:57:47 +0000 |
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committer | Leon Clarke <leonclarke@google.com> | 2010-01-27 15:57:47 +0000 |
commit | 888f6729be6a6f6fbe246cb5a9f122e2dbe455b7 (patch) | |
tree | 16f9ce250ef5d36e49a0fb0018e979002ed5b4fb /src/arm/assembler-arm.cc | |
parent | 1471e9f5b6f291eea8447f441527cd2a85074a33 (diff) | |
download | android_external_v8-888f6729be6a6f6fbe246cb5a9f122e2dbe455b7.tar.gz android_external_v8-888f6729be6a6f6fbe246cb5a9f122e2dbe455b7.tar.bz2 android_external_v8-888f6729be6a6f6fbe246cb5a9f122e2dbe455b7.zip |
Pull from svn bleeding_edge@3716
Diffstat (limited to 'src/arm/assembler-arm.cc')
-rw-r--r-- | src/arm/assembler-arm.cc | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc index 07da8009..74547be6 100644 --- a/src/arm/assembler-arm.cc +++ b/src/arm/assembler-arm.cc @@ -30,9 +30,9 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED // OF THE POSSIBILITY OF SUCH DAMAGE. -// The original source code covered by the above license above has been modified -// significantly by Google Inc. -// Copyright 2006-2008 the V8 project authors. All rights reserved. +// The original source code covered by the above license above has been +// modified significantly by Google Inc. +// Copyright 2010 the V8 project authors. All rights reserved. #include "v8.h" @@ -1371,6 +1371,36 @@ void Assembler::stc2(Coprocessor coproc, // Support for VFP. +void Assembler::vldr(const DwVfpRegister dst, + const Register base, + int offset, + const Condition cond) { + // Ddst = MEM(Rbase + offset). + // Instruction details available in ARM DDI 0406A, A8-628. + // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) | + // Vdst(15-12) | 1011(11-8) | offset + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT(offset % 4 == 0); + emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 | + 0xB*B8 | ((offset / 4) & 255)); +} + + +void Assembler::vstr(const DwVfpRegister src, + const Register base, + int offset, + const Condition cond) { + // MEM(Rbase + offset) = Dsrc. + // Instruction details available in ARM DDI 0406A, A8-786. + // cond(31-28) | 1101(27-24)| 1000(23-20) | | Rbase(19-16) | + // Vsrc(15-12) | 1011(11-8) | (offset/4) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT(offset % 4 == 0); + emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | + 0xB*B8 | ((offset / 4) & 255)); +} + + void Assembler::vmov(const DwVfpRegister dst, const Register src1, const Register src2, |