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author | Iain Merrick <husky@google.com> | 2010-08-19 15:07:18 +0100 |
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committer | Iain Merrick <husky@google.com> | 2010-08-23 14:25:34 +0100 |
commit | 756813857a4c2a4d8ad2e805969d5768d3cf43a0 (patch) | |
tree | 002fad3c25654870c9634232d53a48219346c50b /src/arm/assembler-arm.cc | |
parent | bb769b257e753aafcbd96767abb2abc645eaa20c (diff) | |
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Update V8 to r5295 as required by WebKit r65615
Change-Id: I1d72d4990703e88b7798919c7a53e12ebf76958a
Diffstat (limited to 'src/arm/assembler-arm.cc')
-rw-r--r-- | src/arm/assembler-arm.cc | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc index b1705df9..6df6411d 100644 --- a/src/arm/assembler-arm.cc +++ b/src/arm/assembler-arm.cc @@ -1820,6 +1820,7 @@ void Assembler::vldr(const DwVfpRegister dst, ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(offset % 4 == 0); ASSERT((offset / 4) < 256); + ASSERT(offset >= 0); emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 | 0xB*B8 | ((offset / 4) & 255)); } @@ -1836,6 +1837,7 @@ void Assembler::vldr(const SwVfpRegister dst, ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(offset % 4 == 0); ASSERT((offset / 4) < 256); + ASSERT(offset >= 0); emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 | 0xA*B8 | ((offset / 4) & 255)); } @@ -1852,11 +1854,29 @@ void Assembler::vstr(const DwVfpRegister src, ASSERT(CpuFeatures::IsEnabled(VFP3)); ASSERT(offset % 4 == 0); ASSERT((offset / 4) < 256); + ASSERT(offset >= 0); emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | 0xB*B8 | ((offset / 4) & 255)); } +void Assembler::vstr(const SwVfpRegister src, + const Register base, + int offset, + const Condition cond) { + // MEM(Rbase + offset) = SSrc. + // Instruction details available in ARM DDI 0406A, A8-786. + // cond(31-28) | 1101(27-24)| 1000(23-20) | Rbase(19-16) | + // Vdst(15-12) | 1010(11-8) | (offset/4) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT(offset % 4 == 0); + ASSERT((offset / 4) < 256); + ASSERT(offset >= 0); + emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | + 0xA*B8 | ((offset / 4) & 255)); +} + + static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { uint64_t i; memcpy(&i, &d, 8); @@ -2276,6 +2296,21 @@ void Assembler::vcmp(const DwVfpRegister src1, } +void Assembler::vcmp(const DwVfpRegister src1, + const double src2, + const SBit s, + const Condition cond) { + // vcmp(Dd, Dm) double precision floating point comparison. + // Instruction details available in ARM DDI 0406A, A8-570. + // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) | + // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | 0000(3-0) + ASSERT(CpuFeatures::IsEnabled(VFP3)); + ASSERT(src2 == 0.0); + emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 | + src1.code()*B12 | 0x5*B9 | B8 | B6); +} + + void Assembler::vmrs(Register dst, Condition cond) { // Instruction details available in ARM DDI 0406A, A8-652. // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | |