1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
|
///*****************************************************************************
//*
//* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
//*
//* Licensed under the Apache License, Version 2.0 (the "License");
//* you may not use this file except in compliance with the License.
//* You may obtain a copy of the License at:
//*
//* http://www.apache.org/licenses/LICENSE-2.0
//*
//* Unless required by applicable law or agreed to in writing, software
//* distributed under the License is distributed on an "AS IS" BASIS,
//* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//* See the License for the specific language governing permissions and
//* limitations under the License.
//*
//*****************************************************************************/
///**
//*******************************************************************************
//* @file
//* ihevc_intra_pred_filters_planar.s
//*
//* @brief
//* contains function definitions for inter prediction interpolation.
//* functions are coded using neon intrinsics and can be compiled using
//* rvct
//*
//* @author
//* akshaya mukund
//*
//* @par list of functions:
//*
//*
//* @remarks
//* none
//*
//*******************************************************************************
//*/
///**
//*******************************************************************************
//*
//* @brief
//* luma intraprediction filter for planar input
//*
//* @par description:
//*
//* @param[in] pu1_ref
//* uword8 pointer to the source
//*
//* @param[out] pu1_dst
//* uword8 pointer to the destination
//*
//* @param[in] src_strd
//* integer source stride
//*
//* @param[in] dst_strd
//* integer destination stride
//*
//* @param[in] pi1_coeff
//* word8 pointer to the planar coefficients
//*
//* @param[in] nt
//* size of tranform block
//*
//* @param[in] mode
//* type of filtering
//*
//* @returns
//*
//* @remarks
//* none
//*
//*******************************************************************************
//*/
//void ihevc_intra_pred_luma_planar(uword8* pu1_ref,
// word32 src_strd,
// uword8* pu1_dst,
// word32 dst_strd,
// word32 nt,
// word32 mode,
// word32 pi1_coeff)
//**************variables vs registers*****************************************
//x0 => *pu1_ref
//x1 => src_strd
//x2 => *pu1_dst
//x3 => dst_strd
//stack contents from #40
// nt
// mode
// pi1_coeff
.text
.align 4
.include "ihevc_neon_macros.s"
.globl ihevc_intra_pred_chroma_planar_av8
.extern gau1_ihevc_planar_factor
.type ihevc_intra_pred_chroma_planar_av8, %function
ihevc_intra_pred_chroma_planar_av8:
// stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
push_v_regs
stp x19, x20,[sp,#-16]!
adrp x11, :got:gau1_ihevc_planar_factor //loads table of coeffs
ldr x11, [x11, #:got_lo12:gau1_ihevc_planar_factor]
clz w5,w4
sub x20, x5, #32
neg x5, x20
dup v14.8h,w5
neg v14.8h, v14.8h //shr value (so vneg)
dup v2.8b,w4 //nt
dup v16.8h,w4 //nt
sub x6, x4, #1 //nt-1
add x6, x0,x6,lsl #1 //2*(nt-1)
ldr w7, [x6]
sxtw x7,w7
dup v0.4h,w7 //src[nt-1]
add x6, x4, x4,lsl #1 //3nt
add x6, x6, #1 //3nt + 1
lsl x6,x6,#1 //2*(3nt + 1)
add x6, x6, x0
ldr w7, [x6]
sxtw x7,w7
dup v1.4h,w7 //src[3nt+1]
add x6, x4, x4 //2nt
add x14, x6, #1 //2nt+1
lsl x14,x14,#1 //2*(2nt+1)
sub x6, x6, #1 //2nt-1
lsl x6,x6,#1 //2*(2nt-1)
add x6, x6, x0 //&src[2nt-1]
add x14, x14, x0 //&src[2nt+1]
mov x8, #1 //row+1 (row is first 0)
sub x9, x4, x8 //nt-1-row (row is first 0)
dup v5.8b,w8 //row + 1
dup v6.8b,w9 //nt - 1 - row
mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
add x12, x11, #1 //coeffs (to be reloaded after every row)
mov x1, x4 //nt (row counter) (dec after every row)
mov x5, x2 //dst (to be reloaded after every row and inc by dst_strd)
mov x10, #8 //increment for the coeffs
mov x0, x14 //&src[2nt+1] (to be reloaded after every row)
cmp x4, #4
beq tf_sz_4
mov x10,x6
tf_sz_8_16:
ld1 {v10.8b, v11.8b}, [x14],#16 //load src[2nt+1+col]
ld1 {v8.8b},[x12],#8
mov v9.8b, v8.8b
zip1 v29.8b, v8.8b, v9.8b
zip2 v9.8b, v8.8b, v9.8b
mov v8.d[0], v29.d[0]
sub v30.8b, v2.8b , v8.8b //[nt-1-col]
sub v31.8b, v2.8b , v9.8b
loop_sz_8_16:
ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
sxtw x7,w7
umull v12.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
ldr w11, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
sxtw x11,w11
umlal v12.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
dup v4.4h,w7 //src[2nt-1-row]
umlal v12.8h, v8.8b, v1.8b //(col+1) * src[3nt+1]
dup v3.4h,w11 //src[2nt-1-row]
umlal v12.8h, v30.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
umull v28.8h, v5.8b, v0.8b
ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
sxtw x7,w7
umlal v28.8h, v6.8b, v11.8b
add v18.8b, v5.8b , v7.8b //row++ [(row+1)++]c
umlal v28.8h, v31.8b, v4.8b
sub v19.8b, v6.8b , v7.8b //[nt-1-row]--
umlal v28.8h, v9.8b, v1.8b
dup v4.4h,w7 //src[2nt-1-row]
umull v26.8h, v18.8b, v0.8b //(row+1) * src[nt-1]
add v12.8h, v12.8h , v16.8h //add (nt)
umlal v26.8h, v19.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
sshl v12.8h, v12.8h, v14.8h //shr
umlal v26.8h, v8.8b, v1.8b //(col+1) * src[3nt+1]
add v28.8h, v28.8h , v16.8h
umlal v26.8h, v30.8b, v3.8b //(nt-1-col) * src[2nt-1-row]
sshl v28.8h, v28.8h, v14.8h
umull v24.8h, v18.8b, v0.8b
add v5.8b, v18.8b , v7.8b //row++ [(row+1)++]
umlal v24.8h, v19.8b, v11.8b
sub v6.8b, v19.8b , v7.8b //[nt-1-row]--
umlal v24.8h, v9.8b, v1.8b
xtn v12.8b, v12.8h
umlal v24.8h, v31.8b, v3.8b
xtn v13.8b, v28.8h
add v26.8h, v26.8h , v16.8h //add (nt)
umull v22.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
sshl v26.8h, v26.8h, v14.8h //shr
umlal v22.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
st1 {v12.2s, v13.2s}, [x2], x3
umlal v22.8h, v8.8b, v1.8b //(col+1) * src[3nt+1]
add v24.8h, v24.8h , v16.8h
umlal v22.8h, v30.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
sshl v24.8h, v24.8h, v14.8h
umull v20.8h, v5.8b, v0.8b
add v18.8b, v5.8b , v7.8b //row++ [(row+1)++]c
umlal v20.8h, v6.8b, v11.8b
sub v19.8b, v6.8b , v7.8b //[nt-1-row]--
umlal v20.8h, v31.8b, v4.8b
ldr w11, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
sxtw x11,w11
umlal v20.8h, v9.8b, v1.8b
dup v3.4h,w11 //src[2nt-1-row]
add v22.8h, v22.8h , v16.8h //add (nt)
umull v12.8h, v18.8b, v0.8b //(row+1) * src[nt-1]
xtn v26.8b, v26.8h
umlal v12.8h, v19.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
xtn v27.8b, v24.8h
umlal v12.8h, v8.8b, v1.8b //(col+1) * src[3nt+1]
sshl v22.8h, v22.8h, v14.8h //shr
umlal v12.8h, v30.8b, v3.8b //(nt-1-col) * src[2nt-1-row]
add v20.8h, v20.8h , v16.8h
umull v28.8h, v18.8b, v0.8b
st1 {v26.2s, v27.2s}, [x2], x3
umlal v28.8h, v19.8b, v11.8b
add v5.8b, v18.8b , v7.8b //row++ [(row+1)++]
sub v6.8b, v19.8b , v7.8b //[nt-1-row]--
umlal v28.8h, v9.8b, v1.8b
umlal v28.8h, v31.8b, v3.8b
sshl v20.8h, v20.8h, v14.8h
add v12.8h, v12.8h , v16.8h //add (nt)
xtn v22.8b, v22.8h
add v28.8h, v28.8h , v16.8h
xtn v23.8b, v20.8h
sshl v12.8h, v12.8h, v14.8h //shr
st1 {v22.2s, v23.2s}, [x2], x3
sshl v28.8h, v28.8h, v14.8h
xtn v20.8b, v12.8h
xtn v21.8b, v28.8h
st1 {v20.2s, v21.2s}, [x2], x3
subs x1, x1, #4
bne loop_sz_8_16
cmp x4,#16
bne end_loop
sub x4, x4,#16
dup v5.8b,w8 //row + 1
dup v6.8b,w9 //nt - 1 - row
mov v7.8b, v5.8b //mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
mov x6,x10
mov x1,#16
sub x2,x2,x3,lsl #4
add x2,x2,#16
ld1 {v10.8b, v11.8b}, [x14],#16 //load src[2nt+1+col]
ld1 {v8.8b},[x12],#8
mov v9.8b, v8.8b
zip1 v29.8b, v8.8b, v9.8b
zip2 v9.8b, v8.8b, v9.8b
mov v8.d[0], v29.d[0]
sub v30.8b, v2.8b , v8.8b //[nt-1-col]
sub v31.8b, v2.8b , v9.8b
beq loop_sz_8_16
tf_sz_4:
ld1 {v10.8b},[x14] //load src[2nt+1+col]
ld1 {v8.8b},[x12], x10 //load 8 coeffs [col+1]
mov v9.8b, v8.8b
zip1 v29.8b, v8.8b, v9.8b
zip2 v9.8b, v8.8b, v9.8b
mov v8.d[0], v29.d[0]
loop_sz_4:
//mov x10, #4 @reduce inc to #4 for 4x4
ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row)
sxtw x7,w7
dup v4.4h,w7 //src[2nt-1-row]
sub v9.8b, v2.8b , v8.8b //[nt-1-col]
umull v12.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
umlal v12.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
umlal v12.8h, v8.8b, v1.8b //(col+1) * src[3nt+1]
umlal v12.8h, v9.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
// vadd.i16 q6, q6, q8 @add (nt)
// vshl.s16 q6, q6, q7 @shr
// vmovn.i16 d12, q6
rshrn v12.8b, v12.8h,#3
st1 {v12.2s},[x2], x3
add v5.8b, v5.8b , v7.8b //row++ [(row+1)++]
sub v6.8b, v6.8b , v7.8b //[nt-1-row]--
subs x1, x1, #1
bne loop_sz_4
end_loop:
// ldmfd sp!,{x4-x12,x15} //reload the registers from sp
ldp x19, x20,[sp],#16
pop_v_regs
ret
|
