From 7497191460a9504f8b4f64df169ab633f0b74353 Mon Sep 17 00:00:00 2001 From: Harish Mahendrakar Date: Mon, 20 Apr 2015 15:33:05 +0530 Subject: Resolved warnings and fixed alignment of few assemblies Resolved warnings seen in x86 modules Fixed alignment of few modules Updated comments in few arm modules for consistency Fixed warnings seen in clang build Change-Id: I0623169b5e84a6a6f09c3d2212e754101272f5e9 --- common/arm/ih264_inter_pred_luma_vert_qpel_a9q.s | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'common/arm/ih264_inter_pred_luma_vert_qpel_a9q.s') diff --git a/common/arm/ih264_inter_pred_luma_vert_qpel_a9q.s b/common/arm/ih264_inter_pred_luma_vert_qpel_a9q.s index d45055e..e2c68ef 100644 --- a/common/arm/ih264_inter_pred_luma_vert_qpel_a9q.s +++ b/common/arm/ih264_inter_pred_luma_vert_qpel_a9q.s @@ -17,7 +17,7 @@ @ ***************************************************************************** @ * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore @*/ -@/** +@** @****************************************************************************** @* @file @* ih264_inter_pred_luma_vert_qpel_a9q.s @@ -36,13 +36,11 @@ @* None @* @******************************************************************************* -@*/ +@* -@/* All the functions here are replicated from ih264_inter_pred_filters.c +@* All the functions here are replicated from ih264_inter_pred_filters.c @ -@/** -@/** @******************************************************************************* @* @* @brief @@ -79,7 +77,7 @@ @* None @* @******************************************************************************* -@*/ +@* @void ih264_inter_pred_luma_vert ( @ UWORD8 *pu1_src, @@ -211,12 +209,12 @@ loop_16: @when wd=16 subne r0, r0, r2 beq end_func @ Branch if height==4 - b loop_16 @ looping if height = 8 or 16 + b loop_16 @ looping if height = 8 or 16 loop_8: - @// Processing row0 and row1 + @ Processing row0 and row1 vld1.u32 d0, [r0], r2 @ Vector load from src[0_0] vld1.u32 d1, [r0], r2 @ Vector load from src[1_0] vld1.u32 d2, [r0], r2 @ Vector load from src[2_0] @@ -270,7 +268,7 @@ loop_8: b loop_8 @looping if height == 8 or 16 loop_4: -@// Processing row0 and row1 +@ Processing row0 and row1 vld1.u32 d0[0], [r0], r2 @ Vector load from src[0_0] vld1.u32 d1[0], [r0], r2 @ Vector load from src[1_0] -- cgit v1.2.3