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| author | Martin Storsjo <martin@martin.st> | 2015-06-10 12:05:14 +0300 |
|---|---|---|
| committer | Marco Nelissen <marcone@google.com> | 2015-06-25 08:25:46 -0700 |
| commit | 9f81a0a2024d1aa640e15085717a8164f770eba4 (patch) | |
| tree | 4095089abfaace92958b0013b636f09cfbae3374 /common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s | |
| parent | 436fccb1641f9f25afff6cf20f9d4957c08f43cd (diff) | |
| download | android_external_libavc-9f81a0a2024d1aa640e15085717a8164f770eba4.tar.gz android_external_libavc-9f81a0a2024d1aa640e15085717a8164f770eba4.tar.bz2 android_external_libavc-9f81a0a2024d1aa640e15085717a8164f770eba4.zip | |
armv8: Remove redundant NEON element size declarations
When specifying one specific lane of the vector, the number of
lanes don't need to be specified.
The clang built-in assembler doesn't allow the redundant
declarations, while binutils gas work fine with both forms.
Change-Id: I86077ce0774d4594a1295b6860e4944df87dde2f
Diffstat (limited to 'common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s')
| -rw-r--r-- | common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s b/common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s index b1e4866..3f3e297 100644 --- a/common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s +++ b/common/armv8/ih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s @@ -209,7 +209,7 @@ loop_16: uqxtn v18.8b, v18.8h uqxtn v19.8b, v19.8h - mov v18.2s[1], v19.2s[0] + mov v18.s[1], v19.s[0] ext v24.16b, v20.16b , v22.16b , #4 ext v26.16b, v20.16b , v22.16b , #6 @@ -238,7 +238,7 @@ loop_16: uqxtn v19.8b, v19.8h uqxtn v18.8b, v18.8h - mov v19.2s[1], v18.2s[0] + mov v19.s[1], v18.s[0] ld1 {v18.2s}, [x1] sqrshrun v20.8b, v20.8h, #5 @@ -297,7 +297,7 @@ loop_16: uqxtn v18.8b, v18.8h uqxtn v19.8b, v19.8h - mov v18.2s[1], v19.2s[0] + mov v18.s[1], v19.s[0] ext v24.16b, v20.16b , v22.16b , #4 ext v26.16b, v20.16b , v22.16b , #6 @@ -323,7 +323,7 @@ loop_16: ld1 {v22.4s}, [x6], x7 uqxtn v19.8b, v19.8h uqxtn v18.8b, v18.8h - mov v19.2s[1], v18.2s[0] + mov v19.s[1], v18.s[0] ld1 {v18.4s}, [x1] sqrshrun v20.8b, v20.8h, #5 sqrshrun v21.8b, v22.8h, #5 @@ -380,7 +380,7 @@ loop_16: uqxtn v18.8b, v18.8h uqxtn v19.8b, v19.8h - mov v18.2s[1], v19.2s[0] + mov v18.s[1], v19.s[0] ext v24.16b, v20.16b , v22.16b , #4 @@ -409,7 +409,7 @@ loop_16: uqxtn v19.8b, v19.8h uqxtn v18.8b, v18.8h - mov v19.2s[1], v18.2s[0] + mov v19.s[1], v18.s[0] ld1 {v18.2s}, [x1] sqrshrun v20.8b, v20.8h, #5 @@ -466,7 +466,7 @@ loop_16: ld1 {v22.4s}, [x9], #16 uqxtn v18.8b, v18.8h uqxtn v19.8b, v19.8h - mov v18.2s[1], v19.2s[0] + mov v18.s[1], v19.s[0] ext v24.16b, v20.16b , v22.16b , #4 @@ -506,7 +506,7 @@ loop_16: uqxtn v19.8b, v19.8h uqxtn v18.8b, v18.8h - mov v19.2s[1], v18.2s[0] + mov v19.s[1], v18.s[0] ld1 {v20.4s}, [x6], #16 ld1 {v22.4s}, [x6], x7 @@ -586,7 +586,7 @@ loop_8: ld1 {v2.2s, v3.2s}, [x0], x2 // Vector load from src[7_0] uqxtn v25.8b, v12.8h uqxtn v13.8b, v13.8h - mov v25.2s[1], v13.2s[0] + mov v25.s[1], v13.s[0] uaddl v16.8h, v8.8b, v10.8b @@ -620,7 +620,7 @@ loop_8: uaddl v28.8h, v9.8b, v11.8b uqxtn v13.8b, v16.8h uqxtn v17.8b, v17.8h - mov v13.2s[1], v17.2s[0] + mov v13.s[1], v17.s[0] urhadd v12.16b, v12.16b , v14.16b urhadd v13.16b, v13.16b , v15.16b @@ -662,7 +662,7 @@ loop_8: mls v16.8h, v30.8h , v24.8h uqxtn v27.8b, v12.8h uqxtn v13.8b, v13.8h - mov v27.2s[1], v13.2s[0] + mov v27.s[1], v13.s[0] sqrshrun v14.8b, v14.8h, #5 ext v22.16b, v28.16b , v16.16b , #10 @@ -702,7 +702,7 @@ loop_8: subs x4, x4, #4 uqxtn v13.8b, v16.8h uqxtn v17.8b, v17.8h - mov v13.2s[1], v17.2s[0] + mov v13.s[1], v17.s[0] urhadd v12.16b, v12.16b , v14.16b urhadd v13.16b, v13.16b , v15.16b |