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| author | Serban Constantinescu <serban.constantinescu@arm.com> | 2013-06-14 14:49:14 +0100 |
|---|---|---|
| committer | Steve Kondik <shade@chemlab.org> | 2014-02-02 02:03:18 -0800 |
| commit | bccafaba53f33e5abb36b1f18891dbc5aba228f2 (patch) | |
| tree | 25bf86f64485616f8fa70dd6c587a40d5503059e /vm/mterp | |
| parent | c28a3412e2d18872f0eae1b1a96bb29e6f6e0df9 (diff) | |
| download | android_dalvik-bccafaba53f33e5abb36b1f18891dbc5aba228f2.tar.gz android_dalvik-bccafaba53f33e5abb36b1f18891dbc5aba228f2.tar.bz2 android_dalvik-bccafaba53f33e5abb36b1f18891dbc5aba228f2.zip | |
Dalvik: Add hardware support for OP_LONG_TO_DOUBLE in the interpreter
The following patch adds hardware vfp support for OP_LONG_TO_DOUBLE
in the interpreter. Previously this opcode was implemented using one of
gcc's builtin helpers.
Change-Id: I7713aa03c0b0bed8df592710dd50ab3d13d4bd9b
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Diffstat (limited to 'vm/mterp')
| -rw-r--r-- | vm/mterp/arm-vfp/OP_LONG_TO_DOUBLE.S | 28 | ||||
| -rw-r--r-- | vm/mterp/config-armv7-a-neon | 2 | ||||
| -rw-r--r-- | vm/mterp/out/InterpAsm-armv7-a-neon.S | 28 |
3 files changed, 45 insertions, 13 deletions
diff --git a/vm/mterp/arm-vfp/OP_LONG_TO_DOUBLE.S b/vm/mterp/arm-vfp/OP_LONG_TO_DOUBLE.S new file mode 100644 index 000000000..3ed3b194b --- /dev/null +++ b/vm/mterp/arm-vfp/OP_LONG_TO_DOUBLE.S @@ -0,0 +1,28 @@ +%default {} +%verify "executed" + /* + * Specialised 64-bit floating point operation. + * + * Note: The result will be returned in d2. + * + * For: long-to-double + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + add r3, rFP, r3, lsl #2 @ r3<- &fp[B] + add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + vldr d0, [r3] @ d0<- vAA + FETCH_ADVANCE_INST(1) @ advance rPC, load rINST + + vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) + vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) + vldr d3, constval$opcode + vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl + + GET_INST_OPCODE(ip) @ extract opcode from rINST + vstr.64 d2, [r9] @ vAA<- d2 + GOTO_OPCODE(ip) @ jump to next instruction + + /* literal pool helper */ +constval${opcode}: + .8byte 0x41f0000000000000 diff --git a/vm/mterp/config-armv7-a-neon b/vm/mterp/config-armv7-a-neon index 7f4295023..e91661a85 100644 --- a/vm/mterp/config-armv7-a-neon +++ b/vm/mterp/config-armv7-a-neon @@ -92,7 +92,7 @@ op-start armv5te op OP_IPUT_QUICK armv6t2 op OP_IPUT_WIDE armv6t2 op OP_IPUT_WIDE_QUICK armv6t2 - op OP_LONG_TO_DOUBLE armv6t2 + op OP_LONG_TO_DOUBLE arm-vfp op OP_LONG_TO_FLOAT armv6t2 op OP_MOVE armv6t2 op OP_MOVE_WIDE armv6t2 diff --git a/vm/mterp/out/InterpAsm-armv7-a-neon.S b/vm/mterp/out/InterpAsm-armv7-a-neon.S index 9dc851c08..86f7ab044 100644 --- a/vm/mterp/out/InterpAsm-armv7-a-neon.S +++ b/vm/mterp/out/InterpAsm-armv7-a-neon.S @@ -3667,29 +3667,33 @@ dalvik_inst: /* ------------------------------ */ .balign 64 .L_OP_LONG_TO_DOUBLE: /* 0x86 */ -/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ -/* File: armv6t2/unopWide.S */ +/* File: arm-vfp/OP_LONG_TO_DOUBLE.S */ /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. + * Specialised 64-bit floating point operation. * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long + * Note: The result will be returned in d2. + * + * For: long-to-double */ - /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B ubfx r9, rINST, #8, #4 @ r9<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] add r9, rFP, r9, lsl #2 @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA + vldr d0, [r3] @ d0<- vAA FETCH_ADVANCE_INST(1) @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed + + vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) + vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) + vldr d3, constvalOP_LONG_TO_DOUBLE + vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl + GET_INST_OPCODE(ip) @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 + vstr.64 d2, [r9] @ vAA<- d2 GOTO_OPCODE(ip) @ jump to next instruction - /* 10-11 instructions */ + /* literal pool helper */ +constvalOP_LONG_TO_DOUBLE: + .8byte 0x41f0000000000000 /* ------------------------------ */ .balign 64 |