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| author | Douglas Leung <douglas@mips.com> | 2012-11-26 18:57:38 -0800 |
|---|---|---|
| committer | Paul Lind <plind@mips.com> | 2012-11-26 18:58:40 -0800 |
| commit | 6e3967d1cca2f8baee1fa6e90f511553dd8651e5 (patch) | |
| tree | 6c5ff74974220c566a0a138e6d908d875a142924 /vm/mterp | |
| parent | 15d51db11420b8ec3dd885f5e790dab6b79ce1be (diff) | |
| download | android_dalvik-6e3967d1cca2f8baee1fa6e90f511553dd8651e5.tar.gz android_dalvik-6e3967d1cca2f8baee1fa6e90f511553dd8651e5.tar.bz2 android_dalvik-6e3967d1cca2f8baee1fa6e90f511553dd8651e5.zip | |
[MIPS] Fixing FP registers fs0 and fs1 corruption bug.
For performance reasons, we don't want to use "callee saved" FP registers.
The fix is to just use temporary FP registers instead.
Change-Id: Ifae20c707ff7022905a080892348bfbc151e4935
Signed-off-by: Douglas Leung <douglas@mips.com>
Diffstat (limited to 'vm/mterp')
| -rw-r--r-- | vm/mterp/mips/OP_CMPL_DOUBLE.S | 10 | ||||
| -rw-r--r-- | vm/mterp/mips/OP_CMPL_FLOAT.S | 10 | ||||
| -rw-r--r-- | vm/mterp/out/InterpAsm-mips.S | 40 |
3 files changed, 30 insertions, 30 deletions
diff --git a/vm/mterp/mips/OP_CMPL_DOUBLE.S b/vm/mterp/mips/OP_CMPL_DOUBLE.S index 63bb0055e..2c824b345 100644 --- a/vm/mterp/mips/OP_CMPL_DOUBLE.S +++ b/vm/mterp/mips/OP_CMPL_DOUBLE.S @@ -36,15 +36,15 @@ LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 b ${opcode}_continue #else - LOAD64_F(fs0, fs0f, rOBJ) - LOAD64_F(fs1, fs1f, rBIX) - c.olt.d fcc0, fs0, fs1 + LOAD64_F(ft0, ft0f, rOBJ) + LOAD64_F(ft1, ft1f, rBIX) + c.olt.d fcc0, ft0, ft1 li rTEMP, -1 bc1t fcc0, ${opcode}_finish - c.olt.d fcc0, fs1, fs0 + c.olt.d fcc0, ft1, ft0 li rTEMP, 1 bc1t fcc0, ${opcode}_finish - c.eq.d fcc0, fs0, fs1 + c.eq.d fcc0, ft0, ft1 li rTEMP, 0 bc1t fcc0, ${opcode}_finish b ${opcode}_nan diff --git a/vm/mterp/mips/OP_CMPL_FLOAT.S b/vm/mterp/mips/OP_CMPL_FLOAT.S index 6e070844d..01db92032 100644 --- a/vm/mterp/mips/OP_CMPL_FLOAT.S +++ b/vm/mterp/mips/OP_CMPL_FLOAT.S @@ -45,15 +45,15 @@ move a1, rBIX # a1 <- vCC b ${opcode}_continue #else - GET_VREG_F(fs0, a2) - GET_VREG_F(fs1, a3) - c.olt.s fcc0, fs0, fs1 # Is fs0 < fs1 + GET_VREG_F(ft0, a2) + GET_VREG_F(ft1, a3) + c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1 li rTEMP, -1 bc1t fcc0, ${opcode}_finish - c.olt.s fcc0, fs1, fs0 + c.olt.s fcc0, ft1, ft0 li rTEMP, 1 bc1t fcc0, ${opcode}_finish - c.eq.s fcc0, fs0, fs1 + c.eq.s fcc0, ft0, ft1 li rTEMP, 0 bc1t fcc0, ${opcode}_finish b ${opcode}_nan diff --git a/vm/mterp/out/InterpAsm-mips.S b/vm/mterp/out/InterpAsm-mips.S index dd43f1f2f..67cbdabd1 100644 --- a/vm/mterp/out/InterpAsm-mips.S +++ b/vm/mterp/out/InterpAsm-mips.S @@ -1542,15 +1542,15 @@ dalvik_inst: move a1, rBIX # a1 <- vCC b OP_CMPL_FLOAT_continue #else - GET_VREG_F(fs0, a2) - GET_VREG_F(fs1, a3) - c.olt.s fcc0, fs0, fs1 # Is fs0 < fs1 + GET_VREG_F(ft0, a2) + GET_VREG_F(ft1, a3) + c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1 li rTEMP, -1 bc1t fcc0, OP_CMPL_FLOAT_finish - c.olt.s fcc0, fs1, fs0 + c.olt.s fcc0, ft1, ft0 li rTEMP, 1 bc1t fcc0, OP_CMPL_FLOAT_finish - c.eq.s fcc0, fs0, fs1 + c.eq.s fcc0, ft0, ft1 li rTEMP, 0 bc1t fcc0, OP_CMPL_FLOAT_finish b OP_CMPL_FLOAT_nan @@ -1605,15 +1605,15 @@ dalvik_inst: move a1, rBIX # a1 <- vCC b OP_CMPG_FLOAT_continue #else - GET_VREG_F(fs0, a2) - GET_VREG_F(fs1, a3) - c.olt.s fcc0, fs0, fs1 # Is fs0 < fs1 + GET_VREG_F(ft0, a2) + GET_VREG_F(ft1, a3) + c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1 li rTEMP, -1 bc1t fcc0, OP_CMPG_FLOAT_finish - c.olt.s fcc0, fs1, fs0 + c.olt.s fcc0, ft1, ft0 li rTEMP, 1 bc1t fcc0, OP_CMPG_FLOAT_finish - c.eq.s fcc0, fs0, fs1 + c.eq.s fcc0, ft0, ft1 li rTEMP, 0 bc1t fcc0, OP_CMPG_FLOAT_finish b OP_CMPG_FLOAT_nan @@ -1659,15 +1659,15 @@ dalvik_inst: LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 b OP_CMPL_DOUBLE_continue #else - LOAD64_F(fs0, fs0f, rOBJ) - LOAD64_F(fs1, fs1f, rBIX) - c.olt.d fcc0, fs0, fs1 + LOAD64_F(ft0, ft0f, rOBJ) + LOAD64_F(ft1, ft1f, rBIX) + c.olt.d fcc0, ft0, ft1 li rTEMP, -1 bc1t fcc0, OP_CMPL_DOUBLE_finish - c.olt.d fcc0, fs1, fs0 + c.olt.d fcc0, ft1, ft0 li rTEMP, 1 bc1t fcc0, OP_CMPL_DOUBLE_finish - c.eq.d fcc0, fs0, fs1 + c.eq.d fcc0, ft0, ft1 li rTEMP, 0 bc1t fcc0, OP_CMPL_DOUBLE_finish b OP_CMPL_DOUBLE_nan @@ -1711,15 +1711,15 @@ dalvik_inst: LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1 b OP_CMPG_DOUBLE_continue #else - LOAD64_F(fs0, fs0f, rOBJ) - LOAD64_F(fs1, fs1f, rBIX) - c.olt.d fcc0, fs0, fs1 + LOAD64_F(ft0, ft0f, rOBJ) + LOAD64_F(ft1, ft1f, rBIX) + c.olt.d fcc0, ft0, ft1 li rTEMP, -1 bc1t fcc0, OP_CMPG_DOUBLE_finish - c.olt.d fcc0, fs1, fs0 + c.olt.d fcc0, ft1, ft0 li rTEMP, 1 bc1t fcc0, OP_CMPG_DOUBLE_finish - c.eq.d fcc0, fs0, fs1 + c.eq.d fcc0, ft0, ft1 li rTEMP, 0 bc1t fcc0, OP_CMPG_DOUBLE_finish b OP_CMPG_DOUBLE_nan |