Revert JIT changes for now

 * Need fixed to play nice with perf

Revert "Dalvik: Add hardware vfp support for OP_LONG_TO_DOUBLE in JIT"

This reverts commit eadd85e3c0eceb448f4afb55ab6ef4b5f3b7736a.

Revert "Dalvik: Add sdiv support in the JIT"

This reverts commit c28a3412e2d18872f0eae1b1a96bb29e6f6e0df9.

5 files changed, 2 insertions, 131 deletions

diff --git a/vm/compiler/codegen/arm/ArmLIR.h b/vm/compiler/codegen/arm/ArmLIR.h
index da99410c2..773662b8a 100644
--- a/vm/compiler/codegen/arm/ArmLIR.h
+++ b/vm/compiler/codegen/arm/ArmLIR.h
@@ -433,8 +433,6 @@ typedef enum ArmOpcode {
                                     rd[15-12] [10100000] rm[3..0] */
     kThumb2Vdivd,        /* vdiv vd, vn, vm [111011101000] rn[19..16]
                                     rd[15-12] [10110000] rm[3..0] */
-    kThumb2VmlaF64,      /* vmla.F64 vd, vn, vm [111011100000] vn[19..16]
-                                     vd[15..12] [10110000] vm[3..0] */
     kThumb2VcvtIF,       /* vcvt.F32 vd, vm [1110111010111000] vd[15..12]
                                     [10101100] vm[3..0] */
     kThumb2VcvtID,       /* vcvt.F64 vd, vm [1110111010111000] vd[15..12]
@@ -447,10 +445,6 @@ typedef enum ArmOpcode {
                                        [10101100] vm[3..0] */
     kThumb2VcvtDF,       /* vcvt.F32.F64 vd, vm [1110111010110111] vd[15..12]
                                        [10111100] vm[3..0] */
-    kThumb2VcvtF64S32,   /* vcvt.F64.S32 vd, vm [1110111010111000] vd[15..12]
-                                       [10111100] vm[3..0] */
-    kThumb2VcvtF64U32,   /* vcvt.F64.U32 vd, vm [1110111010111000] vd[15..12]
-                                       [10110100] vm[3..0] */
     kThumb2Vsqrts,       /* vsqrt.f32 vd, vm [1110111010110001] vd[15..12]
                                        [10101100] vm[3..0] */
     kThumb2Vsqrtd,       /* vsqrt.f64 vd, vm [1110111010110001] vd[15..12]
@@ -620,14 +614,8 @@ typedef enum ArmOpcode {
                                   [10110000] imm4l[3-0] */
     kThumb2Mla,          /* mla [111110110000] rn[19-16] ra[15-12] rd[7-4]
                                   [0000] rm[3-0] */
-    kThumb2MlsRRRR,      /* mls [1111101110000] rn[19-16] ra[15-12] rd[11-8]
-                                  [0001] rm[3-0] */
     kThumb2Umull,        /* umull [111110111010] rn[19-16], rdlo[15-12]
                                   rdhi[11-8] [0000] rm[3-0] */
-    kThumb2SdivRRR,      /* sdiv [1111101111001 rn[19-16] [1111] rd[11-8]
-                                  [1111] rm[3-0] */
-    kThumb2UdivRRR,      /* udiv [1111101111011 rn[19-16] [1111] rd[11-8]
-                                  [1111] rm[3-0] */
     kThumb2Ldrex,        /* ldrex [111010000101] rn[19-16] rt[11-8] [1111]
                                   imm8[7-0] */
     kThumb2Strex,        /* strex [111010000100] rn[19-16] rt[11-8] rd[11-8]
diff --git a/vm/compiler/codegen/arm/Assemble.cpp b/vm/compiler/codegen/arm/Assemble.cpp
index 96a1b69e5..debe39b38 100644
--- a/vm/compiler/codegen/arm/Assemble.cpp
+++ b/vm/compiler/codegen/arm/Assemble.cpp
@@ -447,10 +447,6 @@ ArmEncodingMap EncodingMap[kArmLast] = {
                  kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
                  kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
                  "vdivd", "!0S, !1S, !2S", 2),
-    ENCODING_MAP(kThumb2VmlaF64,     0xee000b00,
-                 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
-                 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE012,
-                 "vmla", "!0S, !1S, !2S", 2),
     ENCODING_MAP(kThumb2VcvtIF,       0xeeb80ac0,
                  kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
                  kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
@@ -475,14 +471,6 @@ ArmEncodingMap EncodingMap[kArmLast] = {
                  kFmtSfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
                  kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
                  "vcvt.f32.f64 ", "!0s, !1S", 2),
-    ENCODING_MAP(kThumb2VcvtF64S32,   0xeeb80bc0,
-                 kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
-                 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
-                 "vcvt.f64.s32 ", "!0S, !1s", 2),
-    ENCODING_MAP(kThumb2VcvtF64U32,   0xeeb80b40,
-                 kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
-                 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
-                 "vcvt.f64.u32 ", "!0S, !1s", 2),
     ENCODING_MAP(kThumb2Vsqrts,       0xeeb10ac0,
                  kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
                  kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
@@ -859,26 +847,11 @@ ArmEncodingMap EncodingMap[kArmLast] = {
                  kFmtBitBlt, 15, 12,
                  IS_QUAD_OP | REG_DEF0 | REG_USE1 | REG_USE2 | REG_USE3,
                  "mla", "r!0d, r!1d, r!2d, r!3d", 2),
-    ENCODING_MAP(kThumb2MlsRRRR,  0xfb000010,
-                 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
-                 kFmtBitBlt, 15, 12,
-                 IS_QUAD_OP | REG_DEF0 | REG_USE1 | REG_USE2 | REG_USE3,
-                 "mls", "r!0d, r!1d, r!2d, r!3d", 2),
     ENCODING_MAP(kThumb2Umull,  0xfba00000,
                  kFmtBitBlt, 15, 12, kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16,
                  kFmtBitBlt, 3, 0,
                  IS_QUAD_OP | REG_DEF0 | REG_DEF1 | REG_USE2 | REG_USE3,
                  "umull", "r!0d, r!1d, r!2d, r!3d", 2),
-    ENCODING_MAP(kThumb2SdivRRR,  0xfb90f0f0,
-                 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
-                 kFmtUnused, -1, -1,
-                 IS_TERTIARY_OP | REG_DEF0_USE12,
-                 "sdiv", "r!0d, r!1d, r!2d", 2),
-    ENCODING_MAP(kThumb2UdivRRR,  0xfbb0f0f0,
-                 kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0,
-                 kFmtUnused, -1, -1,
-                 IS_TERTIARY_OP | REG_DEF0 | REG_USE1 | REG_USE2,
-                 "udiv", "r!0d, r!1d, r!2d", 2),
     ENCODING_MAP(kThumb2Ldrex,       0xe8500f00,
                  kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
                  kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
diff --git a/vm/compiler/codegen/arm/CodegenDriver.cpp b/vm/compiler/codegen/arm/CodegenDriver.cpp
index b61b89407..93ea6133a 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.cpp
+++ b/vm/compiler/codegen/arm/CodegenDriver.cpp
@@ -827,7 +827,6 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
     int (*callTgt)(int, int) = NULL;
     RegLocation rlResult;
     bool shiftOp = false;
-    bool remOp = false;
 
     switch (mir->dalvikInsn.opcode) {
         case OP_NEG_INT:
@@ -852,27 +851,18 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
             break;
         case OP_DIV_INT:
         case OP_DIV_INT_2ADDR:
-#ifdef __ARM_ARCH_EXT_IDIV__
-            op = kOpDiv;
-#else
             callOut = true;
+            checkZero = true;
             callTgt = __aeabi_idiv;
             retReg = r0;
-#endif
-            checkZero = true;
             break;
         /* NOTE: returns in r1 */
         case OP_REM_INT:
         case OP_REM_INT_2ADDR:
-#ifdef __ARM_ARCH_EXT_IDIV__
-            op = kOpRem;
-            remOp = true;
-#else
             callOut = true;
+            checkZero = true;
             callTgt = __aeabi_idivmod;
             retReg = r1;
-#endif
-            checkZero = true;
             break;
         case OP_AND_INT:
         case OP_AND_INT_2ADDR:
@@ -914,11 +904,6 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
                      rlSrc1.lowReg);
         } else {
             rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
-#ifdef __ARM_ARCH_EXT_IDIV__
-            if (checkZero) {
-                genNullCheck(cUnit, rlSrc2.sRegLow, r1, mir->offset, NULL);
-            }
-#endif
             if (shiftOp) {
                 int tReg = dvmCompilerAllocTemp(cUnit);
                 opRegRegImm(cUnit, kOpAnd, tReg, rlSrc2.lowReg, 31);
@@ -926,14 +911,6 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
                 opRegRegReg(cUnit, op, rlResult.lowReg,
                             rlSrc1.lowReg, tReg);
                 dvmCompilerFreeTemp(cUnit, tReg);
-            } else if(remOp) {
-                int tReg = dvmCompilerAllocTemp(cUnit);
-                opRegRegReg(cUnit, kOpDiv, tReg,
-                            rlSrc1.lowReg, rlSrc2.lowReg);
-                rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
-                opRegRegRegReg(cUnit, op, rlResult.lowReg,
-                               rlSrc2.lowReg, tReg, rlSrc1.lowReg);
-                dvmCompilerFreeTemp(cUnit, tReg);
             } else {
                 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
                 opRegRegReg(cUnit, op, rlResult.lowReg,
@@ -2358,7 +2335,6 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
     OpKind op = (OpKind)0;      /* Make gcc happy */
     int shiftOp = false;
     bool isDiv = false;
-    bool isRem = false;
 
     switch (dalvikOpcode) {
         case OP_RSUB_INT_LIT8:
@@ -2428,17 +2404,6 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
             if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) {
                 return false;
             }
-#ifdef __ARM_ARCH_EXT_IDIV__
-            if ((dalvikOpcode == OP_DIV_INT_LIT8) ||
-                (dalvikOpcode == OP_DIV_INT_LIT16)) {
-                op = kOpDiv;
-            }
-            else {
-                isRem = true;
-                op = kOpRem;
-            }
-            break;
-#endif
             dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
             loadValueDirectFixed(cUnit, rlSrc, r0);
             dvmCompilerClobber(cUnit, r0);
@@ -2468,15 +2433,6 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
     // Avoid shifts by literal 0 - no support in Thumb.  Change to copy
     if (shiftOp && (lit == 0)) {
         genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
-    } else if(isRem) {
-        int tReg1 = dvmCompilerAllocTemp(cUnit);
-        int tReg2 = dvmCompilerAllocTemp(cUnit);
-
-        loadConstant(cUnit, tReg2, lit);
-        opRegRegReg(cUnit, kOpDiv, tReg1, rlSrc.lowReg, tReg2);
-        opRegRegRegReg(cUnit, op, rlResult.lowReg, tReg2, tReg1, rlSrc.lowReg);
-        dvmCompilerFreeTemp(cUnit, tReg1);
-        dvmCompilerFreeTemp(cUnit, tReg2);
     } else {
         opRegRegImm(cUnit, op, rlResult.lowReg, rlSrc.lowReg, lit);
     }
diff --git a/vm/compiler/codegen/arm/FP/Thumb2VFP.cpp b/vm/compiler/codegen/arm/FP/Thumb2VFP.cpp
index 0ee1b8fb5..750cbdc19 100644
--- a/vm/compiler/codegen/arm/FP/Thumb2VFP.cpp
+++ b/vm/compiler/codegen/arm/FP/Thumb2VFP.cpp
@@ -108,30 +108,6 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
     return false;
 }
 
-static bool genConversionL2D(CompilationUnit *cUnit, MIR *mir)
-{
-    int srcReg, tmp1, tmp2;
-    RegLocation rlSrc;
-    RegLocation rlDest;
-    RegLocation rlResult;
-
-    rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
-    rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
-    srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
-    rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
-    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
-    tmp1 = dvmCompilerAllocTypedTempPair(cUnit, true, kFPReg);
-    tmp2 = dvmCompilerAllocTypedTempPair(cUnit, true, kFPReg);
-    newLIR2(cUnit, (ArmOpcode)kThumb2VcvtF64S32, tmp1, ((srcReg & 0xff)+1));
-    newLIR2(cUnit, (ArmOpcode)kThumb2VcvtF64U32, S2D(rlResult.lowReg, rlResult.highReg),
-            (srcReg & 0xff));
-    loadConstantValueWide(cUnit, (tmp2 & 0xff), ((tmp2 >> 8) & 0xff), 0x0, 0x41f00000);
-    newLIR3(cUnit, (ArmOpcode)kThumb2VmlaF64, S2D(rlResult.lowReg, rlResult.highReg),
-                    tmp1, tmp2);
-    storeValueWide(cUnit, rlDest, rlResult);
-    return false;
-}
-
 static bool genConversion(CompilationUnit *cUnit, MIR *mir)
 {
     Opcode opcode = mir->dalvikInsn.opcode;
@@ -175,7 +151,6 @@ static bool genConversion(CompilationUnit *cUnit, MIR *mir)
             op = kThumb2VcvtDI;
             break;
         case OP_LONG_TO_DOUBLE:
-            return genConversionL2D(cUnit, mir);
         case OP_FLOAT_TO_LONG:
         case OP_LONG_TO_FLOAT:
         case OP_DOUBLE_TO_LONG:
diff --git a/vm/compiler/codegen/arm/Thumb2/Factory.cpp b/vm/compiler/codegen/arm/Thumb2/Factory.cpp
index 39cfc46e8..f1fa19d29 100644
--- a/vm/compiler/codegen/arm/Thumb2/Factory.cpp
+++ b/vm/compiler/codegen/arm/Thumb2/Factory.cpp
@@ -361,10 +361,6 @@ static ArmLIR *opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
             assert(shift == 0);
             opcode = (thumbForm) ? kThumbMul : kThumb2MulRRR;
             break;
-        case kOpDiv:
-            assert(shift == 0);
-            opcode = kThumb2SdivRRR;
-            break;
         case kOpMvn:
             opcode = (thumbForm) ? kThumbMvn : kThumb2MvnRR;
             break;
@@ -478,13 +474,6 @@ static ArmLIR *opRegRegRegShift(CompilationUnit *cUnit, OpKind op,
             assert(shift == 0);
             opcode = kThumb2MulRRR;
             break;
-        case kOpDiv:
-            assert(shift == 0);
-            opcode = kThumb2SdivRRR;
-            break;
-        case kOpRem:
-            opcode = kThumb2MlsRRRR;
-            break;
         case kOpOr:
             opcode = kThumb2OrrRRR;
             break;
@@ -526,12 +515,6 @@ static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
     return opRegRegRegShift(cUnit, op, rDest, rSrc1, rSrc2, 0);
 }
 
-static ArmLIR *opRegRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
-                           int rSrc1, int rSrc2, int rSrc3)
-{
-    return opRegRegRegShift(cUnit, op, rDest, rSrc1, rSrc2, rSrc3);
-}
-
 __attribute__((weak)) ArmLIR *opRegRegImmThumb2(CompilationUnit *cUnit, OpKind op, int rDest,
                                                     int rSrc1, int value)
 {
@@ -633,10 +616,6 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
             modImm = -1;
             altOpcode = kThumb2MulRRR;
             break;
-        case kOpDiv:
-            modImm = -1;
-            altOpcode = kThumb2SdivRRR;
-            break;
         case kOpCmp: {
             int modImm = modifiedImmediate(value);
             ArmLIR *res;