Also incorporate the former contents of OpCodeNames.h. This is a small
attempt to increase naming consistency in libdex. There will be a bit
more to come, in a follow-up.

Change-Id: Ia7ab06042dde2e19eda02ef1fee72fb4260e899d

Although we don't yet generate any of the extended opcodes, this
change makes it a bit easier to add them.

In particular, we now differentiate between the raw opcode in a code
unit and an associated "packed opcode number." The packed opcode space
is densely populated in the range 0x000-0x1ff (though there will still
be a few unused slots), whereas the raw opcode values are sparse
throughout the range 0x0000-0xffff.

The OpCode enum is redefined/clarified to have packed, not sparse,
opcode values.

Change-Id: Ie3208a258648fbf044d344646f66c49ad24c31b2

Change-Id: Ic9d7fcfd234116099ef510e4339a9af0bc3fcb1d

This is, once again, an intermediate step. Soon, I'm going to try to
remove need to keep and pass copies of the opcode info pointers all
over the place.

Change-Id: Ic6af849310b22ca604a7f2d18c78ff8d112459b4

This was another one that was pretty easy to add to opcode-gen. I did
end up tweaking opcode-gen to make it obvious that the two forms of
name are different by more than just upper vs. lower case, especially
because I duplicated the original distinction of the optimized opcodes
having extra prefix characters in their human-oriented names but not
in the names when used as programming constants.

Change-Id: I5062442540d26318914964bd2722cc32380b19ca

This was the easiest bit to tackle in libdex. More to come!

Change-Id: I3f79039ce98951d694d2c896ee1c7a60b417bc49

This introduces the return-void-barrier instruction, which is identical
to return-void on UP systems, but provides an additional store/store
barrier on SMP.  This is intended for use in constructors of objects
with final fields.

The assembler doesn't like "dmb st", and we don't have an
ANDROID_MEMBAR_STORE barrier defined, so this currently uses full
fences.

This just defines the new instruction.  It's not actually used yet.

Also, removed some stale "unused" files from the x86 and x86-atom
directories.

Bug 2965743.

Change-Id: I072e372fd2d57f2617a8d4fff5fd4b38bdda75d1

This adds instructions for {i,s}{get,put}{,-object}-volatile, for a
total of eight new instructions.

On SMP systems, these instructions will be substituted in for existing
field access instructions, either by dexopt or during just-in-time
verification.  Unlike the wide-volatile instructions, these will not be
used at all when the VM is not built for SMP.

(Ideally we'd omit the volatile instruction implementations entirely on
non-SMP builds, but that requires a little work in gen-mterp.py.)

The change defines and implements the opcodes and support methods, but
does not cause them to be used.

Also, changed dvmQuasiAtomicRead64's argument to be const.

Change-Id: I9e44fe881e87f27aa41f6c6e898ec4402cb5493e

Change-Id: I95534bb2b88eaf48f2329282041118cd034c812b

This adds four new instructions for accessing volatile wide fields (long
and double).  The JLS requires that such accesses are atomic, but the
VM doesn't otherwise make guarantees about the atomicity of reads and
writes on 64-bit fields.

There are no behavioral changes.  This just adds definitions for the new
instructions and a couple of tests.  The current implementation is just
the non-volatile form of the instructions or a C stub, but since we're
not generating them it doesn't really matter yet.

Also:
 - bumped Dalvik version to 1.3.0
 - added a note to the x86-atom TODO list

For bug 1633591.