/* * Copyright (C) 2012 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "codegen_x86.h" #include "dex/quick/mir_to_lir-inl.h" #include "x86_lir.h" namespace art { #define MAX_ASSEMBLER_RETRIES 50 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" }, { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" }, { kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" }, #define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ rm8_r8, rm32_r32, \ r8_rm8, r32_rm32, \ ax8_i8, ax32_i32, \ rm8_i8, rm8_i8_modrm, \ rm32_i32, rm32_i32_modrm, \ rm32_i8, rm32_i8_modrm) \ { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \ { kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<skeleton.prefix1 > 0) { ++size; if (entry->skeleton.prefix2 > 0) { ++size; } } ++size; // opcode if (entry->skeleton.opcode == 0x0F) { ++size; if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { ++size; } } ++size; // modrm if (has_sib || base == rX86_SP) { // SP requires a SIB byte. ++size; } if (displacement != 0 || base == rBP) { // BP requires an explicit displacement, even when it's 0. if (entry->opcode != kX86Lea32RA) { DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name; } size += IS_SIMM8(displacement) ? 1 : 4; } size += entry->skeleton.immediate_bytes; return size; } int X86Mir2Lir::GetInsnSize(LIR* lir) { const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; switch (entry->kind) { case kData: return 4; // 4 bytes of data case kNop: return lir->operands[0]; // length of nop is sole operand case kNullary: return 1; // 1 byte of opcode case kReg: // lir operands - 0: reg return ComputeSize(entry, 0, 0, false); case kMem: // lir operands - 0: base, 1: disp return ComputeSize(entry, lir->operands[0], lir->operands[1], false); case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp return ComputeSize(entry, lir->operands[0], lir->operands[3], true); case kMemReg: // lir operands - 0: base, 1: disp, 2: reg return ComputeSize(entry, lir->operands[0], lir->operands[1], false); case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg return ComputeSize(entry, lir->operands[0], lir->operands[3], true); case kThreadReg: // lir operands - 0: disp, 1: reg return ComputeSize(entry, 0, lir->operands[0], false); case kRegReg: return ComputeSize(entry, 0, 0, false); case kRegRegStore: return ComputeSize(entry, 0, 0, false); case kRegMem: // lir operands - 0: reg, 1: base, 2: disp return ComputeSize(entry, lir->operands[1], lir->operands[2], false); case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp return ComputeSize(entry, lir->operands[1], lir->operands[4], true); case kRegThread: // lir operands - 0: reg, 1: disp return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit case kRegImm: { // lir operands - 0: reg, 1: immediate size_t size = ComputeSize(entry, 0, 0, false); if (entry->skeleton.ax_opcode == 0) { return size; } else { // AX opcodes don't require the modrm byte. int reg = lir->operands[0]; return size - (reg == rAX ? 1 : 0); } } case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate return ComputeSize(entry, lir->operands[0], lir->operands[1], false); case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate return ComputeSize(entry, lir->operands[0], lir->operands[3], true); case kThreadImm: // lir operands - 0: disp, 1: imm return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm return ComputeSize(entry, 0, 0, false); case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm return ComputeSize(entry, lir->operands[1], lir->operands[2], false); case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm return ComputeSize(entry, lir->operands[1], lir->operands[4], true); case kMovRegImm: // lir operands - 0: reg, 1: immediate return 1 + entry->skeleton.immediate_bytes; case kShiftRegImm: // lir operands - 0: reg, 1: immediate // Shift by immediate one has a shorter opcode. return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0); case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate // Shift by immediate one has a shorter opcode. return ComputeSize(entry, lir->operands[0], lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0); case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate // Shift by immediate one has a shorter opcode. return ComputeSize(entry, lir->operands[0], lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0); case kShiftRegCl: return ComputeSize(entry, 0, 0, false); case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl return ComputeSize(entry, lir->operands[0], lir->operands[1], false); case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg return ComputeSize(entry, lir->operands[0], lir->operands[3], true); case kRegCond: // lir operands - 0: reg, 1: cond return ComputeSize(entry, 0, 0, false); case kMemCond: // lir operands - 0: base, 1: disp, 2: cond return ComputeSize(entry, lir->operands[0], lir->operands[1], false); case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond return ComputeSize(entry, lir->operands[0], lir->operands[3], true); case kJcc: if (lir->opcode == kX86Jcc8) { return 2; // opcode + rel8 } else { DCHECK(lir->opcode == kX86Jcc32); return 6; // 2 byte opcode + rel32 } case kJmp: if (lir->opcode == kX86Jmp8) { return 2; // opcode + rel8 } else if (lir->opcode == kX86Jmp32) { return 5; // opcode + rel32 } else { DCHECK(lir->opcode == kX86JmpR); return 2; // opcode + modrm } case kCall: switch (lir->opcode) { case kX86CallR: return 2; // opcode modrm case kX86CallM: // lir operands - 0: base, 1: disp return ComputeSize(entry, lir->operands[0], lir->operands[1], false); case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp return ComputeSize(entry, lir->operands[0], lir->operands[3], true); case kX86CallT: // lir operands - 0: disp return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit default: break; } break; case kPcRel: if (entry->opcode == kX86PcRelLoadRA) { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table return ComputeSize(entry, lir->operands[1], 0x12345678, true); } else { DCHECK(entry->opcode == kX86PcRelAdr); return 5; // opcode with reg + 4 byte immediate } case kMacro: DCHECK_EQ(lir->opcode, static_cast(kX86StartOfMethod)); return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) - (lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding default: break; } UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; return 0; } static uint8_t ModrmForDisp(int base, int disp) { // BP requires an explicit disp, so do not omit it in the 0 case if (disp == 0 && base != rBP) { return 0; } else if (IS_SIMM8(disp)) { return 1; } else { return 2; } } void X86Mir2Lir::EmitDisp(int base, int disp) { // BP requires an explicit disp, so do not omit it in the 0 case if (disp == 0 && base != rBP) { return; } else if (IS_SIMM8(disp)) { code_buffer_.push_back(disp & 0xFF); } else { code_buffer_.push_back(disp & 0xFF); code_buffer_.push_back((disp >> 8) & 0xFF); code_buffer_.push_back((disp >> 16) & 0xFF); code_buffer_.push_back((disp >> 24) & 0xFF); } } void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg)) { reg = reg & X86_FP_REG_MASK; } if (reg >= 4) { DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast(reg) << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); } DCHECK_LT(reg, 8); uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; code_buffer_.push_back(modrm); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); DCHECK_LT(entry->skeleton.modrm_opcode, 8); DCHECK_LT(base, 8); uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base; code_buffer_.push_back(modrm); EmitDisp(base, disp); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg)) { reg = reg & X86_FP_REG_MASK; } if (reg >= 4) { DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast(reg) << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); } DCHECK_LT(reg, 8); DCHECK_LT(base, 8); uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | base; code_buffer_.push_back(modrm); if (base == rX86_SP) { // Special SIB for SP base code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP); } EmitDisp(base, disp); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp) { // Opcode will flip operands. EmitMemReg(entry, base, disp, reg); } void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, int scale, int disp) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg)) { reg = reg & X86_FP_REG_MASK; } DCHECK_LT(reg, 8); uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP; code_buffer_.push_back(modrm); DCHECK_LT(scale, 4); DCHECK_LT(index, 8); DCHECK_LT(base, 8); uint8_t sib = (scale << 6) | (index << 3) | base; code_buffer_.push_back(sib); EmitDisp(base, disp); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) { // Opcode will flip operands. EmitRegArray(entry, reg, base, index, scale, disp); } void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) { DCHECK_NE(entry->skeleton.prefix1, 0); code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg)) { reg = reg & X86_FP_REG_MASK; } if (reg >= 4) { DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast(reg) << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); } DCHECK_LT(reg, 8); uint8_t modrm = (0 << 6) | (reg << 3) | rBP; code_buffer_.push_back(modrm); code_buffer_.push_back(disp & 0xFF); code_buffer_.push_back((disp >> 8) & 0xFF); code_buffer_.push_back((disp >> 16) & 0xFF); code_buffer_.push_back((disp >> 24) & 0xFF); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg1)) { reg1 = reg1 & X86_FP_REG_MASK; } if (X86_FPREG(reg2)) { reg2 = reg2 & X86_FP_REG_MASK; } DCHECK_LT(reg1, 8); DCHECK_LT(reg2, 8); uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; code_buffer_.push_back(modrm); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg1)) { reg1 = reg1 & X86_FP_REG_MASK; } if (X86_FPREG(reg2)) { reg2 = reg2 & X86_FP_REG_MASK; } DCHECK_LT(reg1, 8); DCHECK_LT(reg2, 8); uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; code_buffer_.push_back(modrm); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); switch (entry->skeleton.immediate_bytes) { case 1: DCHECK(IS_SIMM8(imm)); code_buffer_.push_back(imm & 0xFF); break; case 2: DCHECK(IS_SIMM16(imm)); code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); break; case 4: code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); code_buffer_.push_back((imm >> 16) & 0xFF); code_buffer_.push_back((imm >> 24) & 0xFF); break; default: LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes << ") for instruction: " << entry->name; break; } } void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } if (reg == rAX && entry->skeleton.ax_opcode != 0) { code_buffer_.push_back(entry->skeleton.ax_opcode); } else { code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (X86_FPREG(reg)) { reg = reg & X86_FP_REG_MASK; } uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; code_buffer_.push_back(modrm); } switch (entry->skeleton.immediate_bytes) { case 1: DCHECK(IS_SIMM8(imm)); code_buffer_.push_back(imm & 0xFF); break; case 2: DCHECK(IS_SIMM16(imm)); code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); break; case 4: code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); code_buffer_.push_back((imm >> 16) & 0xFF); code_buffer_.push_back((imm >> 24) & 0xFF); break; default: LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes << ") for instruction: " << entry->name; break; } } void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; code_buffer_.push_back(modrm); code_buffer_.push_back(disp & 0xFF); code_buffer_.push_back((disp >> 8) & 0xFF); code_buffer_.push_back((disp >> 16) & 0xFF); code_buffer_.push_back((disp >> 24) & 0xFF); switch (entry->skeleton.immediate_bytes) { case 1: DCHECK(IS_SIMM8(imm)); code_buffer_.push_back(imm & 0xFF); break; case 2: DCHECK(IS_SIMM16(imm)); code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); break; case 4: code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); code_buffer_.push_back((imm >> 16) & 0xFF); code_buffer_.push_back((imm >> 24) & 0xFF); break; default: LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes << ") for instruction: " << entry->name; break; } DCHECK_EQ(entry->skeleton.ax_opcode, 0); } void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { DCHECK_LT(reg, 8); code_buffer_.push_back(0xB8 + reg); code_buffer_.push_back(imm & 0xFF); code_buffer_.push_back((imm >> 8) & 0xFF); code_buffer_.push_back((imm >> 16) & 0xFF); code_buffer_.push_back((imm >> 24) & 0xFF); } void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } if (imm != 1) { code_buffer_.push_back(entry->skeleton.opcode); } else { // Shorter encoding for 1 bit shift code_buffer_.push_back(entry->skeleton.ax_opcode); } if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } if (reg >= 4) { DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast(reg) << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); } DCHECK_LT(reg, 8); uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; code_buffer_.push_back(modrm); if (imm != 1) { DCHECK_EQ(entry->skeleton.immediate_bytes, 1); DCHECK(IS_SIMM8(imm)); code_buffer_.push_back(imm & 0xFF); } } void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) { DCHECK_EQ(cl, static_cast(rCX)); if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); DCHECK_LT(reg, 8); uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; code_buffer_.push_back(modrm); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0x0F, entry->skeleton.opcode); code_buffer_.push_back(0x0F); DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); code_buffer_.push_back(0x90 | condition); DCHECK_EQ(0, entry->skeleton.extra_opcode2); DCHECK_LT(reg, 8); uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; code_buffer_.push_back(modrm); DCHECK_EQ(entry->skeleton.immediate_bytes, 0); } void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) { if (entry->opcode == kX86Jmp8) { DCHECK(IS_SIMM8(rel)); code_buffer_.push_back(0xEB); code_buffer_.push_back(rel & 0xFF); } else if (entry->opcode == kX86Jmp32) { code_buffer_.push_back(0xE9); code_buffer_.push_back(rel & 0xFF); code_buffer_.push_back((rel >> 8) & 0xFF); code_buffer_.push_back((rel >> 16) & 0xFF); code_buffer_.push_back((rel >> 24) & 0xFF); } else { DCHECK(entry->opcode == kX86JmpR); code_buffer_.push_back(entry->skeleton.opcode); uint8_t reg = static_cast(rel); DCHECK_LT(reg, 8); uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; code_buffer_.push_back(modrm); } } void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) { DCHECK_LT(cc, 16); if (entry->opcode == kX86Jcc8) { DCHECK(IS_SIMM8(rel)); code_buffer_.push_back(0x70 | cc); code_buffer_.push_back(rel & 0xFF); } else { DCHECK(entry->opcode == kX86Jcc32); code_buffer_.push_back(0x0F); code_buffer_.push_back(0x80 | cc); code_buffer_.push_back(rel & 0xFF); code_buffer_.push_back((rel >> 8) & 0xFF); code_buffer_.push_back((rel >> 16) & 0xFF); code_buffer_.push_back((rel >> 24) & 0xFF); } } void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) { if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base; code_buffer_.push_back(modrm); if (base == rX86_SP) { // Special SIB for SP base code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP); } EmitDisp(base, disp); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) { DCHECK_NE(entry->skeleton.prefix1, 0); code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; code_buffer_.push_back(modrm); code_buffer_.push_back(disp & 0xFF); code_buffer_.push_back((disp >> 8) & 0xFF); code_buffer_.push_back((disp >> 16) & 0xFF); code_buffer_.push_back((disp >> 24) & 0xFF); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, int scale, int table_or_disp) { int disp; if (entry->opcode == kX86PcRelLoadRA) { Mir2Lir::SwitchTable *tab_rec = reinterpret_cast(table_or_disp); disp = tab_rec->offset; } else { DCHECK(entry->opcode == kX86PcRelAdr); Mir2Lir::FillArrayData *tab_rec = reinterpret_cast(base_or_table); disp = tab_rec->offset; } if (entry->skeleton.prefix1 != 0) { code_buffer_.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { code_buffer_.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } if (X86_FPREG(reg)) { reg = reg & X86_FP_REG_MASK; } DCHECK_LT(reg, 8); if (entry->opcode == kX86PcRelLoadRA) { code_buffer_.push_back(entry->skeleton.opcode); DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP; code_buffer_.push_back(modrm); DCHECK_LT(scale, 4); DCHECK_LT(index, 8); DCHECK_LT(base_or_table, 8); uint8_t base = static_cast(base_or_table); uint8_t sib = (scale << 6) | (index << 3) | base; code_buffer_.push_back(sib); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } else { code_buffer_.push_back(entry->skeleton.opcode + reg); } code_buffer_.push_back(disp & 0xFF); code_buffer_.push_back((disp >> 8) & 0xFF); code_buffer_.push_back((disp >> 16) & 0xFF); code_buffer_.push_back((disp >> 24) & 0xFF); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); } void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) { DCHECK(entry->opcode == kX86StartOfMethod) << entry->name; code_buffer_.push_back(0xE8); // call +0 code_buffer_.push_back(0); code_buffer_.push_back(0); code_buffer_.push_back(0); code_buffer_.push_back(0); DCHECK_LT(reg, 8); code_buffer_.push_back(0x58 + reg); // pop reg EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */); } void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " << BuildInsnString(entry->fmt, lir, 0); for (int i = 0; i < GetInsnSize(lir); ++i) { code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 } } /* * Assemble the LIR into binary instruction format. Note that we may * discover that pc-relative displacements may not fit the selected * instruction. In those cases we will try to substitute a new code * sequence or request that the trace be shortened and retried. */ AssemblerStatus X86Mir2Lir::AssembleInstructions(uintptr_t start_addr) { LIR *lir; AssemblerStatus res = kSuccess; // Assume success const bool kVerbosePcFixup = false; for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { if (lir->opcode < 0) { continue; } if (lir->flags.is_nop) { continue; } if (lir->flags.pcRelFixup) { switch (lir->opcode) { case kX86Jcc8: { LIR *target_lir = lir->target; DCHECK(target_lir != NULL); int delta = 0; uintptr_t pc; if (IS_SIMM8(lir->operands[0])) { pc = lir->offset + 2 /* opcode + rel8 */; } else { pc = lir->offset + 6 /* 2 byte opcode + rel32 */; } uintptr_t target = target_lir->offset; delta = target - pc; if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { if (kVerbosePcFixup) { LOG(INFO) << "Retry for JCC growth at " << lir->offset << " delta: " << delta << " old delta: " << lir->operands[0]; } lir->opcode = kX86Jcc32; SetupResourceMasks(lir); res = kRetryAll; } if (kVerbosePcFixup) { LOG(INFO) << "Source:"; DumpLIRInsn(lir, 0); LOG(INFO) << "Target:"; DumpLIRInsn(target_lir, 0); LOG(INFO) << "Delta " << delta; } lir->operands[0] = delta; break; } case kX86Jcc32: { LIR *target_lir = lir->target; DCHECK(target_lir != NULL); uintptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */; uintptr_t target = target_lir->offset; int delta = target - pc; if (kVerbosePcFixup) { LOG(INFO) << "Source:"; DumpLIRInsn(lir, 0); LOG(INFO) << "Target:"; DumpLIRInsn(target_lir, 0); LOG(INFO) << "Delta " << delta; } lir->operands[0] = delta; break; } case kX86Jmp8: { LIR *target_lir = lir->target; DCHECK(target_lir != NULL); int delta = 0; uintptr_t pc; if (IS_SIMM8(lir->operands[0])) { pc = lir->offset + 2 /* opcode + rel8 */; } else { pc = lir->offset + 5 /* opcode + rel32 */; } uintptr_t target = target_lir->offset; delta = target - pc; if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { // Useless branch lir->flags.is_nop = true; if (kVerbosePcFixup) { LOG(INFO) << "Retry for useless branch at " << lir->offset; } res = kRetryAll; } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { if (kVerbosePcFixup) { LOG(INFO) << "Retry for JMP growth at " << lir->offset; } lir->opcode = kX86Jmp32; SetupResourceMasks(lir); res = kRetryAll; } lir->operands[0] = delta; break; } case kX86Jmp32: { LIR *target_lir = lir->target; DCHECK(target_lir != NULL); uintptr_t pc = lir->offset + 5 /* opcode + rel32 */; uintptr_t target = target_lir->offset; int delta = target - pc; lir->operands[0] = delta; break; } default: break; } } /* * If one of the pc-relative instructions expanded we'll have * to make another pass. Don't bother to fully assemble the * instruction. */ if (res != kSuccess) { continue; } CHECK_EQ(static_cast(lir->offset), code_buffer_.size()); const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; size_t starting_cbuf_size = code_buffer_.size(); switch (entry->kind) { case kData: // 4 bytes of data code_buffer_.push_back(lir->operands[0]); break; case kNullary: // 1 byte of opcode DCHECK_EQ(0, entry->skeleton.prefix1); DCHECK_EQ(0, entry->skeleton.prefix2); code_buffer_.push_back(entry->skeleton.opcode); if (entry->skeleton.extra_opcode1 != 0) { code_buffer_.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode2 != 0) { code_buffer_.push_back(entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); break; case kReg: // lir operands - 0: reg EmitOpReg(entry, lir->operands[0]); break; case kMem: // lir operands - 0: base, 1: disp EmitOpMem(entry, lir->operands[0], lir->operands[1]); break; case kMemReg: // lir operands - 0: base, 1: disp, 2: reg EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); break; case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3], lir->operands[4]); break; case kRegMem: // lir operands - 0: reg, 1: base, 2: disp EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); break; case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3], lir->operands[4]); break; case kRegThread: // lir operands - 0: reg, 1: disp EmitRegThread(entry, lir->operands[0], lir->operands[1]); break; case kRegReg: // lir operands - 0: reg1, 1: reg2 EmitRegReg(entry, lir->operands[0], lir->operands[1]); break; case kRegRegStore: // lir operands - 0: reg2, 1: reg1 EmitRegReg(entry, lir->operands[1], lir->operands[0]); break; case kRegRegImm: EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); break; case kRegImm: // lir operands - 0: reg, 1: immediate EmitRegImm(entry, lir->operands[0], lir->operands[1]); break; case kThreadImm: // lir operands - 0: disp, 1: immediate EmitThreadImm(entry, lir->operands[0], lir->operands[1]); break; case kMovRegImm: // lir operands - 0: reg, 1: immediate EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); break; case kShiftRegImm: // lir operands - 0: reg, 1: immediate EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); break; case kShiftRegCl: // lir operands - 0: reg, 1: cl EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); break; case kRegCond: // lir operands - 0: reg, 1: condition EmitRegCond(entry, lir->operands[0], lir->operands[1]); break; case kJmp: // lir operands - 0: rel EmitJmp(entry, lir->operands[0]); break; case kJcc: // lir operands - 0: rel, 1: CC, target assigned EmitJcc(entry, lir->operands[0], lir->operands[1]); break; case kCall: switch (entry->opcode) { case kX86CallM: // lir operands - 0: base, 1: disp EmitCallMem(entry, lir->operands[0], lir->operands[1]); break; case kX86CallT: // lir operands - 0: disp EmitCallThread(entry, lir->operands[0]); break; default: EmitUnimplemented(entry, lir); break; } break; case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3], lir->operands[4]); break; case kMacro: EmitMacro(entry, lir->operands[0], lir->offset); break; default: EmitUnimplemented(entry, lir); break; } CHECK_EQ(static_cast(GetInsnSize(lir)), code_buffer_.size() - starting_cbuf_size) << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; } return res; } } // namespace art