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* Fix for incorrect encode and parse of PEXTRW instructionnikolay serdjuk2015-04-291-0/+8
| | | | | | | | | | | | The instruction PEXTRW encoded by sequence 66 0F 3A 15 was incorrectly encoded in compiler table and incorrectly parsed by disassembler. Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com> (cherry picked from commit e0705f51fdc71e9670a29f8c3a47168f50724b35) Change-Id: I7f051e23789aa3745d6eb854c97f80c475748b74
* Fix for incorrect parse of PEXTRW instructionnikolay serdjuk2015-04-071-1/+1
| | | | | | | | | | The instruction PEXTRW encoded by sequence 66 0F C5 has form: PEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and xmm is encoded in the R/M part of ModR/M byte. Since the order is opposite to the PEXTRB and PEXTRD, we have to set 'load' to true and 'store' leave as false. Change-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d
* [optimizing] Implement x86/x86_64 math intrinsicsMark Mendell2015-04-011-0/+18
| | | | | | | | | | | | | | | | | | | Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* ART: Fix x86 disassemblerAndreas Gampe2015-01-271-10/+16
| | | | | | | | Index 4 in SIB is valid when given Rex.x, where it denotes r12 and not the invalid rsp. Bug: 19149560 Change-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850
* Fix crash in x86 disassembler.Nicolas Geoffray2014-12-161-1/+1
| | | | | | Probably a typo from last refactoring. Change-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945
* ART: Do not inline elf writer debug symbolsAndreas Gampe2014-12-151-2/+2
| | | | | | | | | Using Clang, this pushes the frame size of the caller across our limit. Thus forbid inlining. The function is only called once per compile, impact is insignificant. Bug: 18738594 Change-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c
* ART: Break up x86 disassembler main functionAndreas Gampe2014-12-151-237/+274
| | | | | | | | The function leads to large stack frames with Clang. Break out some parts and use four char* variables for opcode. Bug: 18733806 Change-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220
* Tidy x86 disassemblerIan Rogers2014-11-071-24/+84
| | | | Change-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e
* Tidy logging code not using UNIMPLEMENTED.Ian Rogers2014-10-241-2/+2
| | | | Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
* C++11 related clean-up of DISALLOW_..Ian Rogers2014-10-221-2/+3
| | | | | | | | | | | | | | | | | | Move DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations with no definitions this prompts better warning messages so deal with these by correcting the code. Add a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object. Make X86 assembly operand types ValueObjects to fix compilation errors. Tidy the use of iostream and ostream. Avoid making cutils a dependency via mutex-inl.h for tests that link against libart. Push tracing dependencies into appropriate files and mutex.cc. x86 32-bit host symbols size is increased for libarttest, avoid copying this in run-test 115 by using symlinks and remove this test's higher than normal ulimit. Fix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it returns NULL when the heap is under construction by Runtime. Change-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b
* Tidy up logging.Ian Rogers2014-10-221-0/+1
| | | | | | | | | | | | | | | | | Move gVerboseMethods to CompilerOptions. Now "--verbose-methods=" option to dex2oat rather than runtime argument "-verbose-methods:". Move ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc except for a forward declaration. Remove ConstDumpable as Dump methods are all const (and make this so if not currently true). Make LogSeverity an enum and improve compile time assertions and type checking. Remove log_severity.h that's only used in logging.h. With system headers gone from logging.h, go add to .cc files missing system header includes. Also, make operator new in ValueObject private for compile time instantiation checking. Change-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641
* Enable -Wimplicit-fallthrough.Ian Rogers2014-10-091-1/+1
| | | | | | | | Falling through switch cases on a clang build must now annotate the fallthrough with the FALLTHROUGH_INTENDED macro. Bug: 17731372 Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
* ART: Fix some -Wpedantic errorsAndreas Gampe2014-09-291-5/+5
| | | | | | | | | | | | | | | | Remove extra semicolons. Dollar signs in C++ identifiers are an extension. Named variadic macros are an extension. Binary literals are a C++14 feature. Enum re-declarations are not allowed. Overflow. Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
* Avoid printing absolute addresses in oatdumpBrian Carlstrom2014-09-161-3/+5
| | | | | | | | | | | | | | | | | - Added printing of OatClass offsets. - Added printing of OatMethod offsets. - Added bounds checks for code size size, code size, mapping table, gc map, vmap table. - Added sanity check of 100k for code size. - Added partial disassembly of questionable code. - Added --no-disassemble to disable disassembly. - Added --no-dump:vmap to disable vmap dumping. - Reordered OatMethod info to be in file order. Bug: 15567083 (cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f) Change-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8
* ART: Vectorization opcode implementation fixesLupusoru, Razvan A2014-09-031-59/+34
| | | | | | | | | This patch fixes the implementation of the x86 vectorization opcodes. Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com> Signed-off-by: Philbert Lin <philbert.lin@intel.com>
* ART: Add non-temporal store supportJean Christophe Beyler2014-08-261-0/+1
| | | | | | | | | | | Added non-temporal store support as a hint from the ME. Added the implementation of the memory barrier extended instruction that supports non-temporal stores by explicitly serializing all previous store-to-memory instructions. Change-Id: I8205a92083f9725253d8ce893671a133a0b6849d Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
* Implement inlined shift long for 32bitYixin Shou2014-08-141-0/+12
| | | | | | | Added support for x86 inlined shift long for 32bit Change-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa Signed-off-by: Yixin Shou <yixin.shou@intel.com>
* ART: Correct disassembling of 64bit immediates on x86_64Vladimir Kostyukov2014-07-301-2/+2
| | | | | | | | | The patch fixes an issue with disassembling 'movsxd' and 'movabsq' instructions altered with 64bit immediates: not only a REX.W prefix may be prepended to these instructions. Change-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* ART: Correct disassembling of regs from opcodesVladimir Kostyukov2014-07-091-3/+5
| | | | | | | | | | | | | | | | Registers, which are part of opcode might have 1-byte size or 2-byte size depending on the instruction and 66h prefix. This patch makes the decoding of such instruction correct. Examples: - '664155' should be decoded as 'push r13w' (66h + REX.B) - '41B320' should be decoded as 'mov r11l, 0x20' (byte-operand + REX.B) Change-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Merge "X86 Backend support for vectorized float and byte 16x16 operations"Ian Rogers2014-07-081-3/+17
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| * X86 Backend support for vectorized float and byte 16x16 operationsUdayan Banerji2014-07-081-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reserving vector registers for the duration of vector loop. Add support for 16x16 multiplication, shifts, and add reduce. Changed the vectorization implementation to be able to use the dataflow elements for SSA recreation and fixed a few implementation details. Change-Id: I2f358f05f574fc4ab299d9497517b9906f234b98 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Olivier Come <olivier.come@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
* | x86_64: Clean-up after cmp-long fixSerguei Katkov2014-07-091-4/+6
|/ | | | | | | | The patch adresses the coments from review done by Ian Rogers. Clean-up of assembler. Change-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
* Merge "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation"Ian Rogers2014-07-071-0/+27
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| * ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generationOlivier Come2014-06-251-0/+27
| | | | | | | | | | | | | | | | The patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation for X86. Change-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6 Signed-off-by: Olivier Come <olivier.come@intel.com>
* | ART: FF-opcodes are target-specificVladimir Kostyukov2014-07-031-8/+15
| | | | | | | | | | | | | | | | | | Some of the FF-opcodes' (i.e., push, call, jmp) register names depend on the the target (32-bit vs 64-bit). This patch makes such opcodes target-specific. Change-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | Load 64 bit constant into GPR by single instruction for 64bit modeYixin Shou2014-07-021-2/+12
| | | | | | | | | | | | | | | | | | This patch load 64 bit constant into a register by a single movabsq instruction on 64 bit bit instead of previous mov, shift, add instruction sequences. Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c Signed-off-by: Yixin Shou <yixin.shou@intel.com>
* | ART: FPU instructions support in disassemblerVladimir Kostyukov2014-07-011-5/+27
|/ | | | | | | | | | This patch extends the disassembler with new FPU instructions: - fstsw - fucompp - fprem Change-Id: I9458510bc17f2b3b286edec102552f64be05147e Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* X86 Dis: Add missing mov byte; Add size suffixesMark Mendell2014-06-211-6/+32
| | | | | | | | | Yet another instruction not disassembled properly. Add 'b', 'w', 'q' to opcodes to diffferentiate between various versions and make it more understandable. Change-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Add Move with Sign Extend Double to disassemblerMark Mendell2014-06-081-0/+11
| | | | | | | I noticed another missing instruction. Change-Id: I71170496b014ac2609116eff2aeb13a13e71e263 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Fix X86 disassambler printing of XMM, MM registersMark Mendell2014-06-051-1/+1
| | | | | | | Printing of uint8_t is done as a char, rather than an integer. Change-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* ART: x86_64 disassembler improvementsVladimir Kostyukov2014-06-041-21/+68
| | | | | | | | | | | | | | This patch (a) enables full support of 64bit extended regs r8-r15, including 8bit r8l-r15l, 16bit r8w-r15w and also 32bit r8d-r15d (b) fixes an issue with decoding reg from ModRM byte (REX.B should be used) (c) fixes an issue with decoding regs from SIB byte (regs that contain addr are target-specific) Change-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Support disassembly of 16-bit immediatesMark Mendell2014-05-301-2/+7
| | | | | Change-Id: I66f5ce93077241204311e52c547599f5287bae04 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Implement all vector instructions for X86Mark Mendell2014-05-241-4/+193
| | | | | | | | Add X86 code generation for the vector operations. Added support for X86 disassembler for the new instructions. Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* ART: Enables x86_64 disassemblyVladimir Kostyukov2014-04-251-7/+25
| | | | | | | | | This patch (a) cuts a REX prefix from the instruction and (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes. Change-Id: I2674678224ca27746b33d4006ed38d497972309f Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* ART: Fixes an issue with REX prefix for instructions with no ModRM byteVladimir Kostyukov2014-04-171-1/+1
| | | | | | | | | | | | | | | | | | There are instructions (such as push, pop, mov) in the x86 ISA that encode first operands in their opcodes (opcode + reg). In order to enable an extended 64bit registers (R9-R15) a special prefix REX.B should be emitted before such instructions. This patch fixes the issue when REX.R prefix was emitted before instructions with no MorRM byte. So, the REX-prefix was simply ignored by CPU for those instructions whose operands are encoded in their opcodes. This patch makes the jni_compiler_test passed with JNI compiler enabled for x86_64 target. Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Allow mixing of thread offsets between 32 and 64bit architectures.Ian Rogers2014-04-011-2/+6
| | | | | | | Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
* Relaxed memory barriers for x86Razvan A Lupusoru2014-03-261-0/+6
| | | | | | | | | | X86 provides stronger memory guarantees and thus the memory barriers can be optimized. This patch ensures that all memory barriers for x86 are treated as scheduling barriers. And in cases where a barrier is needed (StoreLoad case), an mfence is used. Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* x86-64 disassembler support.Ian Rogers2014-03-141-10/+16
| | | | Change-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0
* Inline x86 String.indexOfMark Mendell2014-02-201-0/+4
| | | | | | | | Take advantage of the presence of a constant search char or start index to tune the generated code. Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Support to generate inline long to FP bytecodes for x86Razvan A Lupusoru2014-02-111-0/+14
| | | | | | | | long-to-float and long-to-double are now generated inline instead of calling a helper routine. The conversion is done by using x87. Change-Id: I196e526afec1be212898baceca8527549c3655b6 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* Specializing x86 range argument copyingRazvan A Lupusoru2014-02-051-0/+36
| | | | | | | | | | The ARM implementation of range argument copying was specialized in some cases. For all other architectures, it would fall back to generating memcpy. This patch updates the x86 implementation so it does not call memcpy and instead generates loads and stores, favoring movement of 128-bit chunks. Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* Merge "Improve x86 long multiply and shifts"Ian Rogers2014-01-281-0/+12
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| * Improve x86 long multiply and shiftsMark Mendell2014-01-241-0/+12
| | | | | | | | | | | | | | | | | | | | Generate inline code for long shifts by constants and do long multiplication inline. Convert multiplication by a constant to a shift when we can. Fix some x86 assembler problems and add the new instructions that were needed (64 bit shifts). Change-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Reduce x86 sequence for GP pair to XMMRazvan A Lupusoru2014-01-241-0/+11
|/ | | | | | | | | | | Added support for punpckldq which is useful for interleaving 32-bit values from two xmm registers. This new instruction is now used for transfers from GP pairs to XMM in order to reduce path length. Change-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* Improve x86 long divideMark Mendell2014-01-241-0/+3
| | | | | | | | | | Implement inline division for literal and variable divisors. Use the general case for dividing by a literal by using a double length multiply by the appropriate constant with fixups. This is the Hacker's Delight algorithm. Change-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Add conditional move support to x86 and allow GenMinMax to use itRazvan A Lupusoru2014-01-081-0/+6
| | | | | | | | | | | | X86 supports conditional moves which is useful for reducing branchiness. This patch adds support to the x86 backend to generate conditional reg to reg operations. Both encoder and decoder support was added for cmov. The x86 version of GenMinMax used for generating inlined version Math.min/max has been updated to make use of the conditional move support. Change-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* Disassemble more x86 instructionsMark Mendell2013-12-121-0/+16
| | | | | | | | | | | | By using oatdump on the core.oat, I found a couple more instructions that didn't disassemble properly. These included another form of imul and some FP instructions used by the JNI code. Now the only unknown opcodes I could find seem to be literal data at the end of the method. Change-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Add missing x86 imul opcode to disassemblerMark Mendell2013-12-111-0/+1
| | | | | | | | When playing with ART, I noticed that an integer multiply didn't disassemble properly. This patch adds the instruction. Change-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Unsafe.compareAndSwapLong() intrinsic for x86.Vladimir Marko2013-12-031-0/+7
| | | | Change-Id: Idbc5371a62dfdd84485a657d4548990519200205
* Add byte swap instructions for ARM and x86.Vladimir Marko2013-10-281-0/+4
| | | | Change-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d
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