summaryrefslogtreecommitdiffstats
path: root/compiler/optimizing/codegen_test.cc
Commit message (Collapse)AuthorAgeFilesLines
* ART: Force constants into the entry blockDavid Brazdil2015-03-261-20/+12
| | | | | | | | | | | | | | | | | | Optimizations such as GVN and BCE make the assumption that all constants are located in the entry block of the CFG, but not all passes adhere to this rule. This patch makes constructors of constants private and only accessible to friend classes - HGraph for int/long constants and SsaBuilder for float/double - which ensure that they are placed correctly and not duplicated. Note that the ArenaAllocatorAdapter was modified to not increment the ArenaAllocator's internal reference counter in order to allow for use of ArenaSafeMap inside an arena-allocated objects. Because their destructor is not called, the counter does not get decremented. Change-Id: I36a4fa29ae34fb905cdefd482ccbf386cff14166
* ART: Fix crash in gtestsDavid Brazdil2015-03-241-0/+1
| | | | | | | SsaLivenessAnalysis was crashing after change of iteration order in 142377 because gtests do not always build reverse post order. Change-Id: If5ad5b7c52040b119c4415f0b942988049fa3c16
* Opt Compiler: ARM64: Enable explicit memory barriers over acquire/releaseSerban Constantinescu2015-03-021-4/+9
| | | | | | | | | | | | | | | | Implement remaining explicit memory barrier code paths and temporarily enable the use of explicit memory barriers for testing. This CL also enables the use of instruction set features in the ARM64 backend. kUseAcquireRelease has been replaced with PreferAcquireRelease(), which for now is statically set to false (prefer explicit memory barriers). Please note that we still prefer acquire-release for the ARM64 Optimizing Compiler, but we would like to exercise the explicit memory barrier code path too. Change-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Create HGraph outside Builder, print timingsDavid Brazdil2015-02-041-6/+8
| | | | | | | | | This patch refactors the way HGraph objects are created, moving the instantiation out of the Builder class and creating the CodeGenerator earlier. The patch uses this to build a single interface for printing timings info and dumping the CFG. Change-Id: I2eb63eabf28e2d0f5cdc7affaa690c3a4b1bdd21
* Fix lint error and typo.Nicolas Geoffray2015-01-261-2/+2
| | | | Change-Id: Ie2787a4da5b2d76975664e64f443c081127b7cd9
* Fix codegen_test.Nicolas Geoffray2015-01-261-5/+30
| | | | | | | Native and ART do not have the same calling convention for ART, so we need to adjust blocked and allocated registers. Change-Id: I606b2620c0e5a54bd60d6100a137c06616ad40b4
* Add implicit null checks for the optimizing compilerCalin Juravle2015-01-161-8/+13
| | | | | | | | | - for backends: arm, arm64, x86, x86_64 - fixed parameter passing for CodeGenerator - 003-omnibus-opcodes test verifies that NullPointerExceptions work as expected Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
* ART: Fix leak in codegen_testAndreas Gampe2015-01-061-1/+3
| | | | | | Make sure the InstructionSetFeatures isn't leaked. Change-Id: Ide25773500c1513ecb204a380bb0a95513ff7276
* Look at instruction set features when generating volatiles codeCalin Juravle2015-01-051-2/+3
| | | | Change-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a
* Opt compiler: Add arm64 support for register allocation.Alexandre Rames2014-12-101-18/+7
| | | Change-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7
* Instruction set features for ARM64, MIPS and X86.Ian Rogers2014-11-131-2/+2
| | | | | | | | | | | | | Also, refactor how feature strings are handled so they are additive or subtractive. Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler rather than #ifdefs that wouldn't have worked in cross-compilation. Add SIMD features for x86/x86-64 proposed in: https://android-review.googlesource.com/#/c/112370/ Bug: 18056890 Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
* Revert "Revert "Add support for long-to-int in the optimizing compiler.""Roland Levillain2014-11-111-0/+21
| | | | | | This reverts commit 3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a. Change-Id: Iacf0c6492d49267e24f1b727dbf6379b21fd02db
* Revert "Add support for long-to-int in the optimizing compiler."Roland Levillain2014-11-111-17/+0
| | | | | | This reverts commit 647b96f29cb81832e698f863884fdba06674c9de. Change-Id: I552f23585463c676acbd547521b4d3ee5c0342eb
* Fix lint error.Calin Juravle2014-11-111-4/+4
| | | | Change-Id: Ief9b9fe6982e7e76aae74d6c909bd9f4b3f82673
* Add support for long-to-int in the optimizing compiler.Roland Levillain2014-11-111-0/+17
| | | | | | | | | | | | - Add support for the long-to-int Dex instruction in the optimizing compiler. - Generate x86, x86-64 and ARM (but not ARM64) code for long-to-int HTypeConversion nodes. - Add related tests to test/422-type-conversion. - Also fix comments in test/415-optimizing-arith-neg and in test/416-optimizing-arith-not. Change-Id: I3084af30f2a495d178362ae1154dc7ceb7bf3a58
* Merge "[optimizing compiler] Add DIV_INT_2ADDR"Calin Juravle2014-11-061-0/+14
|\
| * [optimizing compiler] Add DIV_INT_2ADDRCalin Juravle2014-11-061-0/+14
| | | | | | | | Change-Id: I38fc7e216f820d8ccc8bbf8b8e7a67b75fb9de87
* | Add support for not-long on ARM64 in the optimizing compiler.Roland Levillain2014-11-061-12/+81
| | | | | | | | Change-Id: I3e98ff411ba358d92774def18a12daccdc4f558f
* | Fix failures after div support.Nicolas Geoffray2014-11-061-0/+4
|/ | | | | | | - We need to special case divide by -1 because of x86. - Disable div test on arm64, which does not support div yet. Change-Id: I07e137cb555a958b02a6c4070f296503b7e30bae
* [optimizing compiler] Add div-int and exception handling.Calin Juravle2014-11-061-0/+9
| | | | | | | | | | | | - for backends: arm, x86, x86_64 - fixed a register allocator bug: the request for a fixed register for the first input was ignored if the output was kSameAsFirstInput - added divide by zero exception - more tests - shuffle around some code in the builder to reduce the number of lines of code for a single function. Change-Id: Id3a515e02bfbc66cd9d16cb9746f7551bdab3d42
* ART: More warningsAndreas Gampe2014-11-041-9/+9
| | | | | | | Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
* Opt compiler: Add ARM64 support for the Mul IR.Alexandre Rames2014-10-291-8/+0
| | | | | | | | | | | Also disable compilation and use of the boot image with the optimizing compiler: this won't work with the way we're bringing up arm64 and we need to find a better solution. Bug: 18147756 Change-Id: I6ec0de73681f9226d095bc3db92338dbd46499aa
* ART: Add basic tests for materialized conditions.Alexandre Rames2014-10-231-0/+117
| | | | Change-Id: I4acef30cc6a48b5fe07d55db6b9cf0d093b326ee
* ART: optimizing compiler: initial support for ARM64.Alexandre Rames2014-10-231-0/+17
| | | | | | | | | | The ARM64 port uses VIXL for code generation, to which it defers work like label binding and branch resolving, register type coherency checking, and immediate values handling. Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com> Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
* Remove obsolete TODOs from codegen testsCalin Juravle2014-10-231-3/+1
| | | | | | The features are already exercised by the art test 411-optimizing-arith. Change-Id: Id008931e0ed8206ced11ecc85a80a7e4aef3e68e
* Implement int bit-wise not operation in the optimizing compiler.Roland Levillain2014-10-231-0/+25
| | | | | | | | | | | | | | | | | | - Add support for the not-int (integer one's complement negate) instruction in the optimizing compiler. - Extend the HNot control-flow graph node type and make it inherit from HUnaryOperation. - Generate ARM, x86 and x86-64 code for integer HNeg nodes. - Exercise these additions in the codegen_test gtest, as there is not direct way to assess the support of not-int from a Java source. Indeed, compiling a Java expression such as `~a' using javac and then dx generates an xor-int/lit8 Dex instruction instead of the expected not-int Dex instruction. This is probably because the Java bytecode has an `ixor' instruction, but there's not instruction directly corresponding to a bit-wise not operation. Change-Id: I223aed75c4dac5785e04d99da0d22e8d699aee2b
* Minor fix in codegen tests.Calin Juravle2014-10-221-1/+1
| | | | Change-Id: I9b843536353d4f820b969895d5f75ee9b679aff0
* Add multiplication for integral typesCalin Juravle2014-10-171-0/+45
| | | | | | | This also fixes an issue where we could allocate a pair register even if one of its parts was already blocked. Change-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01
* Fix code generation of materialized conditions.Nicolas Geoffray2014-10-091-10/+103
| | | | | | | | | | | | | Move the logic for knowing if a condition needs to be materialized in an optimization pass (so that the information does not change as a side effect of another optimization). Also clean-up arm and x86_64 codegen: - arm: ldr and str are for power-users when a constant is in play. We should use LoadFromOffset and StoreToOffset. - x86_64: fix misuses of movq instead of movl. Change-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3
* Revert "Revert "Implement suspend checks in new compiler.""Nicolas Geoffray2014-09-161-0/+2
| | | | | | This reverts commit 7e3652c45c30c1f2f840e6088e24e2db716eaea7. Change-Id: Ib489440c34e41cba9e9e297054f9274f6e81a2d8
* Fix builds on archs the compiler does not support.Nicolas Geoffray2014-09-111-2/+0
| | | | Change-Id: Ibfc47026596c868fb6d48465a6e564a0b1e07fd0
* Fix valgrind errors.Nicolas Geoffray2014-09-111-16/+18
| | | | | | | | For now just stack allocate the code generator. Will think about cleaning up the root problem later (CodeGenerator being an arena object). Change-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7
* Make unit test tell if a method is a leaf.Nicolas Geoffray2014-07-221-3/+5
| | | | | | | | The runtime is not initialized completely in gtests, so we cannot run code (such as explicit stack overflow checks) that look at tls values. Change-Id: I74a4449b01eb203f1b411dda700e9459878d0d55
* Use the thumb2 assembler for the optimizing compiler.Nicolas Geoffray2014-07-161-4/+11
| | | | Change-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82
* Re-enable tests with the optimizing compiler.Nicolas Geoffray2014-06-261-4/+0
| | | | | | | | | | | Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Make SignalTest as crashing for optimizing. We need to implement stack overflow checks. Change-Id: Ieda575501eaf30af7aaa2c44e71544c9c467c24f
* Revert "Re-enable tests with the optimizing compiler."Nicolas Geoffray2014-06-251-0/+4
| | | | | | This reverts commit 20550910e608ed7d86db97927d2ce9d2191061a4. Change-Id: Ic28b719946c795378838a18162a2a2b2cf41a0e8
* Re-enable tests with the optimizing compiler.Nicolas Geoffray2014-06-251-4/+0
| | | | | | | | Tests run ok on my host/target. I reverted the move to using thumb2, because tests were crashing. But I could not reproduce file limits issues. Change-Id: I26bc4ec1eb6c227750d11210e012d9d3b1d824af
* Add some more instruction support to optimizing compiler.Dave Allison2014-06-241-1/+6
| | | | | | | | | | | | | | | This adds a few more DEX instructions to the optimizing compiler's builder (constants, moves, if_xx, etc). Also: * Changes the codegen for IF_XX instructions to use a condition rather than comparing a value against 0. * Fixes some instructions in the ARM disassembler. * Fixes PushList and PopList in the thumb2 assembler. * Switches the assembler for the optimizing compiler to thumb2 rather than ARM. Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
* Guard `Run` for platforms we're not compiling to, yet.Nicolas Geoffray2014-06-131-0/+2
| | | | Change-Id: I0dc210d2734e95714bed6c481a31fa4daabb9332
* Add x86_64 support to the optimizing compiler.Nicolas Geoffray2014-06-131-11/+19
| | | | Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
* Final CL to enable register allocation on x86.Nicolas Geoffray2014-06-121-2/+2
| | | | | | | | | | | | This CL implements: 1) Resolution after allocation: connecting the locations allocated to an interval within a block and between blocks. 2) Handling of fixed registers: some instructions require inputs/output to be at a specific location, and the allocator needs to deal with them in a special way. 3) ParallelMoveResolver::EmitNativeCode for x86. Change-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858
* Now we have a proper C++ library, use std::unique_ptr.Ian Rogers2014-05-191-1/+1
| | | | | | | Also remove the Android.libcxx.mk and other bits of stlport compatibility mechanics. Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
* Add support for adding two integers in optimizing compiler.Nicolas Geoffray2014-03-311-0/+38
| | | | Change-Id: I5524e193cd07f2692a57c6b4f8069904471b2928
* Plug new optimizing compiler in compilation pipeline.Nicolas Geoffray2014-03-181-10/+16
| | | | | | Also rename accessors to ART's conventions. Change-Id: I344807055b98aa4b27215704ec362191464acecc
* Fix non-{arm, x86} builds.Nicolas Geoffray2014-03-131-1/+4
| | | | Change-Id: If4c13775f8e1fd0fd26b4a731f3011c77b0bfed1
* More code generation for the optimizing compiler.Nicolas Geoffray2014-03-131-8/+77
| | | | | | | | | - Add HReturn instruction - Generate code for locals/if/return - Setup infrastructure for register allocation. Currently emulate a stack. Change-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb
* Add register support to the optimizing compiler.Nicolas Geoffray2014-03-101-28/+25
| | | | | | Also make if take an input and build the use list for instructions. Change-Id: I1938cee7dce5bd4c66b259fa2b431d2c79b3cf82
* Add codegen support to the optimizing compiler.Nicolas Geoffray2014-03-041-0/+124
Change-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-19 13:54:57 +0000