From 2bf1085d58c3c934be1873f758ddce626601297a Mon Sep 17 00:00:00 2001 From: Kalyani Chidambaram Date: Wed, 19 Dec 2018 11:06:14 -0800 Subject: Tegra: remove support for SEPARATE_CODE_AND_RODATA=0 Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0. This patch uses the common macros provided by bl_common.h as a result and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set to '1'. Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e Signed-off-by: Kalyani Chidambaram --- plat/nvidia/tegra/common/tegra_bl31_setup.c | 17 +++++------------ plat/nvidia/tegra/include/platform_def.h | 8 ++++++++ 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 46686c368..05890772e 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -39,15 +39,8 @@ * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ - IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); -static const uint64_t BL31_RW_END = BL_END; -static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; -static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; -static const uint64_t TEXT_START = BL_CODE_BASE; -static const uint64_t TEXT_END = BL_CODE_END; - extern uint64_t tegra_bl31_phys_base; static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; @@ -314,11 +307,11 @@ void bl31_plat_runtime_setup(void) void bl31_plat_arch_setup(void) { uint64_t rw_start = BL31_RW_START; - uint64_t rw_size = BL31_RW_END - BL31_RW_START; - uint64_t rodata_start = BL31_RODATA_BASE; - uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - uint64_t code_base = TEXT_START; - uint64_t code_size = TEXT_END - TEXT_START; + uint64_t rw_size = BL_END - BL31_RW_START; + uint64_t rodata_start = BL_RO_DATA_BASE; + uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; + uint64_t code_base = BL_CODE_BASE; + uint64_t code_size = BL_CODE_END - BL_CODE_BASE; const mmap_region_t *plat_mmio_map = NULL; #if USE_COHERENT_MEM uint32_t coh_start, coh_size; diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index eb55def4a..817f480a2 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -12,6 +12,13 @@ #include +/******************************************************************************* + * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 + ******************************************************************************/ +#if !SEPARATE_CODE_AND_RODATA +#error "SEPARATE_CODE_AND_RODATA should be set to 1" +#endif + /* * Platform binary types for linking */ @@ -72,4 +79,5 @@ #define MAX_IO_DEVICES U(0) #define MAX_IO_HANDLES U(0) + #endif /* PLATFORM_DEF_H */ -- cgit v1.2.3 From a5bfcad8518f84beb250ea697b71e5fc7c0cf3a5 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 21 Dec 2018 10:53:53 -0800 Subject: Tegra: include missing stdbool.h This patch includes the missing stdbool.h header from flowctrl.h and bpmp_ivc.c files. Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c | 1 + plat/nvidia/tegra/include/drivers/flowctrl.h | 3 +++ 2 files changed, 4 insertions(+) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c index 57daf6aeb..d964fc001 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h index 54336b044..e5ab600b4 100644 --- a/plat/nvidia/tegra/include/drivers/flowctrl.h +++ b/plat/nvidia/tegra/include/drivers/flowctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +10,8 @@ #include +#include + #include #define FLOWCTRL_HALT_CPU0_EVENTS (0x0U) -- cgit v1.2.3 From 42080d489231614a19865c5b6b962e55e94c6f5a Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 21 Dec 2018 10:55:42 -0800 Subject: Tegra: remove circular dependency with common_def.h This patch stops including common_def.h from platform_def.h to fix a circular depoendency between them. This means platform_def.h now has to define the linker macros: * PLATFORM_LINKER_FORMAT * PLATFORM_LINKER_ARCH Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/include/platform_def.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'plat') diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 817f480a2..8a8a0d268 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +26,12 @@ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 +/* + * Platform binary types for linking + */ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + /******************************************************************************* * Generic platform constants ******************************************************************************/ -- cgit v1.2.3 From aba5dddc62c5db79e0bcc033376a98db84665a33 Mon Sep 17 00:00:00 2001 From: Kalyani Chidambaram Date: Tue, 18 Dec 2018 13:51:18 -0800 Subject: Tegra: remove support for USE_COHERENT_MEM This patch removes the support for 'USE_COHERENT_MEM' as Tegra platforms no longer support the feature. Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4ec Signed-off-by: Kalyani Chidambaram --- plat/nvidia/tegra/common/tegra_bl31_setup.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 05890772e..269afb196 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -313,9 +313,6 @@ void bl31_plat_arch_setup(void) uint64_t code_base = BL_CODE_BASE; uint64_t code_size = BL_CODE_END - BL_CODE_BASE; const mmap_region_t *plat_mmio_map = NULL; -#if USE_COHERENT_MEM - uint32_t coh_start, coh_size; -#endif const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); /* @@ -342,15 +339,6 @@ void bl31_plat_arch_setup(void) code_size, MT_CODE | MT_SECURE); -#if USE_COHERENT_MEM - coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); - coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; - - mmap_add_region(coh_start, coh_start, - coh_size, - (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); -#endif - /* map TZDRAM used by BL31 as coherent memory */ if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { mmap_add_region(params_from_bl2->tzdram_base, -- cgit v1.2.3 From 9b51aa87a741ebabe02de758bd3a83712ddc44a4 Mon Sep 17 00:00:00 2001 From: Ken Chang Date: Fri, 28 Dec 2018 08:44:12 +0800 Subject: Tegra: memctrl: map video memory as uncached Memmap video memory as uncached normal memory by adding flag 'MT_NON_CACHEABLE' in mmap_add_dynamic_region(). This improves the time taken for clearing the non-overlapping video memory: test conditions: 32MB memory size, EMC running at 1866MHz, t186 1) without MT_NON_CACHEABLE: 30ms ~ 40ms <3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000 <3>[ 133.860471] _tegra_set_vpr_params[120]: begin <3>[ 133.896481] _tegra_set_vpr_params[123]: end <3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000 <3>[ 133.916397] _tegra_set_vpr_params[120]: begin <3>[ 133.956369] _tegra_set_vpr_params[123]: end <3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000 <3>[ 133.977934] _tegra_set_vpr_params[120]: begin <3>[ 134.013874] _tegra_set_vpr_params[123]: end <3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000 <3>[ 134.033512] _tegra_set_vpr_params[120]: begin <3>[ 134.065996] _tegra_set_vpr_params[123]: end <3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000 <3>[ 134.082923] _tegra_set_vpr_params[120]: begin <3>[ 134.113119] _tegra_set_vpr_params[123]: end <3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000 <3>[ 134.130790] _tegra_set_vpr_params[120]: begin <3>[ 134.162523] _tegra_set_vpr_params[123]: end <3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000 <3>[ 134.179772] _tegra_set_vpr_params[120]: begin <3>[ 134.209142] _tegra_set_vpr_params[123]: end 2) with MT_NON_CACHEABLE: 10ms ~ 18ms <3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000 <3>[ 102.116296] _tegra_set_vpr_params[120]: begin <3>[ 102.134272] _tegra_set_vpr_params[123]: end <3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000 <3>[ 102.153226] _tegra_set_vpr_params[120]: begin <3>[ 102.164201] _tegra_set_vpr_params[123]: end <3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000 <3>[ 102.179638] _tegra_set_vpr_params[120]: begin <3>[ 102.190342] _tegra_set_vpr_params[123]: end <3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000 <3>[ 102.205085] _tegra_set_vpr_params[120]: begin <3>[ 102.216112] _tegra_set_vpr_params[123]: end <3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000 <3>[ 102.231387] _tegra_set_vpr_params[120]: begin <3>[ 102.241775] _tegra_set_vpr_params[123]: end <3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000 <3>[ 102.256069] _tegra_set_vpr_params[120]: begin <3>[ 102.266368] _tegra_set_vpr_params[123]: end <3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000 <3>[ 102.280672] _tegra_set_vpr_params[120]: begin <3>[ 102.290929] _tegra_set_vpr_params[123]: end Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a Signed-off-by: Ken Chang --- plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c | 5 +++-- plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index 92fa273b5..c3f95db4d 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -117,7 +117,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ non_overlap_area_start, /* VA */ non_overlap_area_size, /* size */ - MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ + MT_NS | MT_RW | MT_EXECUTE_NEVER | + MT_NON_CACHEABLE); /* attrs */ assert(ret == 0); zeromem((void *)non_overlap_area_start, non_overlap_area_size); diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index a53f66078..2d91cb290 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -348,7 +348,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ non_overlap_area_start, /* VA */ non_overlap_area_size, /* size */ - MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ + MT_NS | MT_RW | MT_EXECUTE_NEVER | + MT_NON_CACHEABLE); /* attrs */ assert(ret == 0); zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); -- cgit v1.2.3 From 8f0e22d56092ff104ddfe7cbb86c003261bfdb67 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 10 Dec 2018 13:28:25 -0800 Subject: Tegra194: SiP function ID to read SMMU_PER registers This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER error records from all supported SMMU blocks. The register values are passed over to the client via CPU registers X1 - X3, where X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0] X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2] X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4] Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 36 +++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 33694a16d..884762de7 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -16,11 +16,13 @@ #include #include #include +#include #include /******************************************************************************* * Tegra194 SiP SMCs ******************************************************************************/ +#define TEGRA_SIP_GET_SMMU_PER 0xC200FF00U /******************************************************************************* * This function is responsible for handling all T194 SiP calls @@ -34,13 +36,43 @@ int32_t plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - int32_t ret = -ENOTSUP; + int32_t ret = 0; + uint32_t i, smmu_per[6] = {0}; + uint32_t num_smmu_devices = plat_get_num_smmu_devices(); + uint64_t per[3] = {0ULL}; - (void)smc_fid; (void)x1; (void)x4; (void)cookie; (void)flags; + switch (smc_fid) { + case TEGRA_SIP_GET_SMMU_PER: + + /* make sure we dont go past the array length */ + assert(num_smmu_devices <= ARRAY_SIZE(smmu_per)); + + /* read all supported SMMU_PER records */ + for (i = 0U; i < num_smmu_devices; i++) { + smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER); + } + + /* pack results into 3 64bit variables. */ + per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U); + per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U); + per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U); + + /* provide the results via X1-X3 CPU registers */ + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); + + break; + + default: + ret = -ENOTSUP; + break; + } + return ret; } -- cgit v1.2.3 From ebe076da237878822fb6e335dda00d3cb03853d1 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 28 Jan 2019 17:00:32 -0800 Subject: Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to 'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this is a Tegra feature. Change-Id: I5c4431e662223ee80efbfd5ec2513f8b1cadfc50 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/platform.mk | 4 ++-- plat/nvidia/tegra/soc/t210/platform_t210.mk | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index 14b99130c..87588202c 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -40,7 +40,7 @@ OVERRIDE_LIBC := 1 # Flag to enable WDT FIQ interrupt handling for Tegra SoCs # prior to Tegra186 -ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0 +ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING ?= 0 # Flag to allow relocation of BL32 image to TZDRAM during boot RELOCATE_BL32_IMAGE ?= 0 @@ -48,7 +48,7 @@ RELOCATE_BL32_IMAGE ?= 0 include plat/nvidia/tegra/common/tegra_common.mk include ${SOC_DIR}/platform_${TARGET_SOC}.mk -$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING)) +$(eval $(call add_define,ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING)) $(eval $(call add_define,RELOCATE_BL32_IMAGE)) # modify BUILD_PLAT to point to SoC specific build directory diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index ba827a073..a5662be02 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -23,8 +23,7 @@ $(eval $(call add_define,MAX_XLAT_TABLES)) MAX_MMAP_REGIONS := 16 $(eval $(call add_define,MAX_MMAP_REGIONS)) -ENABLE_WDT_LEGACY_FIQ_HANDLING := 1 -$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING)) +ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1 PLAT_INCLUDES += -I${SOC_DIR}/drivers/se -- cgit v1.2.3 From eeb1b5e36849b0de529ba220ed20c3146e6584b6 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 17 Jan 2019 16:36:23 -0800 Subject: Tegra: include platform headers from individual makefiles This patch modifies PLAT_INCLUDES to include individual Tegra SoC headers from the platform's makefile. Change-Id: If5248667f4e58ac18727d37a18fbba8e53f2d7b5 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/tegra_common.mk | 3 +-- plat/nvidia/tegra/soc/t132/platform_t132.mk | 3 +++ plat/nvidia/tegra/soc/t186/platform_t186.mk | 3 ++- plat/nvidia/tegra/soc/t194/platform_t194.mk | 3 ++- plat/nvidia/tegra/soc/t210/platform_t210.mk | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 66d037fdf..c946a7597 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -6,8 +6,7 @@ PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \ -Iplat/nvidia/tegra/include/lib \ - -Iplat/nvidia/tegra/include \ - -Iplat/nvidia/tegra/include/${TARGET_SOC} + -Iplat/nvidia/tegra/include include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index 183e1889c..16bd0ead2 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -20,6 +20,9 @@ $(eval $(call add_define,MAX_XLAT_TABLES)) MAX_MMAP_REGIONS := 8 $(eval $(call add_define,MAX_MMAP_REGIONS)) +# platform files +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132 + BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk index c17dab2bd..a5341236d 100644 --- a/plat/nvidia/tegra/soc/t186/platform_t186.mk +++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk @@ -37,7 +37,8 @@ MAX_MMAP_REGIONS := 27 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -PLAT_INCLUDES += -I${SOC_DIR}/drivers/include +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \ + -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 78766fcbe..9ee9138b4 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -37,7 +37,8 @@ MAX_MMAP_REGIONS := 30 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -PLAT_INCLUDES += -I${SOC_DIR}/drivers/include +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ + -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index a5662be02..14e3324a8 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -25,7 +25,8 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1 -PLAT_INCLUDES += -I${SOC_DIR}/drivers/se +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \ + -I${SOC_DIR}/drivers/se BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/cortex_a53.S \ -- cgit v1.2.3 From 713769515f66add17f2a874311619a9874d088ae Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 23 Jan 2019 16:54:12 -0800 Subject: Tegra: memctrl_v2: remove support to secure TZSRAM This patch removes support to secure the on-chip TZSRAM memory for Tegra186 and Tegra194 platforms as the previous bootloader does that for them. Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07 Signed-off-by: Varun Wadekar --- .../tegra/common/drivers/memctrl/memctrl_v2.c | 64 +--------------------- plat/nvidia/tegra/include/drivers/mce.h | 3 +- plat/nvidia/tegra/soc/t186/drivers/mce/mce.c | 9 +-- plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 19 ------- 4 files changed, 3 insertions(+), 92 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index 2d91cb290..5555f5df3 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -159,69 +159,7 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) */ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) { - uint32_t index; - uint32_t total_128kb_blocks = size_in_bytes >> 17; - uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; - uint32_t val; - - INFO("Configuring TrustZone SRAM Memory Carveout\n"); - - /* - * Reset the access configuration registers to restrict access - * to the TZRAM aperture - */ - for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0; - index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); - index += 4U) { - tegra_mc_write_32(index, 0); - } - - /* - * Enable CPU access configuration registers to access the TZRAM aperture - */ - if (!tegra_chipid_is_t186()) { - val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0); - val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW; - tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val); - } - - /* - * Set the TZRAM base. TZRAM base must be 4k aligned, at least. - */ - assert((phys_base & (uint64_t)0xFFF) == 0U); - tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); - tegra_mc_write_32(MC_TZRAM_BASE_HI, - (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); - - /* - * Set the TZRAM size - * - * total size = (number of 128KB blocks) + (number of remaining 4KB - * blocks) - * - */ - val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | - total_128kb_blocks; - tegra_mc_write_32(MC_TZRAM_SIZE, val); - - /* - * Lock the configuration settings by disabling TZ-only lock - * and locking the configuration against any future changes - * at all. - */ - val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); - val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; - val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; - if (!tegra_chipid_is_t186()) { - val |= MC_GSC_ENABLE_CPU_SECURE_BIT; - } - tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); - - /* - * MCE propagates the security configuration values across the - * CCPLEX. - */ - mce_update_gsc_tzram(); + ; /* do nothing */ } /* diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h index 4470b6b8b..5f1bb4f28 100644 --- a/plat/nvidia/tegra/include/drivers/mce.h +++ b/plat/nvidia/tegra/include/drivers/mce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,7 +69,6 @@ int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); -int mce_update_gsc_tzram(void); __dead2 void mce_enter_ccplex_state(uint32_t state_idx); void mce_update_cstate_info(const mce_cstate_info_t *cstate); void mce_verify_firmware_version(void); diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index 9e42b2bcb..54d3b2ccd 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -385,14 +386,6 @@ int32_t mce_update_gsc_tzdram(void) return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX); } -/******************************************************************************* - * Handler to update carveout values for TZ SysRAM aperture - ******************************************************************************/ -int32_t mce_update_gsc_tzram(void) -{ - return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM); -} - /******************************************************************************* * Handler to shutdown/reset the entire system ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 00c671bcc..7edd7a09e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -115,25 +115,6 @@ int32_t mce_update_gsc_tzdram(void) return ret; } -/******************************************************************************* - * Handler to update carveout values for TZ SysRAM aperture - ******************************************************************************/ -int32_t mce_update_gsc_tzram(void) -{ - int32_t ret; - - /* - * MCE firmware is not running on simulation platforms. - */ - if (mce_firmware_not_supported()) { - ret = -EINVAL; - } else { - ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM); - } - - return ret; -} - /******************************************************************************* * Handler to issue the UPDATE_CSTATE_INFO request ******************************************************************************/ -- cgit v1.2.3 From 36e263753694fbe881110c85701e8245f5538491 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 7 Jan 2019 12:02:09 +0530 Subject: Tegra: memctrl: cleanup streamid override registers Streamid override registers are passed to memctrl to program bypass streamid for all the registers. There is no reason to bypass SMMU for any of the client so need to remove register list and do not set streamid_override_cfg. Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC bypass as of now. Will revisit once these issues are fixed. Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934 Signed-off-by: Pritesh Raithatha --- plat/nvidia/tegra/soc/t186/plat_memctrl.c | 64 ------------- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 146 ------------------------------ 2 files changed, 210 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c index 7ff7e77d9..4eb68e44a 100644 --- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c @@ -21,29 +21,6 @@ extern uint64_t tegra_bl31_phys_base; * Array to hold stream_id override config register offsets ******************************************************************************/ const static uint32_t tegra186_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, - MC_STREAMID_OVERRIDE_CFG_AFIR, - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_AFIW, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_GPUSRD, - MC_STREAMID_OVERRIDE_CFG_GPUSWR, MC_STREAMID_OVERRIDE_CFG_SDMMCRA, MC_STREAMID_OVERRIDE_CFG_SDMMCRAA, MC_STREAMID_OVERRIDE_CFG_SDMMCR, @@ -52,47 +29,6 @@ const static uint32_t tegra186_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_SDMMCWAA, MC_STREAMID_OVERRIDE_CFG_SDMMCW, MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_GPUSRD2, - MC_STREAMID_OVERRIDE_CFG_GPUSWR2, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 }; /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 2d5f8e3c6..9a4d22e68 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -11,150 +11,6 @@ #include #include -/******************************************************************************* - * Array to hold stream_id override config register offsets - ******************************************************************************/ -const static uint32_t tegra194_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPFALR, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRA, - MC_STREAMID_OVERRIDE_CFG_SDMMCR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, - MC_STREAMID_OVERRIDE_CFG_SDMMCWA, - MC_STREAMID_OVERRIDE_CFG_SDMMCW, - MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_AXIAPR, - MC_STREAMID_OVERRIDE_CFG_AXIAPW, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, - MC_STREAMID_OVERRIDE_CFG_VIFALR, - MC_STREAMID_OVERRIDE_CFG_VIFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA0WRA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA1WRA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDC, - MC_STREAMID_OVERRIDE_CFG_PVA0WRA, - MC_STREAMID_OVERRIDE_CFG_PVA0WRB, - MC_STREAMID_OVERRIDE_CFG_PVA0WRC, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB, - MC_STREAMID_OVERRIDE_CFG_PVA1RDC, - MC_STREAMID_OVERRIDE_CFG_PVA1WRA, - MC_STREAMID_OVERRIDE_CFG_PVA1WRB, - MC_STREAMID_OVERRIDE_CFG_PVA1WRC, - MC_STREAMID_OVERRIDE_CFG_RCER, - MC_STREAMID_OVERRIDE_CFG_RCEW, - MC_STREAMID_OVERRIDE_CFG_RCEDMAR, - MC_STREAMID_OVERRIDE_CFG_RCEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, - MC_STREAMID_OVERRIDE_CFG_PCIE0R, - MC_STREAMID_OVERRIDE_CFG_PCIE0W, - MC_STREAMID_OVERRIDE_CFG_PCIE1R, - MC_STREAMID_OVERRIDE_CFG_PCIE1W, - MC_STREAMID_OVERRIDE_CFG_PCIE2AR, - MC_STREAMID_OVERRIDE_CFG_PCIE2AW, - MC_STREAMID_OVERRIDE_CFG_PCIE3R, - MC_STREAMID_OVERRIDE_CFG_PCIE3W, - MC_STREAMID_OVERRIDE_CFG_PCIE4R, - MC_STREAMID_OVERRIDE_CFG_PCIE4W, - MC_STREAMID_OVERRIDE_CFG_PCIE5R, - MC_STREAMID_OVERRIDE_CFG_PCIE5W, - MC_STREAMID_OVERRIDE_CFG_ISPFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, - MC_STREAMID_OVERRIDE_CFG_PCIE5R1, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, - MC_STREAMID_OVERRIDE_CFG_ISPRA1, - MC_STREAMID_OVERRIDE_CFG_PCIE0R1, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR, - MC_STREAMID_OVERRIDE_CFG_MIU0R, - MC_STREAMID_OVERRIDE_CFG_MIU0W, - MC_STREAMID_OVERRIDE_CFG_MIU1R, - MC_STREAMID_OVERRIDE_CFG_MIU1W, - MC_STREAMID_OVERRIDE_CFG_MIU2R, - MC_STREAMID_OVERRIDE_CFG_MIU2W, - MC_STREAMID_OVERRIDE_CFG_MIU3R, - MC_STREAMID_OVERRIDE_CFG_MIU3W, - MC_STREAMID_OVERRIDE_CFG_MIU4R, - MC_STREAMID_OVERRIDE_CFG_MIU4W, - MC_STREAMID_OVERRIDE_CFG_MIU5R, - MC_STREAMID_OVERRIDE_CFG_MIU5W, - MC_STREAMID_OVERRIDE_CFG_MIU6R, - MC_STREAMID_OVERRIDE_CFG_MIU6W, - MC_STREAMID_OVERRIDE_CFG_MIU7R, - MC_STREAMID_OVERRIDE_CFG_MIU7W -}; - /******************************************************************************* * Array to hold the security configs for stream IDs ******************************************************************************/ @@ -571,8 +427,6 @@ static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) * Struct to hold the memory controller settings ******************************************************************************/ static tegra_mc_settings_t tegra194_mc_settings = { - .streamid_override_cfg = tegra194_streamid_override_regs, - .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx -- cgit v1.2.3 From a45c3e9d81c0c8f3ab4a1724bf2f7373464f021e Mon Sep 17 00:00:00 2001 From: sumitg Date: Fri, 8 Feb 2019 16:14:06 +0530 Subject: Tegra210: trigger CPU0 hotplug power on using FC Hotplug poweron is not working for boot CPU as it's being triggerred using PMC and not with Flow Controller. This is happening because "cpu_powergate_mask" is only getting set for non-boot CPU's as the boot CPU's first bootup follows different code path. The patch is marking a CPU as ON within "cpu_powergate_mask" when turning its power domain on during power on. This will ensure only first bootup on all CPU's is using PMC and subsequent hotplug poweron will be using Flow Controller. Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2 Signed-off-by: sumitg --- plat/nvidia/tegra/soc/t210/plat_psci_handlers.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index f29e624ea..7f73ea506 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -533,6 +533,13 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) } } + /* + * Mark this CPU as ON in the cpu_powergate_mask[], + * so that we use Flow Controller for all subsequent + * power ups. + */ + cpu_powergate_mask[plat_my_core_pos()] = 1; + /* * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's * used for power management and boot purposes. Inform the BPMP that @@ -561,7 +568,6 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) /* Turn on CPU using flow controller or PMC */ if (cpu_powergate_mask[cpu] == 0) { tegra_pmc_cpu_on(cpu); - cpu_powergate_mask[cpu] = 1; } else { tegra_fc_cpu_on(cpu); } -- cgit v1.2.3 From 7644e2aa6ecd110e213bdb422c2df0ce6290c0a0 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 5 Oct 2018 11:24:54 -0700 Subject: Tegra: gicv2: initialize target masks This patch initializes the target masks in the GICv2 driver data, for all PEs. This will allow platforms to set the PE target for SPIs. Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/tegra_gicv2.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c index 293df8d4f..012107e3b 100644 --- a/plat/nvidia/tegra/common/tegra_gicv2.c +++ b/plat/nvidia/tegra/common/tegra_gicv2.c @@ -1,20 +1,23 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include - #include #include #include #include +#include #include #include +static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT]; + /****************************************************************************** * Tegra common helper to setup the GICv2 driver data. *****************************************************************************/ @@ -33,6 +36,8 @@ void tegra_gic_setup(const interrupt_prop_t *interrupt_props, tegra_gic_data.gicc_base = TEGRA_GICC_BASE; tegra_gic_data.interrupt_props = interrupt_props; tegra_gic_data.interrupt_props_num = interrupt_props_num; + tegra_gic_data.target_masks = tegra_target_masks; + tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks); gicv2_driver_init(&tegra_gic_data); } @@ -43,6 +48,7 @@ void tegra_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } @@ -61,5 +67,6 @@ void tegra_gic_cpuif_deactivate(void) void tegra_gic_pcpu_init(void) { gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } -- cgit v1.2.3 From 9aaa8882eb62034d88eef30171ad1af01ca47b7b Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Mon, 11 Mar 2019 15:50:32 +0800 Subject: Tegra194: move cluster and CPU counter to header file. MISRA rules request that the cluster and CPU counter be unsigned values and have a suffix 'U'. If the define located in the makefile, this cannot be done. This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER macros to tegra_def.h as a result. Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/include/platform_def.h | 2 +- plat/nvidia/tegra/include/t194/tegra_def.h | 6 ++++++ plat/nvidia/tegra/soc/t194/platform_t194.mk | 6 ------ 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'plat') diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 8a8a0d268..91a24ca7e 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -47,7 +47,7 @@ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ - PLATFORM_CLUSTER_COUNT + 1) + PLATFORM_CLUSTER_COUNT + U(1)) /******************************************************************************* * Platform console related constants diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index dc0644514..e39f9cad6 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -9,6 +9,12 @@ #include +/******************************************************************************* + * Chip specific cluster and cpu numbers + ******************************************************************************/ +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) + /******************************************************************************* * Chip specific page table and MMU setup constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 9ee9138b4..c02128ccc 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -24,12 +24,6 @@ COLD_BOOT_SINGLE_CPU := 1 TZDRAM_BASE := 0x40000000 $(eval $(call add_define,TZDRAM_BASE)) -PLATFORM_CLUSTER_COUNT := 4 -$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) - -PLATFORM_MAX_CPUS_PER_CLUSTER := 2 -$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) - MAX_XLAT_TABLES := 25 $(eval $(call add_define,MAX_XLAT_TABLES)) -- cgit v1.2.3