From fd4bb0ad4b2403156c62dea2ae7c1e02c19e79bf Mon Sep 17 00:00:00 2001
From: John Tsichritzis <john.tsichritzis@arm.com>
Date: Tue, 19 Feb 2019 13:54:21 +0000
Subject: Rename Cortex-Helios filenames to Neoverse E1

Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
---
 lib/cpus/aarch64/cortex_helios.S | 44 ----------------------------------------
 lib/cpus/aarch64/neoverse_e1.S   | 44 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 44 deletions(-)
 delete mode 100644 lib/cpus/aarch64/cortex_helios.S
 create mode 100644 lib/cpus/aarch64/neoverse_e1.S

(limited to 'lib')

diff --git a/lib/cpus/aarch64/cortex_helios.S b/lib/cpus/aarch64/cortex_helios.S
deleted file mode 100644
index 7d3d7e45c..000000000
--- a/lib/cpus/aarch64/cortex_helios.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <cortex_helios.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-func cortex_helios_cpu_pwr_dwn
-	mrs	x0, CORTEX_HELIOS_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_HELIOS_CPUPWRCTLR_EL1, x0
-	isb
-	ret
-endfunc cortex_helios_cpu_pwr_dwn
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Helios. Must follow AAPCS.
- */
-func cortex_helios_errata_report
-	ret
-endfunc cortex_helios_errata_report
-#endif
-
-
-.section .rodata.cortex_helios_regs, "aS"
-cortex_helios_regs:  /* The ascii list of register names to be reported */
-	.asciz	"cpuectlr_el1", ""
-
-func cortex_helios_cpu_reg_dump
-	adr	x6, cortex_helios_regs
-	mrs	x8, CORTEX_HELIOS_ECTLR_EL1
-	ret
-endfunc cortex_helios_cpu_reg_dump
-
-declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \
-	CPU_NO_RESET_FUNC, \
-	cortex_helios_cpu_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
new file mode 100644
index 000000000..7d3d7e45c
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <cortex_helios.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+func cortex_helios_cpu_pwr_dwn
+	mrs	x0, CORTEX_HELIOS_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_HELIOS_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_helios_cpu_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Helios. Must follow AAPCS.
+ */
+func cortex_helios_errata_report
+	ret
+endfunc cortex_helios_errata_report
+#endif
+
+
+.section .rodata.cortex_helios_regs, "aS"
+cortex_helios_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_helios_cpu_reg_dump
+	adr	x6, cortex_helios_regs
+	mrs	x8, CORTEX_HELIOS_ECTLR_EL1
+	ret
+endfunc cortex_helios_cpu_reg_dump
+
+declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \
+	CPU_NO_RESET_FUNC, \
+	cortex_helios_cpu_pwr_dwn
-- 
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